static void mmi_em_misc_rf_desense_mode_ssc8(void) {
rf_desense_set_curr_mode(RF_DESENSE_MODE_SSC8);
#if defined(FEATURE_DCM_SSC)
custom_DynamicClockSwitch(SSC_MCU_LOW_SPEED2);
#endif /* FEATURE_DCM_SSC */
}
void DCM_Recovery(void)
{ /* For MT6217/MT6227: back to 52MHz; For MT6228/MT6229: back to 104MHz */
volatile kal_uint16 i,j=0;
if( dcm_state == 2 )
{
#if ((IS_CHIP_MT6228) || (IS_CHIP_MT6229)||(IS_CHIP_MT6235) || (IS_CHIP_MT6238))
/* Gate GMC DMA */
kal_uint32 tmp;
#endif
/* mtk01940
======================================
Idle Dedi
MT6217 13MHz x
MT6229 26MHz 26MHz
MT6227 13MHZ 26MHz
MT6223 13MHz 13MHz
MT6225
MT6228
MT6229
======================================
*/
#if (IS_CHIP_MT6227 || IS_CHIP_MT6228)
#ifdef MT6227D
EXT_ASSERT( *MCUCLK_CON == 0x0000,0,0,0 ); //13MHz
#else
if(dcm.isIdleMode)
{
EXT_ASSERT( *MCUCLK_CON == 0x0000,0,0,0 ); //13MHz
}
else
{
#if (IS_CHIP_MT6228)
EXT_ASSERT( *MCUCLK_CON == 0x0101,0,0,0 ); //26MHz for MT6228
#else
EXT_ASSERT( *MCUCLK_CON == 0x0001,0,0,0 ); //26MHz for MT6227
#endif
}
#endif
#elif (IS_CHIP_MT6229)
EXT_ASSERT( *MCUCLK_CON == 0x0101,0,0,0 ); //26MHz
#elif (IS_CHIP_MT6238)
EXT_ASSERT( *MCUCLK_CON == 0x7000,0,0,0 ); //13MHz
#else
EXT_ASSERT( *MCUCLK_CON == 0x0000,0,0,0 ); //13MHz
#endif
/* mtk01940 */
dcm_state = 3; /* DCM @ 13/26->104/52MHz */
#if ((IS_CHIP_MT6228) || (IS_CHIP_MT6229)||(IS_CHIP_MT6235)||(IS_CHIP_MT6238))
/* Gate GMC DMA */
tmp = GateDG();
for (i = 0; i < 20; i++)
;
#endif
/* I_Bit is disabled and Wait until EMI access is complete.
Otherwise, some external(Burst/Async/Sync RAM), some will get problems. */
#if ( (IS_CHIP_MT6238) || (IS_CHIP_MT6235) )
j = *(volatile kal_uint16 *)0x28000000;
#else
j = *(volatile kal_uint16 *)0x24000000;
#endif
/*A26=1 means will not get data via data cache, it will access EMI directly.*/
/* Change WS and clock rate. */
#if ((IS_CHIP_MT6228) || (IS_CHIP_MT6229) || (IS_CHIP_MT6225))
custom_DynamicClockSwitch( MCU_104MHZ );
#elif ((IS_CHIP_MT6217)|| (IS_CHIP_MT6227)|| (IS_CHIP_MT6223))
custom_DynamicClockSwitch( MCU_52MHZ );
#elif ((IS_CHIP_MT6238)|| (IS_CHIP_MT6235))
custom_DynamicClockSwitch( MCU_208MHZ );
#endif
#if ( (IS_CHIP_MT6228) || (IS_CHIP_MT6229)||(IS_CHIP_MT6238)|| (IS_CHIP_MT6235))
/* Recover GMC DMA gating */
UngateDG(tmp);
#endif
dcm_state = 0; /* DCM @ 104/52MHz */
dcm_excuted = true;/* Record the execution of DCM and print in L1SM_FrameTick */
}
}
static void mmi_em_misc_rf_desense_mode_ssc7(void) {
rf_desense_set_curr_mode(RF_DESENSE_MODE_SSC7);
#if defined(FEATURE_DCM_SSC)
custom_DynamicClockSwitch(SSC_COMBINATION);
#endif /* FEATURE_DCM_SSC */
}
/* Note that idle task is only created when MTK_SLEEP_ENABLE is defined. */
void IdleTask( task_entry_struct * task_entry_ptr )
{
#if defined(KAL_ON_NUCLEUS)
IdleTaskTCB = (NU_TASK*)task_info_g[task_entry_ptr->task_indx].task_id;
#elif defined(KAL_ON_THREADX)
IdleTaskTCB = (TX_THREAD *)task_info_g[task_entry_ptr->task_indx].task_id;
#endif
while(1)
{
/* Partial sleep mode for MCU and AVB block.
To force MCU and AVB bus CLK stopped when system is in idle task.
System will run again and CLK resume automatically only when IRQ comes.
*/
#if defined(MTK_SLEEP_ENABLE) || defined(L1D_TEST)
#if defined( DCM_ENABLE )
kal_uint32 _savedMask;
volatile kal_uint16 i,j=0;
register kal_uint32 start, end, duration, tqwrap;
_savedMask = LockIRQ();
start = *((volatile kal_uint16 *)(TDMA_base + 0x00));
/* Check if DMA, GMC and LCD_DMA is in Power Down Mode. */
if (
#if (IS_CHIP_MT6229)
(((*(volatile kal_uint32 *)0x80030000) & 0x00055555)==0) && /* Check DMA1~10, ignore DMA11~14 */
(((*PDN_CON0) & 0x0078) == 0x0078) && /* Check PDN_CON0 IRDMA, PPP, CHE, and WAVETABLE down */
((*PDN_CON1) & 0x0080) && /* Check PDN_CON1 LCD down */
((*PDN_CON3) == 0xFFFF) && /* Check PDN_CON3 all down [GMC]*/
*MCUCLK_CON == 0x0703 &&
#elif ( (IS_CHIP_MT6238) || (IS_CHIP_MT6235) ) //add by jerry
(((*DMA_GLBSTA) & 0x00055555)==0) && /* Check DMA1~10, ignore DMA11~14 */
(((*PDN_CON0) & 0x0078) == 0x0078) && /* Check PDN_CON0 IRDMA, PPP, CHE, and WAVETABLE down */
((*PDN_CON1) & 0x0080) && /* Check PDN_CON1 LCD down */
((*PDN_CON3) == 0xFFFF) && /* Check PDN_CON3 all down [GMC]*/
*MCUCLK_CON == 0x7F37 && /*EMICLK,ARMCLK,AHBX4CLK,AHBX8CLK,104,208,52,104*/
#elif (IS_CHIP_MT6228)
(((*(volatile kal_uint32 *)0x80030000) & 0x00055555)==0) && /* Check DMA1~10, ignore DMA11~14 */
(((*PDN_CON0) & 0x0038) == 0x0038) && /* Check PDN_CON0 PPP, CHE, and WAVETABLE down */
((*PDN_CON1) & 0x0080) && /* Check PDN_CON1 LCD down */
((*PDN_CON3) == 0xFFFF) && /* Check PDN_CON3 all down [GMC]*/
*MCUCLK_CON == 0x0703 &&
#elif ( IS_CHIP_MT6223)
(((*(volatile kal_uint32 *)0x80030000) & 0x00055555)==0) && /* Check DMA1~10, ignore DMA11~14 */
(((*PDN_CON0) & 0x0048) == 0x0048) && /* Check PDN_CON0 IRDMA, and WAVETABLE down */
((*PDN_CON1) & 0x0080) && /* Check PDN_CON1 LCD down */
((*PDN_CON3) == 0x0001) && /* Check PDN_CON3 all down [GMC]*/
*MCUCLK_CON == 0x0303 &&
#elif ( IS_CHIP_MT6225)
(((*(volatile kal_uint32 *)0x80030000) & 0x00055555)==0) && /* Check DMA1~10, ignore DMA11~14 */
(((*PDN_CON0) & 0x0048) == 0x0048) && /* Check PDN_CON0 IRDMA, and WAVETABLE down */
((*PDN_CON1) & 0x0080) && /* Check PDN_CON1 LCD down */
((*PDN_CON3) == 0x1801) && /* Check PDN_CON3 all down [GMC]*/
*MCUCLK_CON == 0x0703 &&
#elif ( IS_CHIP_MT6227)
(((*(volatile kal_uint32 *)0x80030000) & 0x00055555)==0) && /* Check DMA1~10, ignore DMA11~14 */
((*PDN_CON0) & 0x0008) && /* Check PDN_CON0 WAVETABLE down */
((*PDN_CON1) & 0x0080) && /* Check PDN_CON1 LCD down */
(((*PDN_CON3) & 0x7F91) == 0x7F91)&& /* Check PDN_CON3 all down [GMC] (valid:0x7F91) */
*MCUCLK_CON == 0x0003 &&
#elif ( IS_CHIP_MT6217 )
(((*(volatile kal_uint32 *)0x80030000) & 0x00015555)==0) && /* Check DMA1~10, ignore DMA10~13 for 6217 */
(((*PDN_CON0) & 0x0038) == 0x0038) && /* Check PDN_CON0 RESIZER, JPEG, and WAVETABLE down */
((*PDN_CON1) & 0x0080) && /* Check PDN_CON1 LCD down */
*MCUCLK_CON == 0x0003 &&
#endif
dcm.dcmDisable == 0
)
{
#if ( (IS_CHIP_MT6228) || (IS_CHIP_MT6229)||(IS_CHIP_MT6235)||(IS_CHIP_MT6238))
/* Gate GMC DMA */
kal_uint32 tmp;
tmp = GateDG();
for (i = 0; i < 20; i++)
;
#endif
/*To access an address not in existance will ensure that EMI access is complete.*/
#if ( (IS_CHIP_MT6238) || (IS_CHIP_MT6235) )
j = *(volatile kal_uint16 *)0x28000000;
#else
j = *(volatile kal_uint16 *)0x24000000;
#endif
/*A26=1 means will not get data via data cache, it will access EMI directly.*/
dcm_state = 1; /* DCM @ 104/52->13/26Mhz */
/* Change WS and clock rate. */
/* mtk01940
======================================
Idle Dedi
MT6217 13MHz x
MT6229 26MHz 26MHz
MT6227 13MHZ 26MHz
MT6223 13MHz 13MHz
MT6225
MT6228
MT6229
MT6227D
======================================
*/
#if (IS_CHIP_MT6227 || IS_CHIP_MT6228)
#ifdef MT6227D
custom_DynamicClockSwitch( MCU_13MHZ );
#else
if(dcm.isIdleMode)
{
custom_DynamicClockSwitch( MCU_13MHZ );
}
else
{
custom_DynamicClockSwitch( MCU_26MHZ );
}
#endif
#elif (IS_CHIP_MT6229)
custom_DynamicClockSwitch( MCU_26MHZ );
#else
custom_DynamicClockSwitch( MCU_13MHZ );
#endif
/* mtk01940 */
dcm_state = 2; /* DCM @ 13/26MHz */
#if ((IS_CHIP_MT6228) || (IS_CHIP_MT6229)||(IS_CHIP_MT6235)||(IS_CHIP_MT6238))
/* Recover GMC DMA gating */
UngateDG(tmp);
#endif
/* check if IRQ is disabled for more than 60 qbits */
end = *((volatile kal_uint16 *)(TDMA_base + 0x00));
if (end >= start) {
duration = end - start;
} else {
tqwrap = *(volatile kal_uint16 *)(TDMA_base + 0x04);
duration = (tqwrap - start) + end;
}
if (duration > 60) {
EXT_ASSERT(0, duration, start, end);
}
*SLEEP_CON = 0x0003;
#if ( (IS_CHIP_MT6238) || (IS_CHIP_MT6235) )
cp15_enter_low_pwr_state();
#endif /* MT6238 */
}
else
{
*SLEEP_CON = 0x0001;
#if ( (IS_CHIP_MT6238) || (IS_CHIP_MT6235) )
cp15_enter_low_pwr_state();
#endif /* MT6238 */
}
RestoreIRQ(_savedMask);
#elif defined(MT6218B)
kal_uint32 _savedMask;
_savedMask = LockIRQ();
if ( (((*(volatile kal_uint16 *)0x80000300) & 0x0038)==0x0038) &&
((*(volatile kal_uint16 *)0x80000304) & 0x0080) )
{
/* Power down AHB only when WT & JPEG & Resizer & LCD is turned off. */
*SLEEP_CON = 0x0003;
}
else
{
*SLEEP_CON = 0x0001;
}
RestoreIRQ(_savedMask);
#else
/*To temporarily avoid the problem on AHB.*/
*SLEEP_CON = 0x0001;
#endif /* End #if defined(DCM_ENABLE)*/
#endif /* End #if defined(MTK_SLEEP_ENABLE) || defined(L1D_TEST) */
} /* Infinite loop */
}