/**
* Errata G-16094: QLM Gen2 Equalizer Default Setting Change.
* CN68XX pass 1.x and CN66XX pass 1.x QLM tweak. This function tweaks the
* JTAG setting for a QLMs to run better at 5 and 6.25Ghz.
*/
void __cvmx_qlm_speed_tweak(void)
{
cvmx_mio_qlmx_cfg_t qlm_cfg;
int num_qlms = cvmx_qlm_get_num();
int qlm;
/* Workaround for Errata (G-16467) */
if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2_X)) {
for (qlm = 0; qlm < num_qlms; qlm++) {
int ir50dac;
/* This workaround only applies to QLMs running at 6.25Ghz */
if (cvmx_qlm_get_gbaud_mhz(qlm) == 6250) {
#ifdef CVMX_QLM_DUMP_STATE
cvmx_dprintf("%s:%d: QLM%d: Applying workaround for Errata G-16467\n", __func__, __LINE__, qlm);
cvmx_qlm_display_registers(qlm);
cvmx_dprintf("\n");
#endif
cvmx_qlm_jtag_set(qlm, -1, "cfg_cdr_trunc", 0);
/* Hold the QLM in reset */
cvmx_qlm_jtag_set(qlm, -1, "cfg_rst_n_set", 0);
cvmx_qlm_jtag_set(qlm, -1, "cfg_rst_n_clr", 1);
/* Forcfe TX to be idle */
cvmx_qlm_jtag_set(qlm, -1, "cfg_tx_idle_clr", 0);
cvmx_qlm_jtag_set(qlm, -1, "cfg_tx_idle_set", 1);
if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2_0)) {
ir50dac = cvmx_qlm_jtag_get(qlm, 0, "ir50dac");
while (++ir50dac <= 31)
cvmx_qlm_jtag_set(qlm, -1, "ir50dac", ir50dac);
}
cvmx_qlm_jtag_set(qlm, -1, "div4_byp", 0);
cvmx_qlm_jtag_set(qlm, -1, "clkf_byp", 16);
cvmx_qlm_jtag_set(qlm, -1, "serdes_pll_byp", 1);
cvmx_qlm_jtag_set(qlm, -1, "spdsel_byp", 1);
#ifdef CVMX_QLM_DUMP_STATE
cvmx_dprintf("%s:%d: QLM%d: Done applying workaround for Errata G-16467\n", __func__, __LINE__, qlm);
cvmx_qlm_display_registers(qlm);
cvmx_dprintf("\n\n");
#endif
/* The QLM will be taken out of reset later when ILK/XAUI are initialized. */
}
}
#ifndef CVMX_BUILD_FOR_LINUX_HOST
/* These QLM tuning parameters are specific to EBB6800
eval boards using Cavium QLM cables. These should be
removed or tunned based on customer boards. */
if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBB6800) {
for (qlm = 0; qlm < num_qlms; qlm++) {
#ifdef CVMX_QLM_DUMP_STATE
cvmx_dprintf("Setting tunning parameters for QLM%d\n", qlm);
#endif
cvmx_qlm_jtag_set(qlm, -1, "biasdrv_hs_ls_byp", 12);
cvmx_qlm_jtag_set(qlm, -1, "biasdrv_hf_byp", 12);
cvmx_qlm_jtag_set(qlm, -1, "biasdrv_lf_ls_byp", 12);
cvmx_qlm_jtag_set(qlm, -1, "biasdrv_lf_byp", 12);
cvmx_qlm_jtag_set(qlm, -1, "tcoeff_hf_byp", 15);
cvmx_qlm_jtag_set(qlm, -1, "tcoeff_hf_ls_byp", 15);
cvmx_qlm_jtag_set(qlm, -1, "tcoeff_lf_ls_byp", 15);
cvmx_qlm_jtag_set(qlm, -1, "tcoeff_lf_byp", 15);
cvmx_qlm_jtag_set(qlm, -1, "rx_cap_gen2", 0);
cvmx_qlm_jtag_set(qlm, -1, "rx_eq_gen2", 11);
cvmx_qlm_jtag_set(qlm, -1, "serdes_tx_byp", 1);
}
}
else if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_NIC68_4) {
for (qlm = 0; qlm < num_qlms; qlm++) {
#ifdef CVMX_QLM_DUMP_STATE
cvmx_dprintf("Setting tunning parameters for QLM%d\n", qlm);
#endif
cvmx_qlm_jtag_set(qlm, -1, "biasdrv_hs_ls_byp", 30);
cvmx_qlm_jtag_set(qlm, -1, "biasdrv_hf_byp", 30);
cvmx_qlm_jtag_set(qlm, -1, "biasdrv_lf_ls_byp", 30);
cvmx_qlm_jtag_set(qlm, -1, "biasdrv_lf_byp", 30);
cvmx_qlm_jtag_set(qlm, -1, "tcoeff_hf_byp", 0);
cvmx_qlm_jtag_set(qlm, -1, "tcoeff_hf_ls_byp", 0);
cvmx_qlm_jtag_set(qlm, -1, "tcoeff_lf_ls_byp", 0);
cvmx_qlm_jtag_set(qlm, -1, "tcoeff_lf_byp", 0);
cvmx_qlm_jtag_set(qlm, -1, "rx_cap_gen2", 1);
cvmx_qlm_jtag_set(qlm, -1, "rx_eq_gen2", 8);
cvmx_qlm_jtag_set(qlm, -1, "serdes_tx_byp", 1);
}
}
#endif
}
/* G-16094 QLM Gen2 Equalizer Default Setting Change */
else if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1_X)
|| OCTEON_IS_MODEL(OCTEON_CN66XX_PASS1_X)) {
/* Loop through the QLMs */
for (qlm = 0; qlm < num_qlms; qlm++) {
/* Read the QLM speed */
qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(qlm));
/* If the QLM is at 6.25Ghz or 5Ghz then program JTAG */
if ((qlm_cfg.s.qlm_spd == 5) || (qlm_cfg.s.qlm_spd == 12) || (qlm_cfg.s.qlm_spd == 0) || (qlm_cfg.s.qlm_spd == 6) || (qlm_cfg.s.qlm_spd == 11)) {
cvmx_qlm_jtag_set(qlm, -1, "rx_cap_gen2", 0x1);
cvmx_qlm_jtag_set(qlm, -1, "rx_eq_gen2", 0x8);
}
}
}
}
/**
* @INTERNAL
* Return the link state of an IPD/PKO port as returned by ILK link status.
*
* @param ipd_port IPD/PKO port to query
*
* @return Link state
*/
cvmx_helper_link_info_t __cvmx_helper_ilk_link_get(int ipd_port)
{
cvmx_helper_link_info_t result;
int interface = cvmx_helper_get_interface_num(ipd_port);
int retry_count = 0;
cvmx_ilk_rxx_cfg1_t ilk_rxx_cfg1;
cvmx_ilk_rxx_int_t ilk_rxx_int;
int lanes = 0;
result.u64 = 0;
interface -= CVMX_ILK_GBL_BASE;
retry:
retry_count++;
if (retry_count > 10)
goto out;
ilk_rxx_cfg1.u64 = cvmx_read_csr (CVMX_ILK_RXX_CFG1(interface));
ilk_rxx_int.u64 = cvmx_read_csr (CVMX_ILK_RXX_INT(interface));
/* Clear all RX status bits */
if (ilk_rxx_int.u64)
cvmx_write_csr(CVMX_ILK_RXX_INT(interface), ilk_rxx_int.u64);
if (ilk_rxx_cfg1.s.rx_bdry_lock_ena == 0)
{
/* We need to start looking for work boundary lock */
ilk_rxx_cfg1.s.rx_bdry_lock_ena = cvmx_ilk_get_intf_ln_msk(interface);
ilk_rxx_cfg1.s.rx_align_ena = 0;
cvmx_write_csr(CVMX_ILK_RXX_CFG1(interface), ilk_rxx_cfg1.u64);
//cvmx_dprintf("ILK%d: Looking for word boundary lock\n", interface);
goto retry;
}
if (ilk_rxx_cfg1.s.rx_align_ena == 0)
{
if (ilk_rxx_int.s.word_sync_done)
{
ilk_rxx_cfg1.s.rx_align_ena = 1;
cvmx_write_csr(CVMX_ILK_RXX_CFG1(interface), ilk_rxx_cfg1.u64);
//printf("ILK%d: Looking for lane alignment\n", interface);
goto retry;
}
goto out;
}
if (ilk_rxx_int.s.lane_align_fail)
{
ilk_rxx_cfg1.s.rx_bdry_lock_ena = 0;
ilk_rxx_cfg1.s.rx_align_ena = 0;
cvmx_write_csr(CVMX_ILK_RXX_CFG1(interface), ilk_rxx_cfg1.u64);
cvmx_dprintf("ILK%d: Lane alignment failed\n", interface);
goto out;
}
if (ilk_rxx_int.s.lane_align_done)
{
//cvmx_dprintf("ILK%d: Lane alignment complete\n", interface);
}
lanes = cvmx_pop(ilk_rxx_cfg1.s.rx_bdry_lock_ena);
result.s.link_up = 1;
result.s.full_duplex = 1;
result.s.speed = cvmx_qlm_get_gbaud_mhz(1+interface) * 64 / 67;
result.s.speed *= lanes;
out:
/* If the link is down we will force disable the RX path. If it up, we'll
set it to match the TX state set by the if_enable call */
if (result.s.link_up)
{
cvmx_ilk_txx_cfg1_t ilk_txx_cfg1;
ilk_txx_cfg1.u64 = cvmx_read_csr(CVMX_ILK_TXX_CFG1(interface));
ilk_rxx_cfg1.s.pkt_ena = ilk_txx_cfg1.s.pkt_ena;
cvmx_write_csr(CVMX_ILK_RXX_CFG1(interface), ilk_rxx_cfg1.u64);
//cvmx_dprintf("ILK%d: link up, %d Mbps, Full duplex mode, %d lanes\n", interface, result.s.speed, lanes);
}
else
{
ilk_rxx_cfg1.s.pkt_ena = 0;
cvmx_write_csr(CVMX_ILK_RXX_CFG1(interface), ilk_rxx_cfg1.u64);
//cvmx_dprintf("ILK link down\n");
}
return result;
}
