static int pil_riva_reset(struct pil_desc *pil)
{
u32 reg, sel;
struct riva_data *drv = dev_get_drvdata(pil->dev);
void __iomem *base = drv->base;
unsigned long start_addr = drv->start_addr;
bool use_cxo = cxo_is_needed(drv);
reg = readl_relaxed(base + RIVA_PMU_A2XB_CFG);
reg |= RIVA_PMU_A2XB_CFG_EN;
writel_relaxed(reg, base + RIVA_PMU_A2XB_CFG);
reg = readl_relaxed(RIVA_PLL_MODE);
reg &= ~(PLL_MODE_BYPASSNL | PLL_MODE_OUTCTRL | PLL_MODE_RESET_N);
writel_relaxed(reg, RIVA_PLL_MODE);
if (use_cxo)
writel_relaxed(0x40000C00 | 50, RIVA_PLL_L_VAL);
else
writel_relaxed(0x40000C00 | 40, RIVA_PLL_L_VAL);
writel_relaxed(0, RIVA_PLL_M_VAL);
writel_relaxed(1, RIVA_PLL_N_VAL);
writel_relaxed(0x01495227, RIVA_PLL_CONFIG);
reg = readl_relaxed(RIVA_PLL_MODE);
reg &= ~(PLL_MODE_REF_XO_SEL);
reg |= use_cxo ? PLL_MODE_REF_XO_SEL_CXO : PLL_MODE_REF_XO_SEL_RF;
writel_relaxed(reg, RIVA_PLL_MODE);
reg |= PLL_MODE_BYPASSNL;
writel_relaxed(reg, RIVA_PLL_MODE);
mb();
usleep_range(10, 20);
reg |= PLL_MODE_RESET_N;
writel_relaxed(reg, RIVA_PLL_MODE);
reg |= PLL_MODE_OUTCTRL;
writel_relaxed(reg, RIVA_PLL_MODE);
mb();
usleep_range(50, 100);
sel = readl_relaxed(base + RIVA_PMU_ROOT_CLK_SEL);
reg = readl_relaxed(base + RIVA_PMU_CLK_ROOT3);
if (sel & RIVA_PMU_ROOT_CLK_SEL_3) {
reg &= ~(RIVA_PMU_CLK_ROOT3_SRC0_SEL |
RIVA_PMU_CLK_ROOT3_SRC0_DIV);
reg |= RIVA_PMU_CLK_ROOT3_SRC0_SEL_RIVA |
RIVA_PMU_CLK_ROOT3_SRC0_DIV_2;
} else {
reg &= ~(RIVA_PMU_CLK_ROOT3_SRC1_SEL |
RIVA_PMU_CLK_ROOT3_SRC1_DIV);
reg |= RIVA_PMU_CLK_ROOT3_SRC1_SEL_RIVA |
RIVA_PMU_CLK_ROOT3_SRC1_DIV_2;
}
writel_relaxed(reg, base + RIVA_PMU_CLK_ROOT3);
reg |= RIVA_PMU_CLK_ROOT3_ENA;
writel_relaxed(reg, base + RIVA_PMU_CLK_ROOT3);
reg = readl_relaxed(base + RIVA_PMU_ROOT_CLK_SEL);
reg ^= RIVA_PMU_ROOT_CLK_SEL_3;
writel_relaxed(reg, base + RIVA_PMU_ROOT_CLK_SEL);
reg = readl_relaxed(base + RIVA_PMU_CCPU_CTL);
reg |= RIVA_PMU_CCPU_CTL_HIGH_IVT | RIVA_PMU_CCPU_CTL_REMAP_EN;
writel_relaxed(reg, base + RIVA_PMU_CCPU_CTL);
writel_relaxed(start_addr >> 16, base + RIVA_PMU_CCPU_BOOT_REMAP_ADDR);
reg = readl_relaxed(base + RIVA_PMU_CFG);
reg &= ~(RIVA_PMU_CFG_WARM_BOOT);
writel_relaxed(reg, base + RIVA_PMU_CFG);
reg = readl_relaxed(base + RIVA_PMU_OVRD_VAL);
reg |= RIVA_PMU_OVRD_VAL_CCPU_CLK;
writel_relaxed(reg, base + RIVA_PMU_OVRD_VAL);
reg |= RIVA_PMU_OVRD_VAL_CCPU_RESET;
writel_relaxed(reg, base + RIVA_PMU_OVRD_VAL);
return 0;
}
static int pil_riva_reset(struct pil_desc *pil)
{
u32 reg, sel;
struct riva_data *drv = dev_get_drvdata(pil->dev);
void __iomem *base = drv->base;
phys_addr_t start_addr = pil_get_entry_addr(pil);
void __iomem *cbase = drv->cbase;
bool use_cxo = cxo_is_needed(drv);
/* Enable A2XB bridge */
reg = readl_relaxed(base + RIVA_PMU_A2XB_CFG);
reg |= RIVA_PMU_A2XB_CFG_EN;
writel_relaxed(reg, base + RIVA_PMU_A2XB_CFG);
/* Program PLL 13 to 960 MHz */
reg = readl_relaxed(cbase + RIVA_PLL_MODE);
reg &= ~(PLL_MODE_BYPASSNL | PLL_MODE_OUTCTRL | PLL_MODE_RESET_N);
writel_relaxed(reg, cbase + RIVA_PLL_MODE);
if (use_cxo)
writel_relaxed(0x40000C00 | 50, cbase + RIVA_PLL_L_VAL);
else
writel_relaxed(0x40000C00 | 40, cbase + RIVA_PLL_L_VAL);
writel_relaxed(0, cbase + RIVA_PLL_M_VAL);
writel_relaxed(1, cbase + RIVA_PLL_N_VAL);
writel_relaxed(0x01495227, cbase + RIVA_PLL_CONFIG);
reg = readl_relaxed(cbase + RIVA_PLL_MODE);
reg &= ~(PLL_MODE_REF_XO_SEL);
reg |= use_cxo ? PLL_MODE_REF_XO_SEL_CXO : PLL_MODE_REF_XO_SEL_RF;
writel_relaxed(reg, cbase + RIVA_PLL_MODE);
/* Enable PLL 13 */
reg |= PLL_MODE_BYPASSNL;
writel_relaxed(reg, cbase + RIVA_PLL_MODE);
/*
* H/W requires a 5us delay between disabling the bypass and
* de-asserting the reset. Delay 10us just to be safe.
*/
mb();
usleep_range(10, 20);
reg |= PLL_MODE_RESET_N;
writel_relaxed(reg, cbase + RIVA_PLL_MODE);
reg |= PLL_MODE_OUTCTRL;
writel_relaxed(reg, cbase + RIVA_PLL_MODE);
/* Wait for PLL to settle */
mb();
usleep_range(50, 100);
/* Configure cCPU for 240 MHz */
sel = readl_relaxed(base + RIVA_PMU_ROOT_CLK_SEL);
reg = readl_relaxed(base + RIVA_PMU_CLK_ROOT3);
if (sel & RIVA_PMU_ROOT_CLK_SEL_3) {
reg &= ~(RIVA_PMU_CLK_ROOT3_SRC0_SEL |
RIVA_PMU_CLK_ROOT3_SRC0_DIV);
reg |= RIVA_PMU_CLK_ROOT3_SRC0_SEL_RIVA |
RIVA_PMU_CLK_ROOT3_SRC0_DIV_2;
} else {
reg &= ~(RIVA_PMU_CLK_ROOT3_SRC1_SEL |
RIVA_PMU_CLK_ROOT3_SRC1_DIV);
reg |= RIVA_PMU_CLK_ROOT3_SRC1_SEL_RIVA |
RIVA_PMU_CLK_ROOT3_SRC1_DIV_2;
}
writel_relaxed(reg, base + RIVA_PMU_CLK_ROOT3);
reg |= RIVA_PMU_CLK_ROOT3_ENA;
writel_relaxed(reg, base + RIVA_PMU_CLK_ROOT3);
reg = readl_relaxed(base + RIVA_PMU_ROOT_CLK_SEL);
reg ^= RIVA_PMU_ROOT_CLK_SEL_3;
writel_relaxed(reg, base + RIVA_PMU_ROOT_CLK_SEL);
/* Use the high vector table */
reg = readl_relaxed(base + RIVA_PMU_CCPU_CTL);
reg |= RIVA_PMU_CCPU_CTL_HIGH_IVT | RIVA_PMU_CCPU_CTL_REMAP_EN;
writel_relaxed(reg, base + RIVA_PMU_CCPU_CTL);
/* Set base memory address */
writel_relaxed(start_addr >> 16, base + RIVA_PMU_CCPU_BOOT_REMAP_ADDR);
/* Clear warmboot bit indicating this is a cold boot */
reg = readl_relaxed(base + RIVA_PMU_CFG);
reg &= ~(RIVA_PMU_CFG_WARM_BOOT);
writel_relaxed(reg, base + RIVA_PMU_CFG);
/* Enable the cCPU clock */
reg = readl_relaxed(base + RIVA_PMU_OVRD_VAL);
reg |= RIVA_PMU_OVRD_VAL_CCPU_CLK;
writel_relaxed(reg, base + RIVA_PMU_OVRD_VAL);
/* Take cCPU out of reset */
reg |= RIVA_PMU_OVRD_VAL_CCPU_RESET;
writel_relaxed(reg, base + RIVA_PMU_OVRD_VAL);
return 0;
}
static int pil_riva_reset(struct pil_desc *pil)
{
u32 reg, sel;
struct riva_data *drv = dev_get_drvdata(pil->dev);
void __iomem *base = drv->base;
unsigned long start_addr = drv->start_addr;
bool use_cxo = cxo_is_needed(drv);
#ifdef CONFIG_QUALCOMM_WLAN_PXO
u32 nLoopCount = 5;
u32 hw_ver_id;
hw_ver_id = (readl(HW_VER_ID_VIRT)& 0xf0000000) >> 28;
printk("[WLAN][SSR] Get hw_ver_id = %#x\n", hw_ver_id);
#endif
reg = readl_relaxed(base + RIVA_PMU_A2XB_CFG);
reg |= RIVA_PMU_A2XB_CFG_EN;
writel_relaxed(reg, base + RIVA_PMU_A2XB_CFG);
reg = readl_relaxed(RIVA_PLL_MODE);
reg &= ~(PLL_MODE_BYPASSNL | PLL_MODE_OUTCTRL | PLL_MODE_RESET_N);
writel_relaxed(reg, RIVA_PLL_MODE);
if (use_cxo)
writel_relaxed(0x40000C00 | 50, RIVA_PLL_L_VAL);
else
writel_relaxed(0x40000C00 | 40, RIVA_PLL_L_VAL);
writel_relaxed(0, RIVA_PLL_M_VAL);
writel_relaxed(1, RIVA_PLL_N_VAL);
writel_relaxed(0x01495227, RIVA_PLL_CONFIG);
reg = readl_relaxed(RIVA_PLL_MODE);
reg &= ~(PLL_MODE_REF_XO_SEL);
reg |= use_cxo ? PLL_MODE_REF_XO_SEL_CXO : PLL_MODE_REF_XO_SEL_RF;
writel_relaxed(reg, RIVA_PLL_MODE);
reg |= PLL_MODE_BYPASSNL;
writel_relaxed(reg, RIVA_PLL_MODE);
mb();
usleep_range(10, 20);
reg |= PLL_MODE_RESET_N;
writel_relaxed(reg, RIVA_PLL_MODE);
reg |= PLL_MODE_OUTCTRL;
writel_relaxed(reg, RIVA_PLL_MODE);
mb();
usleep_range(50, 100);
#ifdef CONFIG_QUALCOMM_WLAN_PXO
if (hw_ver_id >= APQ8064_HW_VER_2_0) {
printk("[WLAN][SSR] Wait for PLL warm-up\n");
while(nLoopCount > 0)
{
udelay(CLOCK_PLL_WARMUP_TIME_US);
if(in_dword_masked(HWIO_PLL_LOCK_DET_STATUS_ADDR, 0xffffffff) & (1 << 13))
{break;}
nLoopCount--;
}
if(nLoopCount == 0)
{
printk("[WLAN][SSR] PLL lock detection failed!\n");
return -1;
}
printk("[WLAN][SSR] Check PLL lock detection passed\n");
HWIO_RIVA_PLL_MODE_OUTM(0x1, (u32)(1) << (0x0));
if (Clock_WaitForPLLActive(CLOCK_SOURCE_PLL13) == FALSE)
{return -1;}
printk("[WLAN][SSR] Wait for PLL Active ...OK!\n");
}
#endif
sel = readl_relaxed(base + RIVA_PMU_ROOT_CLK_SEL);
reg = readl_relaxed(base + RIVA_PMU_CLK_ROOT3);
if (sel & RIVA_PMU_ROOT_CLK_SEL_3) {
reg &= ~(RIVA_PMU_CLK_ROOT3_SRC0_SEL |
RIVA_PMU_CLK_ROOT3_SRC0_DIV);
reg |= RIVA_PMU_CLK_ROOT3_SRC0_SEL_RIVA |
RIVA_PMU_CLK_ROOT3_SRC0_DIV_2;
} else {
reg &= ~(RIVA_PMU_CLK_ROOT3_SRC1_SEL |
RIVA_PMU_CLK_ROOT3_SRC1_DIV);
reg |= RIVA_PMU_CLK_ROOT3_SRC1_SEL_RIVA |
RIVA_PMU_CLK_ROOT3_SRC1_DIV_2;
}
writel_relaxed(reg, base + RIVA_PMU_CLK_ROOT3);
reg |= RIVA_PMU_CLK_ROOT3_ENA;
writel_relaxed(reg, base + RIVA_PMU_CLK_ROOT3);
reg = readl_relaxed(base + RIVA_PMU_ROOT_CLK_SEL);
reg ^= RIVA_PMU_ROOT_CLK_SEL_3;
writel_relaxed(reg, base + RIVA_PMU_ROOT_CLK_SEL);
reg = readl_relaxed(base + RIVA_PMU_CCPU_CTL);
reg |= RIVA_PMU_CCPU_CTL_HIGH_IVT | RIVA_PMU_CCPU_CTL_REMAP_EN;
writel_relaxed(reg, base + RIVA_PMU_CCPU_CTL);
writel_relaxed(start_addr >> 16, base + RIVA_PMU_CCPU_BOOT_REMAP_ADDR);
reg = readl_relaxed(base + RIVA_PMU_CFG);
reg &= ~(RIVA_PMU_CFG_WARM_BOOT);
writel_relaxed(reg, base + RIVA_PMU_CFG);
reg = readl_relaxed(base + RIVA_PMU_OVRD_VAL);
reg |= RIVA_PMU_OVRD_VAL_CCPU_CLK;
writel_relaxed(reg, base + RIVA_PMU_OVRD_VAL);
#ifdef CONFIG_QUALCOMM_WLAN_PXO
if (hw_ver_id >= APQ8064_HW_VER_2_0) {
printk("[WLAN][SSR] Use PXO for RIVA\n");
HWIO_RIVA_RESET_OUTM((0x2),(u32)(1) << (0x1));
HWIO_RIVA_XO_SRC_CLK_CTL_OUTM((0x00000004), (u32)(1) << (0x2));
HWIO_RIVA_RESET_OUTM((0x2),(u32)(0) << (0x1));
}
#endif
reg |= RIVA_PMU_OVRD_VAL_CCPU_RESET;
writel_relaxed(reg, base + RIVA_PMU_OVRD_VAL);
return 0;
}