void i2cEnableInterrupt (BOOL bIsEnableINT)
{ UINT32 regdata;
//k09144-1 sysSetInterruptType(IRQ_FI2C, LOW_LEVEL_SENSITIVE); //k08184-1
#ifdef ECOS
if (bIsEnableINT) // enable I2C interrupt
{ cyg_interrupt_create(IRQ_FI2C, 1, 0, Int_Handler_FastI2C, NULL,
&int_handle_I2C, &int_holder_I2C);
cyg_interrupt_attach(int_handle_I2C);
cyg_interrupt_unmask(IRQ_FI2C);
}
else
{ cyg_interrupt_mask(IRQ_FI2C);
cyg_interrupt_detach(int_handle_I2C);
}
#else
sysInstallISR(IRQ_LEVEL_1, IRQ_FI2C, (PVOID)Int_Handler_FastI2C); //IRQ_FI2C=24
if (bIsEnableINT) sysEnableInterrupt(IRQ_FI2C); //k03224-1
else sysDisableInterrupt (IRQ_FI2C);
#endif
_i2c_bINT_EN=bIsEnableINT; //k07195-1
//enable sensor I2C engine's interrupt
if (bIsEnableINT)
{ regdata=inpw (REG_FastSerialBusCR)|0x02;
outpw (REG_FastSerialBusCR,regdata);
}
//To clear interrupt status
regdata=inpw (REG_FastSerialBusStatus)|0x03;
outpw (REG_FastSerialBusStatus,regdata);
/* enable I2C interrupt */
//k08204-1 sysEnableInterrupt(IRQ_FI2C); //k03224-1
}
void dev_at91sam9261_spi_dsr(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
{
kernel_sem_post(&spi_sem_tx_end);
//autorise à nouveau les IT
cyg_interrupt_unmask(vector);
}
//initialize data and enable IT
int dev_linux_eth_open(desc_t desc, int o_flag) {
cyg_vector_t eth_vector = CYGNUM_HAL_INT_ETH;
int rc;
//
if(o_flag & O_WRONLY) {
if(_linux_eth_desc_wr>=0)
return -1;
_linux_eth_desc_wr=desc;
}
if(o_flag & O_RDONLY) {
if(_linux_eth_desc_rd>=0)
return -1;
_linux_eth_desc_rd = desc;
_linux_eth_input_r = 0;
_linux_eth_input_w = 0;
}
//
if(_linux_eth_desc_wr>=0 && _linux_eth_desc_rd>=0) {
//open eth port in virtual cpu
eth_cmd.hdwr_id = ETH_0;
eth_cmd.cmd = OPS_OPEN;
//
//disable IT
//__clr_irq();
while(cyg_hal_sys_write(1, (void *)ð_cmd, sizeof(virtual_cmd_t)) != sizeof(virtual_cmd_t)) ;
while(cyg_hal_sys_read(0, (void *)ð_cmd, sizeof(virtual_cmd_t)) != sizeof(virtual_cmd_t)) ;
//enable IT
//__set_irq();
cyg_interrupt_unmask(eth_vector);
}
return 0;
}
/*-------------------------------------------
| Name:dev_linux_com0_load
| Description:
| Parameters:
| Return Type:
| Comments:
| See:
---------------------------------------------*/
int dev_linux_com0_load(void)
{
cyg_vector_t serial_vector = CYGNUM_HAL_INT_SERIAL;
cyg_priority_t serial_prior = CYGNUM_HAL_H_PRIOR;
if(_linux_uart_s0_loaded)
return 0; //yes
_linux_uart_s0_desc_rd = -1;
_linux_uart_s0_desc_wr = -1;
_xonoff_option = XONOFF_DSBL;
_rcv_xonoff_status = STATUS_IDLE;
_snd_xonoff_status = STATUS_IDLE;
//
cfmakeraw(&ttys_termios);
cfsetispeed (&ttys_termios,B9600);
cfsetospeed (&ttys_termios,B9600);
ttys_termios.c_iflag &= ~(IXOFF|IXON); //xon/xoff disable
//
ttys_termios.c_cc[VTIME]=0; // no timeout, blocking call
//inter_char_timer = 0;
_linux_uart_s0_loaded=1;
//Primitive de creation de l'IT
cyg_interrupt_create(serial_vector, serial_prior, 0,
&dev_linux_com0_isr, &dev_linux_com0_dsr,
&_linux_uart_s0_handle, &_linux_uart_s0_it);
//Liaison entre l'IT crée et le vecteur d'IT
cyg_interrupt_attach(_linux_uart_s0_handle);
cyg_interrupt_unmask(serial_vector);
return 0;
}
void vjpegInit(void)
{
#ifndef ECOS
tt_rmutex_init(&g_vpJPEG.mtLock);
tt_rmutex_init(&g_vpJPEG.mtLockEncoder);
tt_rmutex_init(&g_vpJPEG.mtLockDecoder);
tt_sem_init(&g_vpJPEG.semEncoder, 1);
tt_sem_init(&g_vpJPEG.semDecoder, 1);
tt_sem_down(&g_vpJPEG.semEncoder);
tt_sem_down(&g_vpJPEG.semDecoder);
#else
cyg_mutex_init(&g_vpJPEG.mtLock);
cyg_mutex_init(&g_vpJPEG.mtLockEncoder);
cyg_mutex_init(&g_vpJPEG.mtLockDecoder);
cyg_semaphore_init(&g_vpJPEG.semEncoder, 1);
cyg_semaphore_init(&g_vpJPEG.semDecoder, 1);
cyg_semaphore_wait(&g_vpJPEG.semEncoder);
cyg_semaphore_wait(&g_vpJPEG.semDecoder);
#endif
g_vpJPEG.nRefCount = 0;
g_vpJPEG.nRefCount_Encoder = 0;
g_vpJPEG.nRefCount_Decoder = 0;
g_vpJPEG.pJPEGEncodeBuffer = NULL;
listInit (&g_vpJPEG.listEncodedJPEG);
g_vpJPEG.nJPEGQua = 2;
g_vpJPEG.bOnTheFly = TRUE;
g_vpJPEG.nOnTheFlyCount = 0;
#ifndef ECOS
sysInstallISR(IRQ_LEVEL_1, IRQ_JPEG, (void*)jpegIntHandler);
#else
cyg_interrupt_disable();
cyg_interrupt_create(IRQ_JPEG, IRQ_LEVEL_1, NULL, &jpegIntHandler, &jpegIntHandler_DSR,
&(g_vpJPEG.cygIntrHandle), &(g_vpJPEG.cygIntrBuffer));
cyg_interrupt_attach(g_vpJPEG.cygIntrHandle);
cyg_interrupt_unmask(IRQ_JPEG);
cyg_interrupt_enable();
#endif
jpegSetIRQHandler(C_JPEG_CALLBACK_ENCODE_COMPLETE_INTERRUPT, vjpegEncoderCom_Callback);
jpegSetIRQHandler(C_JPEG_CALLBACK_DECODE_COMPLETE_INTERRUPT, vjpegDecoderCom_Callback);
jpegSetIRQHandler(C_JPEG_CALLBACK_DECODE_ERROR_INTERRUPT, vjpegDecoderErr_Callback);
if(g_vpJPEG.bOnTheFly == TRUE)
{
jpegSetIRQHandler(C_JPEG_CALLBACK_ENCODE_SWONTHEFLY_WAIT_INTERRUPT, vjpegOnTheFlyCom_Callback);
}
bJPEGInit = TRUE;
}
//DSR
void dev_linux_eth_dsr(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) {
if(rcv_flag) {
rcv_flag=0; //if(rcv_buf_input_no == rcv_buf_read_no) rcv_flag=0;
__fire_io_int(ofile_lst[_linux_eth_desc_rd].owner_pthread_ptr_read);
}
if(_linux_eth_desc_wr>=0 && _linux_eth_output_r==_linux_eth_output_w) {
_linux_eth_output_r = -1;
__fire_io_int(ofile_lst[_linux_eth_desc_wr].owner_pthread_ptr_write);
}
cyg_interrupt_unmask(vector);
}
void capIntHandlerDSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
{
UCHAR ucBuf;
if(CapIntHandlerTable[0]!=0)
{
UCHAR ucfr;
ucfr=(inpw(REG_CAPFuncEnable)&0x04) ? TRUE:FALSE;
CapIntHandlerTable[0](ucBuf,ucBuf,ucfr, FALSE);
}
cyg_interrupt_unmask(vector);
}
/*DSR*/
void dev_linux_com0_dsr(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
{
/*Autorise à nouveau les IT de ce type*/
if(rcv_flag) {
rcv_flag=0;
__fire_io_int(ofile_lst[_linux_uart_s0_desc_rd].owner_pthread_ptr_read);
}
if(_linux_uart_s0_desc_wr>=0 && _linux_uart_s0_output_r==_linux_uart_s0_output_w) {
__fire_io_int(ofile_lst[_linux_uart_s0_desc_wr].owner_pthread_ptr_write);
}
cyg_interrupt_unmask(vector);
}
// This DSR handles the board insertion
static void
cf_detect_dsr(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
{
unsigned long new_state = *SA11X0_GPIO_PIN_LEVEL;
struct cf_slot *slot = (struct cf_slot *)data;
if ((new_state & SA1110_GPIO_CF_DETECT) == SA1110_GPIO_CF_PRESENT) {
slot->state = CF_SLOT_STATE_Inserted;
} else {
slot->state = CF_SLOT_STATE_Removed; // Implies powered up, etc.
}
cyg_interrupt_acknowledge(SA1110_CF_DETECT);
cyg_interrupt_unmask(SA1110_CF_DETECT);
}
/*-------------------------------------------
| Name : dev_at91sam9260_uart1_dsr
| Description:
| Parameters : None
| Return Type: None
| Comments : -
| See : -
---------------------------------------------*/
void dev_at91sam9260_uart1_dsr(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
{
board_inf_uart_t * p_inf_uart = (board_inf_uart_t *)ofile_lst[desc_uart1].p;
if(p_inf_uart->rcv_flag) {
__fire_io_int(ofile_lst[p_inf_uart->desc_rd].owner_pthread_ptr_read);
p_inf_uart->rcv_flag = 0;
}
if ( (p_inf_uart->desc_wr >= 0) && (p_inf_uart->output_r == p_inf_uart->output_w) ) {
__fire_io_int(ofile_lst[p_inf_uart->desc_wr].owner_pthread_ptr_write);
}
//autorise � nouveau les IT
cyg_interrupt_unmask(vector);
}
/*-------------------------------------------
| Name:dev_at91sam9261_uart_dbg_open
| Description:
| Parameters:
| Return Type:
| Comments:
| See:
---------------------------------------------*/
int dev_at91sam9261_uart_dbg_open(desc_t desc, int o_flag)
{
#if defined(__KERNEL_UCORE_ECOS)
cyg_vector_t serial_vector = CYGNUM_HAL_INT_SERIAL;
cyg_priority_t serial_prior = CYGNUM_HAL_H_PRIOR;
#endif
int ret;
// Uart1 informations
ofile_lst[desc].p = (board_inf_uart_t *)p_board_inf_uart_dbg;
((board_inf_uart_t *)ofile_lst[desc].p)->base_adr = (AT91_REG *)AT91C_DBGU_CR; //0xFFFFF200
((board_inf_uart_t *)ofile_lst[desc].p)->periph_id = AT91C_ID_SYS; // system
((board_inf_uart_t *)ofile_lst[desc].p)->ind_pio_rxd = 9; // PA9/DRXD
((board_inf_uart_t *)ofile_lst[desc].p)->ind_pio_txd = 10; // PA10/DTXD
// Switch on descriptor type (R/W) and save it
if (o_flag & O_RDONLY)
{
((board_inf_uart_t *)ofile_lst[desc].p)->desc_r = desc;
}
if (o_flag & O_WRONLY)
{
((board_inf_uart_t *)ofile_lst[desc].p)->desc_w = desc;
}
// save
if(desc_uart_dbg<0)
desc_uart_dbg = desc;
// call uart common Api open
ret = dev_at91sam9261_uart_dbg_x_open(desc, o_flag);
#if defined(__KERNEL_UCORE_EMBOS) || defined(__KERNEL_UCORE_FREERTOS)
// Usart debug interrupt function initialization
g_p_fct_dbg_interrupt = dev_at91sam9261_uart_dbg_interrupt;
#elif defined(__KERNEL_UCORE_ECOS)
//Primitive de creation de l'IT au chargement du driver
cyg_interrupt_create(serial_vector, serial_prior, 0,
&dev_at91sam9261_uart_dbg_isr, &dev_at91sam9261_uart_dbg_dsr,
&_at91sam9261_uart_dbg_handle, &_at91sam9261_uart_dbg_it);
//Liaison entre l'IT crée et le vecteur d'IT
cyg_interrupt_attach(_at91sam9261_uart_dbg_handle);
cyg_interrupt_unmask(serial_vector);
#endif
return 0;
}
// Serial I/O - high level interrupt handler (DSR)
static void ra305x_timer0_dsr(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
{
cyg_uint32 iir;
iir = *((unsigned int*)0xB0000100);
if(iir & 0x1)
{
*((unsigned int*)0xB0000100) |= 0x1;
diag_printf("timer0 out\n");
}
cyg_interrupt_unmask(CYGNUM_HAL_INTERRUPT_TIMER0);
}
/*-------------------------------------------
| Name:dev_k60n512_uart_x_read
| Description:
| Parameters:
| Return Type:
| Comments:
| See:
---------------------------------------------*/
int dev_k60n512_uart_x_read(desc_t desc, char* buf,int size) {
board_kinetis_uart_info_t * p_uart_info = (board_kinetis_uart_info_t*)ofile_lst[desc].p;
int cb = 0;
int count = 0;
cb = (size>=UART_RX_BUFFER_SIZE) ? UART_RX_BUFFER_SIZE : size;
cyg_interrupt_mask((cyg_vector_t)p_uart_info->irq_no);
//
while(p_uart_info->input_r != p_uart_info->input_w && count < cb) {
buf[count++] = p_uart_info->input_buffer[p_uart_info->input_r];
p_uart_info->input_r = (p_uart_info->input_r+1) & (UART_RX_BUFFER_SIZE-1);
}
//
cyg_interrupt_unmask((cyg_vector_t)p_uart_info->irq_no);
return count;
}
void dev_at91sam9261_uart_dsr(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) {
board_inf_uart_t * p_inf_uart = (board_inf_uart_t *)data;
//
if(p_inf_uart->flag_i_int) {
__fire_io_int(ofile_lst[p_inf_uart->desc_rd].owner_pthread_ptr_read);
__unset_flag_fire_i_int(p_inf_uart->flag_i_int);
}
if (p_inf_uart->flag_o_int) {
__fire_io_int(ofile_lst[p_inf_uart->desc_wr].owner_pthread_ptr_write);
__unset_flag_fire_o_int(p_inf_uart->flag_o_int);
}
//autorise à nouveau les IT
cyg_interrupt_unmask(vector);
}
/*-------------------------------------------
| Name : dev_at91sam9260_uart_1_open
| Description: Opening uart device
| call by Open Posix interface
| Parameters : desc_t desc -> descriptor
|
| Return Type:
| Comments : -
| See : -
---------------------------------------------*/
int dev_at91sam9260_uart_1_open(desc_t desc, int o_flag)
{
cyg_vector_t serial_vector = CYGNUM_HAL_INTERRUPT_USART1;
cyg_priority_t serial_prior = 3;
int ret;
// Uart0 informations
ofile_lst[desc].p = (board_inf_uart_t *)p_board_inf_uart_1;
// Specific fields
((board_inf_uart_t *)ofile_lst[desc].p)->base_adr = (AT91_REG *)AT91C_BASE_US1;
((board_inf_uart_t *)ofile_lst[desc].p)->periph_id = AT91C_ID_US1;
((board_inf_uart_t *)ofile_lst[desc].p)->ind_pio_rxd = AT91C_PB7_RXD1;
((board_inf_uart_t *)ofile_lst[desc].p)->ind_pio_txd = AT91C_PB6_TXD1;
// Save o_flag
((board_inf_uart_t *)ofile_lst[desc].p)->o_flag |= o_flag;
// Switch on o_flag type and save it
if (o_flag & O_RDONLY) {
((board_inf_uart_t *)ofile_lst[desc].p)->desc_r = desc;
}
if (o_flag & O_WRONLY) {
((board_inf_uart_t *)ofile_lst[desc].p)->desc_w = desc;
}
// save descriptor
desc_uart1 = desc;
// call uart common Api open
ret = dev_at91sam9260_uart_x_open(desc, o_flag);
//Primitive de creation de l'IT au chargement du driver
cyg_interrupt_create(serial_vector, serial_prior, 0,
&dev_at91sam9260_uart1_isr, &dev_at91sam9260_uart1_dsr,
&_at91sam9260_uart_1_handle, &_at91sam9260_uart_1_it);
/*Configuration IT en edge-trigerred sur front montant*/
//Liaison entre l'IT cr�e et le vecteur d'IT
cyg_interrupt_attach(_at91sam9260_uart_1_handle);
cyg_interrupt_unmask(serial_vector);
return ret;
}
// Function to initialize the device. Called at bootstrap time.
static bool ra305x_wdt_init(void)
{
//#ifdef CYGDBG_IO_INIT
diag_printf("ra305x_wdttimer_init\n");
//#endif
cyg_interrupt_create(CYGNUM_HAL_INTERRUPT_WDTIMER,
0, // can change IRQ0 priority
NULL, // Data item passed to interrupt handler
ra305x_wdt_isr,
ra305x_wdt_dsr,
&rtmp_wdt_interrupt_handle,
&rtmp_wdt_interrupt);
cyg_interrupt_attach(rtmp_wdt_interrupt_handle);
cyg_interrupt_unmask(CYGNUM_HAL_INTERRUPT_WDTIMER);
return true;
}
void dev_at91sam9261_uart_dbg_dsr(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) {
board_inf_uart_t * p_inf_uart = (board_inf_uart_t *)ofile_lst[desc_uart_dbg].p;
//
if(rcv_flag) {
__fire_io_int(ofile_lst[p_inf_uart->desc_rd].owner_pthread_ptr_read);
rcv_flag = 0;
}
#if defined(USE_DMA_UART_SND)
if (p_inf_uart->desc_wr >= 0) {
__fire_io_int(ofile_lst[p_inf_uart->desc_wr].owner_pthread_ptr_write);
}
#else
if ( (p_inf_uart->desc_wr >= 0) && (p_inf_uart->output_r == p_inf_uart->output_w) ) {
__fire_io_int(ofile_lst[p_inf_uart->desc_wr].owner_pthread_ptr_write);
}
#endif
//autorise à nouveau les IT
cyg_interrupt_unmask(vector);
}
void capInit(BOOL bCapEngEnable, BOOL bCapIntEnable)
#endif
{
int j;
int i=sizeof(VCEInit)/sizeof(T_REG_INFO);
for (j=0; j<i ;j++)
outpw((CAP_BA+VCEInit[j].uAddr),VCEInit[j].uValue);
if(bCapEngEnable==TRUE)
{
outpw(REG_CAPEngine,inpw(REG_CAPEngine)|0x01);
}
else
{
outpw(REG_CAPEngine,inpw(REG_CAPEngine)&0xfffffffe);
}
if(bCapIntEnable==TRUE)
{
#ifdef ECOS
cyg_interrupt_disable();
cyg_interrupt_create(IRQ_VCE, 1, 0, capIntHandler, capIntHandlerDSR,
&(t_eCos->cap_int_handle), &(t_eCos->cap_int));
cyg_interrupt_attach(t_eCos->cap_int_handle);
cyg_interrupt_unmask(IRQ_VCE);
cyg_interrupt_enable();
#else
sysInstallISR(IRQ_LEVEL_1, IRQ_VCE, (PVOID)capIntHandler); //
sysEnableInterrupt(IRQ_VCE);
#endif
outpw(REG_CAPFuncEnable,inpw(REG_CAPFuncEnable)|0x2);
}
else
{
#ifdef ECOS
cyg_interrupt_mask(IRQ_VCE);
cyg_interrupt_detach(t_eCos->cap_int_handle);
cyg_interrupt_delete(t_eCos->cap_int_handle);
#else
sysDisableInterrupt(IRQ_VCE);
#endif
outpw(REG_CAPFuncEnable,inpw(REG_CAPFuncEnable)&0xfffffffd);
}
}
/*-------------------------------------------
| Name:dev_k60n512_uart_x_open
| Description:
| Parameters:
| Return Type:
| Comments:
| See:
---------------------------------------------*/
int dev_k60n512_uart_x_open(desc_t desc, int o_flag,
board_kinetis_uart_info_t * kinetis_uart_info) {
if(o_flag & O_RDONLY) {
if(kinetis_uart_info->desc_r<0) {
kinetis_uart_info->desc_r = desc;
}
else
return -1; //already open
}
if(o_flag & O_WRONLY) {
if(kinetis_uart_info->desc_w<0) {
kinetis_uart_info->desc_w = desc;
kinetis_uart_info->output_r = -1;
}
else
return -1; //already open
}
if(!ofile_lst[desc].p)
ofile_lst[desc].p=kinetis_uart_info;
//unmask IRQ
if(kinetis_uart_info->desc_r>=0 && kinetis_uart_info->desc_w>=0) {
cyg_interrupt_create((cyg_vector_t)kinetis_uart_info->irq_no,
kinetis_uart_info->irq_prio,
// Data item passed to interrupt handler
(cyg_addrword_t)kinetis_uart_info,
_kinetis_uart_x_isr,
_kinetis_uart_x_dsr,
&kinetis_uart_info->irq_handle,
&kinetis_uart_info->irq_it);
cyg_interrupt_attach(kinetis_uart_info->irq_handle);
cyg_interrupt_unmask((cyg_vector_t)kinetis_uart_info->irq_no);
HAL_WRITE_UINT8(kinetis_uart_info->uart_base + REG_UART_C2, UART_X_ALLOWED_IRQS);
}
return 0;
}
/*-------------------------------------------
| Name:_kinetis_uart_dsr
| Description:
| Parameters:
| Return Type:
| Comments:
| See:
---------------------------------------------*/
void _kinetis_uart_x_dsr(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) {
board_kinetis_uart_info_t * p_uart_info = (board_kinetis_uart_info_t*)data;
volatile unsigned char uart_sr;
//read status
HAL_READ_UINT8(p_uart_info->uart_base + REG_UART_S1, uart_sr);
//transmit
if(p_uart_info->xmit && (uart_sr & REG_UART_S1_TDRE)) {
if(p_uart_info->output_r != p_uart_info->output_w) {
//finish buffer
HAL_WRITE_UINT8(p_uart_info->uart_base + REG_UART_D,
p_uart_info->output_buffer[p_uart_info->output_r++]);
}
else {
//all data sent
volatile unsigned char uart_reg;
HAL_READ_UINT8(p_uart_info->uart_base + REG_UART_C2, uart_reg);
uart_reg &= ~REG_UART_C2_TIE;
HAL_WRITE_UINT8(p_uart_info->uart_base + REG_UART_C2, uart_reg);
p_uart_info->xmit=0;
__fire_io_int(ofile_lst[p_uart_info->desc_w].owner_pthread_ptr_write);
}
_kinetis_uart_stat.dsr_tx++;
}
//receive
else if(uart_sr & REG_UART_S1_RDRF) {
HAL_READ_UINT8(p_uart_info->uart_base + REG_UART_D,
p_uart_info->input_buffer[p_uart_info->input_w]);
p_uart_info->input_w = (p_uart_info->input_w+1) & (UART_RX_BUFFER_SIZE-1);
__fire_io_int(ofile_lst[p_uart_info->desc_r].owner_pthread_ptr_read);
}
cyg_interrupt_unmask(vector);
}
void cyg_user_start(void){
// Initialize framebuffer in graphic mode
ezs_fb_init();
// Initialize soundblaster
ezs_sb16_init(&sb16,
0x220 /* io address */,
5 /* interrupt */,
1 /* 8 bit DMA */,
5 /* 16 bit DMA */);
// Initialize HPET counter
ezs_counter_init();
// Initialize Tracer
int res = ezs_trace_init();
printf("init res: %d\r\n" , res);
// Create keyboard interrupt, attach to handler table and umask
cyg_interrupt_create(CYGNUM_HAL_INTERRUPT_KEYBOARD, 1, (cyg_addrword_t) &keyhandle, keyb_isr_handler, keyb_dsr_handler, &handle, &intr) ;
cyg_interrupt_attach(handle);
cyg_interrupt_unmask(CYGNUM_HAL_INTERRUPT_KEYBOARD);
// Create test thread
cyg_thread_create(17, &thread, 0, "Abtastung1", my_stack, STACKSIZE,
&threadhndl1, &threaddata);
// Create keyboard thread
cyg_thread_create(1, &keythread, 0, "Keyboard", keystack, STACKSIZE,
&keyhandle, &keydata);
// Create other threads
cyg_thread_create(1, abtastung1, 0, "thread_abtastung1", my_stack_abt1, STACKSIZE,
&(threadhndl_abt1), &(threaddata_abt1));
cyg_thread_create(5, abtastung2, 0, "thread_abtastung2", my_stack_abt2, STACKSIZE,
&(threadhndl_abt2), &(threaddata_abt2));
cyg_thread_create(10, analyse, 0, "thread_analyse", my_stack_anal, STACKSIZE,
&(threadhndl_anal), &(threaddata_anal));
cyg_thread_create(15, darstellung, 0, "thread_darstellung", my_stack_darst, STACKSIZE,
&(threadhndl_darst), &(threaddata_darst));
cyg_handle_t counter;
cyg_clock_to_counter(cyg_real_time_clock(), &counter);
/*
cyg_alarm_create(counter, alarm_handler, (cyg_addrword_t) &threadhndl1 , &alarmhnd1, &alarm1);
cyg_alarm_initialize(alarmhnd1, 0, 10);
cyg_alarm_enable(alarmhnd1);
*/
cyg_alarm_create(counter, alarm_handler, (cyg_addrword_t) &threadhndl_abt1 , &alarmhnd_abt1, &alarm_abt1);
cyg_alarm_initialize(alarmhnd_abt1, cyg_counter_current_value(counter) + 10, 10);
cyg_alarm_create(counter, alarm_handler, (cyg_addrword_t) &threadhndl_abt2 , &alarmhnd_abt2, &alarm_abt2);
cyg_alarm_initialize(alarmhnd_abt2, cyg_counter_current_value(counter) + 12, 20);
cyg_alarm_create(counter, alarm_handler, (cyg_addrword_t) &threadhndl_anal , &alarmhnd_anal, &alarm_anal);
cyg_alarm_initialize(alarmhnd_anal, cyg_counter_current_value(counter) + 14, 20);
cyg_alarm_create(counter, alarm_handler, (cyg_addrword_t) &threadhndl_darst , &alarmhnd_darst, &alarm_darst);
cyg_alarm_initialize(alarmhnd_darst, cyg_counter_current_value(counter) + 22, 100);
}
/*-------------------------------------------
| Name :dev_at91sam9261_spi_open
| Description:
| Parameters :
| Return Type:
| Comments :
| See :
---------------------------------------------*/
int dev_at91sam9261_spi_open(desc_t desc, int o_flag)
{
#ifdef USE_DMA_INTERUPT_TRANSMISSION
//variables pour la gestion de l'IT de fin d'emission
cyg_vector_t spi_vector = CYGNUM_HAL_INTERRUPT_SPI0;
cyg_priority_t spi_prior = CYGNUM_HAL_H_PRIOR;
#endif
//attributs de programmation du timer
rttmr_attr_t spi_timer_attr;
//creation du timer de timeout pour la fin d'attente d'emission
spi_timer_attr.tm_msec = TIMEOUT_SPI;
spi_timer_attr.func = (tmr_func_t)dev_at91sam9261_spi_timer_callback;
spi_timer_attr.data = 0;
rttmr_create(&dev_at91sam9261_spi_timer, &spi_timer_attr);
// Enable peripheral clock for selected SPI
*AT91C_PMC_PCER = 1 << AT91C_ID_SPI0;
// Enable peripheral clock for selected PIOA
*AT91C_PMC_PCER = 1 << AT91C_ID_PIOA; //GPIO clock enable
// Enable Write Enable and SD card presence
*AT91C_PIOA_PER = AT91C_PIO_PA4; // (1<<4); // Write Enable on PA04
*AT91C_PIOA_MDDR = AT91C_PIO_PA4; // (1<<4); // Write Enable/disable open drain
*AT91C_PIOA_PER = AT91C_PIO_PA5; // (1<<5); // SD Card presence on PB05
*AT91C_PIOA_MDDR = AT91C_PIO_PA5; // (1<<5); // SD Card disable open drain
*AT91C_PIOA_ODR = AT91C_PIO_PA4; // (1<<4); // Input only
*AT91C_PIOA_ODR = AT91C_PIO_PA5; // (1<<5); // Input only
// Enable Chip Select line /GPIO on NPCS0 PA03
*AT91C_PIOA_PER = AT91C_PIO_PA3; // (1<<3); // Write Enable on PA111
*AT91C_PIOA_MDDR = AT91C_PIO_PA3; // (1<<3); // Write Enable disable open drain
*AT91C_PIOA_OER = AT91C_PIO_PA3; //(1<<3); // Enable Output on the I/O line
*AT91C_PIOA_OWER = AT91C_PIO_PA3; //(1<<3); // Port A all ODSR enabled
*AT91C_PIOA_SODR = AT91C_PIO_PA3; //(1<<3); //=1 => set CS
// Setup PIO pins for SPI interface
// Disable PIO control of PA11/NPCS0, PA12/MISO, PA13/MOSI, PA14/SPCK
*AT91C_PIOA_PDR = ( AT91C_PIO_PA0 | // (1<<0)
AT91C_PIO_PA1 | // (1<<1)
AT91C_PIO_PA2); // (1<<2)
// Enable I/O peripheral mode A
*AT91C_PIOA_ASR = ( AT91C_PIO_PA0 | // (1<<0)
AT91C_PIO_PA1 | // (1<<1)
AT91C_PIO_PA2); // (1<<2)
*AT91C_SPI0_PTCR = AT91C_PDC_RXTDIS|AT91C_PDC_TXTDIS; // disable DMA transfer TX
*AT91C_SPI0_CR = AT91C_SPI_SWRST; // Software reset
*AT91C_SPI0_CR = AT91C_SPI_SPIEN; // enable the SPI to transfer and receive data
*AT91C_SPI0_IDR = 0xffffffff; // Disable all SPI interrupts.
// Set master mode with:
*AT91C_SPI0_MR = AT91C_SPI_MSTR | // SPI MASTER
AT91C_SPI_PS_FIXED | // Fixed peripheral Select
AT91C_SPI_MODFDIS; // No mode fault
// Setup data transfer format and rate for device 0 => 8 bits, CPOL=0, NCPHA=1
*AT91C_SPI0_CSR = AT91C_SPI_NCPHA |
AT91C_SPI_BITS_8 |
(DLYBCT_SPI_CSR0 << 24) | // Delay between 2 charact
(SPI_SCKDIV_ARM9 << 8); // SCBR
*AT91C_AIC_ICCR = (1 << AT91C_ID_SPI0); // Clears spi interrupt.
#ifdef USE_DMA_INTERUPT_TRANSMISSION
//initialisation du semaphore d'attente
kernel_sem_init(&spi_sem_tx_end, 0, 0);
//Primitive de creation de l'IT au chargement du driver
cyg_interrupt_create(spi_vector,
spi_prior,
0,
&dev_at91sam9261_isr,
&dev_at91sam9261_spi_dsr,
&_at91sam9261_spi_handle,
&_at91sam9261_spi_it);
//Liaison entre l'IT crée et le vecteur d'IT
cyg_interrupt_attach(_at91sam9261_spi_handle);
//connecter l'it
cyg_interrupt_unmask(spi_vector);
#endif
return 0;
}
INT w5691StartPlay(AU_CB_FUNC_T *fnCallBack, INT nSamplingRate,
INT nChannels, INT pcm_format)
{
UINT16 wTMV;
UINT8 byTMB = 0;
UINT8 byClockBase = 1;
UINT8 eFormat = eSPEECH_FORMAT_SIGN_16BIT_PCM;
INT nStatus;
UINT8 byStartSpchCmd[8] = { 0x03, 0x03, 0x00, 0x00, 0x00, 0x00 , 0x7f, 0x40 };//GFIFO start play command
if (_W5691_Playing)
return ERR_W5691_PLAY_ACTIVE;
if (_W5691_Playing == 0)
{
memset((CHAR *)&_tW5691, 0, sizeof(_tW5691));
nStatus = w5691_init();
if (nStatus < 0)
return nStatus;
}
#ifdef ECOS
cyg_interrupt_disable();
sysSetInterruptType(GPIO_INT_NUM, LOW_LEVEL_SENSITIVE);
cyg_interrupt_create(GPIO_INT_NUM, 1, 0, w5691_dma_isr, NULL,
&_tW5691.int_handle_play, &_tW5691.int_holder_play);
cyg_interrupt_attach(_tW5691.int_handle_play);
cyg_interrupt_unmask(AU_PLAY_INT_NUM);
cyg_interrupt_enable();
#else
sysSetInterruptType(GPIO_INT_NUM, LOW_LEVEL_SENSITIVE);
/* Install ISR */
sysInstallISR(IRQ_LEVEL_1, GPIO_INT_NUM, (PVOID)w5691_dma_isr);
/* enable CPSR I bit */
sysSetLocalInterrupt(ENABLE_IRQ);
/* Set AIC into SW mode */
// sysSetAIC2SWMode();
sysEnableInterrupt(GPIO_INT_NUM);
#endif
outpw(REG_GPIO_OE, inpw(REG_GPIO_OE) | (1<<USED_GPIO_NUM));
_tW5691.nPlaySamplingRate = nSamplingRate;
_tW5691.fnPlayCallBack = fnCallBack;
wTMV = (UINT16)(W5691_SYSTEM_CLOCK / _tW5691.nPlaySamplingRate) / byClockBase;
while(wTMV > 511)
{
byClockBase <<= 1;
wTMV >>= 1;
byTMB++;
}
byStartSpchCmd[2] = (UINT8)eFormat | eSPEECH_FCH_PFIFO ;
byStartSpchCmd[3] = (UINT8)(wTMV & 0xFF);
byStartSpchCmd[4] = (UINT8)(wTMV >> 8);
byStartSpchCmd[5] = byTMB;
/* call back to fill DMA buffer*/
_tW5691.bPlayLastBlock = _tW5691.fnPlayCallBack((UINT8 *)_uAuPlayBuffAddr,
Play_FIFO_Trigger_Length*2);
/* send PCM data to w5691*/
ComDrv_SendCommandWithData(eCOMMAND_SEND_SPEECH_DATA,
(UINT8 *)_uAuPlayBuffAddr, Play_FIFO_Trigger_Length*2);
ComDrv_SendCommand(eCOMMAND_ENABLE_SPEECH_INTERRUPT);
#ifdef SOFT_MODE
ComDrv_SendFIFOData(CMD_COM_ID_GEN_FIFO,byStartSpchCmd,6);
#else
outpw(REG_ACTL_M80SIZE, 6+1);
outpw(REG_ACTL_M80DATA0, 0x55 | byStartSpchCmd[0]<<8 | (byStartSpchCmd[1]<<16) | (byStartSpchCmd[2]<<24) );
outpw(REG_ACTL_M80DATA1, byStartSpchCmd[3] | (byStartSpchCmd[4]<<8) | (byStartSpchCmd[5]<<16));
outpw(REG_ACTL_M80ADDR, CMD_COM_ID_GEN_FIFO);
outpw(REG_ACTL_M80CON, inpw(REG_ACTL_M80CON) | W_GFIFO | W_IF12_ACT);
while((inpw(REG_ACTL_M80CON)&W_IF12_ACT) != 0);
outpw(REG_ACTL_M80CON, inpw(REG_ACTL_M80CON) & ~W_GFIFO );
ComDrv_SendSimpleCommand(CMD_COM_ID_WAKE_UP,WAKE_UP_REG_INT);
#endif
Delay(0x5000);
ComDrv_SetInterruptMask(1);
#ifdef SOFT_MODE
soft_read_status_flag_reg();
#else
ComDrv_DisableInterrupt();
#endif
ComDrv_EnableInterrupt();
_W5691_Playing=1;
return 0;
}
void kintr0_main( void )
{
cyg_vector_t v = (CYGNUM_HAL_VSR_MIN + 11) % CYGNUM_HAL_VSR_COUNT;
cyg_vector_t v1;
cyg_vector_t lvl1 = CYGNUM_HAL_ISR_MIN + (1 % CYGNUM_HAL_ISR_COUNT);
cyg_vector_t lvl2 = CYGNUM_HAL_ISR_MIN + (15 % CYGNUM_HAL_ISR_COUNT);
int in_use;
cyg_VSR_t *old_vsr, *new_vsr;
CYG_TEST_INIT();
#ifdef CYGPKG_HAL_MIPS_TX39
// This can be removed when PR 17831 is fixed
if ( cyg_test_is_simulator )
v1 = 12 % CYGNUM_HAL_ISR_COUNT;
else /* NOTE TRAILING ELSE... */
#endif
v1 = CYGNUM_HAL_ISR_MIN + ( 6 % CYGNUM_HAL_ISR_COUNT);
CHECK(flash());
CHECK(flash());
// Make sure the chosen levels are not already in use.
HAL_INTERRUPT_IN_USE( lvl1, in_use );
intr0 = 0;
if (!in_use)
cyg_interrupt_create(lvl1, PRIO_B, (cyg_addrword_t)777,
isr0, dsr0, &intr0, &intr_obj[0]);
HAL_INTERRUPT_IN_USE( lvl2, in_use );
intr1 = 0;
if (!in_use && lvl1 != lvl2)
cyg_interrupt_create(lvl2, PRIO_C, 888,
isr1, dsr1, &intr1, &intr_obj[1]);
// Check these functions at least exist
cyg_interrupt_disable();
cyg_interrupt_enable();
if (intr0)
cyg_interrupt_attach(intr0);
if (intr1)
cyg_interrupt_attach(intr1);
if (intr0)
cyg_interrupt_detach(intr0);
if (intr1)
cyg_interrupt_detach(intr1);
// If this attaching interrupt replaces the previous interrupt
// instead of adding to it we could be in a big mess if the
// vector is being used by something important.
cyg_interrupt_get_vsr( v, &old_vsr );
cyg_interrupt_set_vsr( v, vsr0 );
cyg_interrupt_get_vsr( v, &new_vsr );
CHECK( vsr0 == new_vsr );
new_vsr = NULL;
cyg_interrupt_get_vsr( v, &new_vsr );
cyg_interrupt_set_vsr( v, old_vsr );
CHECK( new_vsr == vsr0 );
cyg_interrupt_set_vsr( v, new_vsr );
new_vsr = NULL;
cyg_interrupt_get_vsr( v, &new_vsr );
CHECK( vsr0 == new_vsr );
cyg_interrupt_set_vsr( v, old_vsr );
CHECK( vsr0 == new_vsr );
new_vsr = NULL;
cyg_interrupt_get_vsr( v, &new_vsr );
CHECK( old_vsr == new_vsr );
CHECK( NULL != vsr0 );
cyg_interrupt_mask(v1);
cyg_interrupt_unmask(v1);
cyg_interrupt_configure(v1, true, true);
CYG_TEST_PASS_FINISH("Kernel C API Intr 0 OK");
}
void
timers_test(cyg_addrword_t data)
{
int loops = LOOPS;
int i;
CYG_INTERRUPT_STATE istate;
CYG_TEST_INIT();
CYG_TEST_INFO("Start Timers test");
for( i = 0; timers[i].timer != 0; i++ )
{
struct timer *t = &timers[i];
init_timer( t->base, t->interval );
cyg_interrupt_create( t->vector,
t->priority,
(cyg_addrword_t)t,
timer_isr,
timer_dsr,
&t->interrupt_handle,
&t->interrupt_object
);
cyg_interrupt_attach( t->interrupt_handle );
cyg_interrupt_unmask( t->vector );
}
while( loops-- )
{
int j;
// 5 second delay
cyg_thread_delay( 5*100 );
// Disable interrupts while we print details, otherwise it
// comes out very slowly.
HAL_DISABLE_INTERRUPTS( istate );
if( max_nesting > max_nesting_seen )
max_nesting_seen = max_nesting;
diag_printf("\nISRs max_nesting %d max_nesting_seen %d\n", max_nesting, max_nesting_seen );
max_nesting = 0;
diag_printf(" T Ticks ");
for( j = 0; j < 9; j++ )
diag_printf("%9d ", j );
diag_printf("\n");
for( i = 0; timers[i].timer != 0; i++ )
{
struct timer *t = &timers[i];
diag_printf("%2d: %9d ", t->timer, t->ticks );
for( j = 0; j < 9; j++ )
diag_printf("%9d ", t->preempt[j] );
diag_printf("\n");
}
diag_printf("DSRs\n");
diag_printf(" T: ");
for( j = 0; j < 9; j++ )
diag_printf("%9d ", j );
diag_printf("\n");
for( i = 0; timers[i].timer != 0; i++ )
{
struct timer *t = &timers[i];
diag_printf("%2d: preempt: ", t->timer);
for( j = 0; j < 9; j++ )
diag_printf("%9d ", t->preempt_dsr[j] );
diag_printf("\n");
diag_printf(" count: ");
for( j = 0; j < 9; j++ )
diag_printf("%9d ", t->dsr_count[j] );
diag_printf("\n");
}
HAL_RESTORE_INTERRUPTS( istate );
}
CYG_TEST_PASS_FINISH("Timers test");
}
