static int fimc_is_resourcemgr_initmem(struct fimc_is_resourcemgr *resourcemgr) { int ret = 0; u32 offset; dbg_core("fimc_is_init_mem - ION\n"); ret = fimc_is_resourcemgr_allocmem(resourcemgr); if (ret) { err("Couldn't alloc for FIMC-IS firmware\n"); ret = -ENOMEM; goto p_err; } offset = FW_SHARED_OFFSET; resourcemgr->minfo.dvaddr_fshared = resourcemgr->minfo.dvaddr + offset; resourcemgr->minfo.kvaddr_fshared = resourcemgr->minfo.kvaddr + offset; offset = FIMC_IS_A5_MEM_SIZE - FIMC_IS_REGION_SIZE; resourcemgr->minfo.dvaddr_region = resourcemgr->minfo.dvaddr + offset; resourcemgr->minfo.kvaddr_region = resourcemgr->minfo.kvaddr + offset; offset = FIMC_IS_A5_MEM_SIZE; #ifdef ENABLE_ODC resourcemgr->minfo.dvaddr_odc = resourcemgr->minfo.dvaddr + offset; resourcemgr->minfo.kvaddr_odc = resourcemgr->minfo.kvaddr + offset; offset += (SIZE_ODC_INTERNAL_BUF * NUM_ODC_INTERNAL_BUF); #else resourcemgr->minfo.dvaddr_odc = 0; resourcemgr->minfo.kvaddr_odc = 0; #endif #ifdef ENABLE_VDIS resourcemgr->minfo.dvaddr_dis = resourcemgr->minfo.dvaddr + offset; resourcemgr->minfo.kvaddr_dis = resourcemgr->minfo.kvaddr + offset; offset += (SIZE_DIS_INTERNAL_BUF * NUM_DIS_INTERNAL_BUF); #else resourcemgr->minfo.dvaddr_dis = 0; resourcemgr->minfo.kvaddr_dis = 0; #endif #ifdef ENABLE_DNR resourcemgr->minfo.dvaddr_3dnr = resourcemgr->minfo.dvaddr + offset; resourcemgr->minfo.kvaddr_3dnr = resourcemgr->minfo.kvaddr + offset; offset += (SIZE_DNR_INTERNAL_BUF * NUM_DNR_INTERNAL_BUF); #else resourcemgr->minfo.dvaddr_3dnr = 0; resourcemgr->minfo.kvaddr_3dnr = 0; #endif dbg_core("fimc_is_init_mem done\n"); p_err: return ret; }
int fimc_is_dvfs_init(struct fimc_is_resourcemgr *resourcemgr) { int i; dbg_core("%s\n", __func__); BUG_ON(!resourcemgr); resourcemgr->dvfs_ctrl.cur_cpu_min_qos = 0; resourcemgr->dvfs_ctrl.cur_cpu_max_qos = 0; resourcemgr->dvfs_ctrl.cur_int_qos = 0; resourcemgr->dvfs_ctrl.cur_mif_qos = 0; resourcemgr->dvfs_ctrl.cur_cam_qos = 0; resourcemgr->dvfs_ctrl.cur_i2c_qos = 0; resourcemgr->dvfs_ctrl.cur_disp_qos = 0; /* init spin_lock for clock gating */ mutex_init(&resourcemgr->dvfs_ctrl.lock); if (!(resourcemgr->dvfs_ctrl.static_ctrl)) resourcemgr->dvfs_ctrl.static_ctrl = kzalloc(sizeof(struct fimc_is_dvfs_scenario_ctrl), GFP_KERNEL); if (!(resourcemgr->dvfs_ctrl.dynamic_ctrl)) resourcemgr->dvfs_ctrl.dynamic_ctrl = kzalloc(sizeof(struct fimc_is_dvfs_scenario_ctrl), GFP_KERNEL); if (!resourcemgr->dvfs_ctrl.static_ctrl || !resourcemgr->dvfs_ctrl.dynamic_ctrl) { err("dvfs_ctrl alloc is failed!!\n"); return -ENOMEM; } /* set priority by order */ for (i = 0; i < ARRAY_SIZE(static_scenarios); i++) static_scenarios[i].priority = i; for (i = 0; i < ARRAY_SIZE(dynamic_scenarios); i++) dynamic_scenarios[i].priority = i; resourcemgr->dvfs_ctrl.static_ctrl->cur_scenario_id = -1; resourcemgr->dvfs_ctrl.static_ctrl->cur_scenario_idx = -1; resourcemgr->dvfs_ctrl.static_ctrl->scenarios = static_scenarios; if (static_scenarios[0].scenario_id == FIMC_IS_SN_DEFAULT) resourcemgr->dvfs_ctrl.static_ctrl->scenario_cnt = 0; else resourcemgr->dvfs_ctrl.static_ctrl->scenario_cnt = ARRAY_SIZE(static_scenarios); resourcemgr->dvfs_ctrl.dynamic_ctrl->cur_scenario_id = -1; resourcemgr->dvfs_ctrl.dynamic_ctrl->cur_scenario_idx = -1; resourcemgr->dvfs_ctrl.dynamic_ctrl->cur_frame_tick = -1; resourcemgr->dvfs_ctrl.dynamic_ctrl->scenarios = dynamic_scenarios; if (static_scenarios[0].scenario_id == FIMC_IS_SN_DEFAULT) resourcemgr->dvfs_ctrl.dynamic_ctrl->scenario_cnt = 0; else resourcemgr->dvfs_ctrl.dynamic_ctrl->scenario_cnt = ARRAY_SIZE(dynamic_scenarios); return 0; }
static int __devinit fimc_is_spi_probe(struct spi_device *spi) { int ret = 0; dbg_core("%s\n", __func__); /* spi->bits_per_word = 16; */ if (spi_setup(spi)) { pr_err("failed to setup spi for fimc_is_spi\n"); ret = -EINVAL; goto exit; } g_spi = spi; exit: return ret; }
static int fimc_is_resourcemgr_allocmem(struct fimc_is_resourcemgr *resourcemgr) { int ret = 0; void *fw_cookie; size_t fw_size = FIMC_IS_A5_MEM_SIZE; #ifdef FW_SUSPEND_RESUME fw_size += FIMC_IS_BACKUP_SIZE; #endif #ifdef ENABLE_ODC fw_size += SIZE_ODC_INTERNAL_BUF * NUM_ODC_INTERNAL_BUF; #endif #ifdef ENABLE_VDIS fw_size += SIZE_DIS_INTERNAL_BUF * NUM_DIS_INTERNAL_BUF; #endif #ifdef ENABLE_DNR fw_size += SIZE_DNR_INTERNAL_BUF * NUM_DNR_INTERNAL_BUF; #endif fw_size = PAGE_ALIGN(fw_size); dbg_core("Allocating memory for FIMC-IS firmware.\n"); fw_cookie = vb2_ion_private_alloc(resourcemgr->mem.alloc_ctx, fw_size, 1, 0); if (IS_ERR(fw_cookie)) { err("Allocating bitprocessor buffer failed"); fw_cookie = NULL; ret = -ENOMEM; goto p_err; } ret = vb2_ion_dma_address(fw_cookie, &resourcemgr->minfo.dvaddr); if ((ret < 0) || (resourcemgr->minfo.dvaddr & FIMC_IS_FW_BASE_MASK)) { err("The base memory is not aligned to 64MB."); vb2_ion_private_free(fw_cookie); resourcemgr->minfo.dvaddr = 0; fw_cookie = NULL; ret = -EIO; goto p_err; } #ifdef PRINT_BUFADDR info("[RSC] daddr = %pa, size = %08X\n", &resourcemgr->minfo.dvaddr, FIMC_IS_A5_MEM_SIZE); #endif resourcemgr->minfo.kvaddr = (ulong)vb2_ion_private_vaddr(fw_cookie); if (IS_ERR((void *)resourcemgr->minfo.kvaddr)) { err("Bitprocessor memory remap failed"); vb2_ion_private_free(fw_cookie); resourcemgr->minfo.kvaddr = 0; fw_cookie = NULL; ret = -EIO; goto p_err; } vb2_ion_sync_for_device(fw_cookie, 0, fw_size, DMA_BIDIRECTIONAL); p_err: info("[RSC] Device virtual for internal: %08lx\n", resourcemgr->minfo.kvaddr); resourcemgr->minfo.fw_cookie = fw_cookie; return ret; }
static int __devinit fimc_is_spi_probe(struct spi_device *spi) { int ret = 0; int gpio; dbg_core("%s\n", __func__); /* spi->bits_per_word = 16; */ if (spi_setup(spi)) { pr_err("failed to setup spi for fimc_is_spi\n"); ret = -EINVAL; goto exit; } g_spi = spi; gpio = EXYNOS5410_GPF1(0); if (gpio_request(gpio, "dout_spi3")) { err("gpio_request(dout_spi3) is fail1"); } else { s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); gpio_free(gpio); } gpio = EXYNOS5410_GPF1(1); if (gpio_request(gpio, "dout_spi3")) { err("gpio_request(dout_spi3) is fail2"); } else { s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(1)); s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); gpio_free(gpio); } for (gpio = EXYNOS5410_GPF1(0); gpio < EXYNOS5410_GPF1(4); gpio++) s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV3); exit: /* 1. disable A5 */ writel(0x00000, PMUREG_ISP_ARM_OPTION); writel(0x0, PMUREG_CMU_RESET_ISP_SYS_PWR_REG); writel(0x0, PMUREG_CMU_SYSCLK_ISP_SYS_PWR_REG); writel(0x0, PMUREG_ISP_ARM_SYS_PWR_REG); #if defined(CONFIG_PM_RUNTIME) pm_runtime_put_sync(get_is_dev()); #endif /* * spi ch3 is isp spi0, this gpio function should be changed for * flash control after usage(only smdk board) */ gpio = EXYNOS5410_GPF1(0); if (gpio_request(gpio, "dout_spi3")) { err("gpio_request(dout_spi3) is fail3"); } else { s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); gpio_free(gpio); } gpio = EXYNOS5410_GPF1(1); if (gpio_request(gpio, "dout_spi3")) { err("gpio_request(dout_spi3) is fail4"); } else { s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); gpio_free(gpio); } return ret; }
static int fimc_is_resourcemgr_initmem(struct fimc_is_resourcemgr *resourcemgr) { int ret = 0; #ifdef ENABLE_FD_SW int num_buf = 0; #endif #ifdef ENABLE_FD_DMA_INPUT int fd_buf = 0; #endif u32 offset; dbg_core("fimc_is_init_mem - ION\n"); ret = fimc_is_resourcemgr_allocmem(resourcemgr); if (ret) { err("Couldn't alloc for FIMC-IS firmware\n"); ret = -ENOMEM; goto p_err; } offset = FW_SHARED_OFFSET; resourcemgr->minfo.dvaddr_fshared = resourcemgr->minfo.dvaddr + offset; resourcemgr->minfo.kvaddr_fshared = resourcemgr->minfo.kvaddr + offset; offset = FIMC_IS_A5_MEM_SIZE - FIMC_IS_REGION_SIZE; resourcemgr->minfo.dvaddr_region = resourcemgr->minfo.dvaddr + offset; resourcemgr->minfo.kvaddr_region = resourcemgr->minfo.kvaddr + offset; offset = FIMC_IS_A5_MEM_SIZE; #ifdef ENABLE_ODC resourcemgr->minfo.dvaddr_odc = resourcemgr->minfo.dvaddr + offset; resourcemgr->minfo.kvaddr_odc = resourcemgr->minfo.kvaddr + offset; offset += (SIZE_ODC_INTERNAL_BUF * NUM_ODC_INTERNAL_BUF); #else resourcemgr->minfo.dvaddr_odc = 0; resourcemgr->minfo.kvaddr_odc = 0; #endif #ifdef ENABLE_VDIS resourcemgr->minfo.dvaddr_dis = resourcemgr->minfo.dvaddr + offset; resourcemgr->minfo.kvaddr_dis = resourcemgr->minfo.kvaddr + offset; offset += (SIZE_DIS_INTERNAL_BUF * NUM_DIS_INTERNAL_BUF); #else resourcemgr->minfo.dvaddr_dis = 0; resourcemgr->minfo.kvaddr_dis = 0; #endif #ifdef ENABLE_DNR resourcemgr->minfo.dvaddr_3dnr = resourcemgr->minfo.dvaddr + offset; resourcemgr->minfo.kvaddr_3dnr = resourcemgr->minfo.kvaddr + offset; offset += (SIZE_DNR_INTERNAL_BUF * NUM_DNR_INTERNAL_BUF); #else resourcemgr->minfo.dvaddr_3dnr = 0; resourcemgr->minfo.kvaddr_3dnr = 0; #endif #ifdef ENABLE_FD_SW for (num_buf = 0; num_buf < NUM_FD_INTERNAL_BUF; num_buf++) { resourcemgr->minfo.dvaddr_fd[num_buf] = resourcemgr->minfo.dvaddr + offset; resourcemgr->minfo.kvaddr_fd[num_buf] = resourcemgr->minfo.kvaddr + offset; offset += (SIZE_FD_INTERNEL_BUF); } #else memset(&resourcemgr->minfo.dvaddr_fd, 0, sizeof(resourcemgr->minfo.dvaddr_fd)); memset(&resourcemgr->minfo.kvaddr_fd, 0, sizeof(resourcemgr->minfo.dvaddr_fd)); #endif #ifdef ENABLE_FD_DMA_INPUT for (fd_buf = 0; fd_buf < MAX_FD_SHOT_BUF; fd_buf++) { resourcemgr->minfo.dvaddr_fdshot[fd_buf] = resourcemgr->minfo.dvaddr + offset; resourcemgr->minfo.kvaddr_fdshot[fd_buf] = resourcemgr->minfo.kvaddr + offset; offset += (SIZE_FD_SHOT_BUF); } #endif dbg_core("fimc_is_init_mem done\n"); p_err: return ret; }