void ddramc_print_config_regs(unsigned int base_address)
{
dbg_very_loud("\n\nMPDDR Controller Registers configurations:\n");
dbg_very_loud("MPDDRC_MDR: %d\n",
read_ddramc(base_address, HDDRSDRC2_MDR));
dbg_very_loud("MPDDRC_READ_DATA_PATH: %d\n",
read_ddramc(base_address, MPDDRC_RD_DATA_PATH));
dbg_very_loud("MPDDRC_IO_CALIBR: %d\n",
read_ddramc(base_address, MPDDRC_IO_CALIBR));
dbg_very_loud("MPDDRC_TPR0: %d\n",
read_ddramc(base_address, HDDRSDRC2_T0PR));
dbg_very_loud("MPDDRC_TPR1: %d\n",
read_ddramc(base_address, HDDRSDRC2_T1PR));
dbg_very_loud("MPDDRC_TPR2: %d\n",
read_ddramc(base_address, HDDRSDRC2_T2PR));
dbg_very_loud("MPDDRC_RTR: %d\n",
read_ddramc(base_address, HDDRSDRC2_RTR));
dbg_very_loud("MPDDRC_CR: %d\n",
read_ddramc(base_address, HDDRSDRC2_CR));
}
int ddram_initialize(unsigned int base_address,
unsigned int ram_address,
struct ddramc_register *ddramc_config)
{
unsigned int ba_offset;
unsigned int cr = 0;
/* compute BA[] offset according to CR configuration */
ba_offset = (ddramc_config->cr & AT91C_DDRC2_NC) + 9;
if (ddramc_decodtype_is_seq(ddramc_config->cr))
ba_offset += ((ddramc_config->cr & AT91C_DDRC2_NR) >> 2) + 11;
ba_offset += (ddramc_config->mdr & AT91C_DDRC2_DBW) ? 1 : 2;
dbg_very_loud(" ba_offset = %x ...\n", ba_offset);
/*
* Step 1: Program the memory device type into the Memory Device Register
*/
write_ddramc(base_address, HDDRSDRC2_MDR, ddramc_config->mdr);
/*
* Step 2: Program the feature of DDR2-SDRAM device into
* the Timing Register, and into the Configuration Register
*/
write_ddramc(base_address, HDDRSDRC2_CR, ddramc_config->cr);
write_ddramc(base_address, HDDRSDRC2_T0PR, ddramc_config->t0pr);
write_ddramc(base_address, HDDRSDRC2_T1PR, ddramc_config->t1pr);
write_ddramc(base_address, HDDRSDRC2_T2PR, ddramc_config->t2pr);
/*
* Step 3: An NOP command is issued to the DDR2-SDRAM
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_NOP_CMD);
*((unsigned volatile int *)ram_address) = 0;
/* Now, clocks which drive the DDR2-SDRAM device are enabled */
/* A minimum pause wait 200 us is provided to precede any signal toggle.
(6 core cycles per iteration, core is at 396MHz: min 13340 loops) */
udelay(200);
/*
* Step 4: An NOP command is issued to the DDR2-SDRAM
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_NOP_CMD);
*((unsigned volatile int *)ram_address) = 0;
/* Now, CKE is driven high */
/* wait 400 ns min */
udelay(1);
/*
* Step 5: An all banks precharge command is issued to the DDR2-SDRAM.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_PRCGALL_CMD);
*((unsigned volatile int *)ram_address) = 0;
/* wait 2 cycles min (of tCK) = 15 ns min */
udelay(1);
/*
* Step 6: An Extended Mode Register set(EMRS2) cycle is issued to chose between commercial or high
* temperature operations.
* Perform a write access to DDR2-SDRAM to acknowledge this command.
* The write address must be chosen so that BA[1] is set to 1 and BA[0] is set to 0.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*((unsigned int *)(ram_address + (0x2 << ba_offset))) = 0;
/* wait 2 cycles min (of tCK) = 15 ns min */
udelay(1);
/*
* Step 7: An Extended Mode Register set(EMRS3) cycle is issued
* to set the Extended Mode Register to "0".
* Perform a write access to DDR2-SDRAM to acknowledge this command.
* The write address must be chosen so that BA[1] is set to 1 and BA[0] is set to 1.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*((unsigned int *)(ram_address + (0x3 << ba_offset))) = 0;
/* wait 2 cycles min (of tCK) = 15 ns min */
udelay(1);
/*
* Step 8: An Extened Mode Register set(EMRS1) cycle is issued to enable DLL,
* and to program D.I.C(Output Driver Impedance Control)
* Perform a write access to DDR2-SDRAM to acknowledge this command.
* The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*((unsigned int *)(ram_address + (0x1 << ba_offset))) = 0;
/* An additional 200 cycles of clock are required for locking DLL */
udelay(1);
/*
* Step 9: Program DLL field into the Configuration Register to high(Enable DLL reset)
*/
cr = read_ddramc(base_address, HDDRSDRC2_CR);
write_ddramc(base_address, HDDRSDRC2_CR, cr | AT91C_DDRC2_DLL_RESET_ENABLED);
/*
* Step 10: A Mode Register set(MRS) cycle is issied to reset DLL.
* Perform a write access to DDR2-SDRAM to acknowledge this command.
* The write address must be chosen so that BA[1:0] bits are set to 0.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_LMR_CMD);
*((unsigned int *)(ram_address + (0x0 << ba_offset))) = 0;
/* wait 2 cycles min (of tCK) = 15 ns min */
udelay(1);
/*
* Step 11: An all banks precharge command is issued to the DDR2-SDRAM.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_PRCGALL_CMD);
*(((unsigned volatile int *)ram_address)) = 0;
/* wait 400 ns min (not needed on certain DDR2 devices) */
udelay(1);
/*
* Step 12: Two auto-refresh (CBR) cycles are provided.
* Program the auto refresh command (CBR) into the Mode Register.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_RFSH_CMD);
*(((unsigned volatile int *)ram_address)) = 0;
/* wait TRFC cycles min (135 ns min) extended to 400 ns */
udelay(1);
/* Set 2nd CBR */
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_RFSH_CMD);
*(((unsigned volatile int *)ram_address)) = 0;
/* wait TRFC cycles min (135 ns min) extended to 400 ns */
udelay(1);
/*
* Step 13: Program DLL field into the Configuration Register to low(Disable DLL reset).
*/
cr = read_ddramc(base_address, HDDRSDRC2_CR);
write_ddramc(base_address, HDDRSDRC2_CR, cr & (~AT91C_DDRC2_DLL_RESET_ENABLED));
/*
* Step 14: A Mode Register set (MRS) cycle is issued to program
* the parameters of the DDR2-SDRAM devices, in particular CAS latency,
* burst length and to disable DDL reset.
* Perform a write access to DDR2-SDRAM to acknowledge this command.
* The write address must be chosen so that BA[1:0] bits are set to 0.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_LMR_CMD);
*((unsigned int *)(ram_address + (0x0 << ba_offset))) = 0;
/* wait 2 cycles min (of tCK) = 15 ns min */
udelay(1);
/*
* Step 15: Program OCD field into the Configuration Register
* to high (OCD calibration default).
*/
cr = read_ddramc(base_address, HDDRSDRC2_CR);
write_ddramc(base_address, HDDRSDRC2_CR, cr | AT91C_DDRC2_OCD_DEFAULT);
/* wait 2 cycles min (of tCK) = 15 ns min */
udelay(1);
/*
* Step 16: An Extended Mode Register set (EMRS1) cycle is issued to OCD default value.
* Perform a write access to DDR2-SDRAM to acknowledge this command.
* The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*((unsigned int *)(ram_address + (0x1 << ba_offset))) = 0;
/* wait 2 cycles min (of tCK) = 15 ns min */
udelay(1);
/*
* Step 17: Program OCD field into the Configuration Register
* to low (OCD calibration mode exit).
*/
cr = read_ddramc(base_address, HDDRSDRC2_CR);
write_ddramc(base_address, HDDRSDRC2_CR, cr & (~AT91C_DDRC2_OCD_DEFAULT));
/* wait 2 cycles min (of tCK) = 15 ns min */
udelay(1);
/*
* Step 18: An Extended Mode Register set (EMRS1) cycle is issued to enable OCD exit.
* Perform a write access to DDR2-SDRAM to acknowledge this command.
* The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*((unsigned int *)(ram_address + (0x1 << ba_offset))) = 0;
/* wait 2 cycles min (of tCK) = 15 ns min */
udelay(1);
/*
* Step 19: A Nornal mode command is provided.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_NORMAL_CMD);
*(((unsigned volatile int *)ram_address)) = 0;
/*
* Step 20: Perform a write access to any DDR2-SDRAM address
*/
*(((unsigned volatile int *)ram_address)) = 0;
/*
* Step 21: Write the refresh rate into the count field in the Refresh Timer register.
*/
write_ddramc(base_address, HDDRSDRC2_RTR, ddramc_config->rtr);
/*
* Now we are ready to work on the DDRSDR
* wait for end of calibration
*/
udelay(10);
return 0;
}
int ddr3_sdram_initialize(unsigned int base_address,
unsigned int ram_address,
struct ddramc_register *ddramc_config)
{
unsigned int ba_offset;
/* Compute BA[] offset according to CR configuration */
ba_offset = (ddramc_config->cr & AT91C_DDRC2_NC) + 9;
if (!(ddramc_config->cr & AT91C_DDRC2_DECOD_INTERLEAVED))
ba_offset += ((ddramc_config->cr & AT91C_DDRC2_NR) >> 2) + 11;
ba_offset += (ddramc_config->mdr & AT91C_DDRC2_DBW) ? 1 : 2;
dbg_very_loud(" ba_offset = %x ...\n", ba_offset);
/*
* Step 1: Program the memory device type in the MPDDRC Memory Device Register
*/
write_ddramc(base_address, HDDRSDRC2_MDR, ddramc_config->mdr);
/*
* Step 2: Program features of the DDR3-SDRAM device in the MPDDRC
* Configuration Register and in the MPDDRC Timing Parameter 0 Register
* /MPDDRC Timing Parameter 1 Register
*/
write_ddramc(base_address, HDDRSDRC2_CR, ddramc_config->cr);
write_ddramc(base_address, HDDRSDRC2_T0PR, ddramc_config->t0pr);
write_ddramc(base_address, HDDRSDRC2_T1PR, ddramc_config->t1pr);
write_ddramc(base_address, HDDRSDRC2_T2PR, ddramc_config->t2pr);
/*
* Step 3: A NOP command is issued to the DDR3-SRAM.
* Program the NOP command in the MPDDRC Mode Register (MPDDRC_MR).
* The application must write a one to the MODE field in the MPDDRC_MR
* Perform a write access to any DDR3-SDRAM address to acknowledge this command.
* The clock which drive the DDR3-SDRAM device are now enabled.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_NOP_CMD);
*((unsigned volatile int *)ram_address) = 0;
/*
* Step 4: A pause of at least 500us must be observed before a single toggle.
*/
udelay(500);
/*
* Step 5: A NOP command is issued to the DDR3-SDRAM
* Program the NOP command in the MPDDRC_MR.
* The application must write a one to the MODE field in the MPDDRC_MR.
* Perform a write access to any DDR3-SDRAM address to acknowledge this command.
* CKE is now driven high.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_NOP_CMD);
*((unsigned volatile int *)ram_address) = 0;
/*
* Step 6: An Extended Mode Register Set (EMRS2) cycle is issued to choose
* between commercial or high temperature operations. The application must
* write a five to the MODE field in the MPDDRC_MR and perform a write
* access to the DDR3-SDRAM to acknowledge this command.
* The write address must be chosen so that signal BA[2] is set to 0,
* BA[1] is set to 1 and signal BA[0] is set to 0.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*((unsigned int *)(ram_address + (0x2 << ba_offset))) = 0;
/*
* Step 7: An Extended Mode Register Set (EMRS3) cycle is issued to set
* the Extended Mode Register to 0. The application must write a five
* to the MODE field in the MPDDRC_MR and perform a write access to the
* DDR3-SDRAM to acknowledge this command. The write address must be
* chosen so that signal BA[2] is set to 0, BA[1] is set to 1 and signal
* BA[0] is set to 1.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*((unsigned int *)(ram_address + (0x3 << ba_offset))) = 0;
/*
* Step 8: An Extended Mode Register Set (EMRS1) cycle is issued to
* disable and to program O.D.S. (Output Driver Strength).
* The application must write a five to the MODE field in the MPDDRC_MR
* and perform a write access to the DDR3-SDRAM to acknowledge this command.
* The write address must be chosen so that signal BA[2:1] is set to 0
* and signal BA[0] is set to 1.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*((unsigned int *)(ram_address + (0x1 << ba_offset))) = 0;
/*
* Step 9: Write a one to the DLL bit (enable DLL reset) in the MPDDRC
* Configuration Register (MPDDRC_CR)
*/
#if 0
cr = read_ddramc(base_address, HDDRSDRC2_CR);
write_ddramc(base_address, HDDRSDRC2_CR, cr | AT91C_DDRC2_DLL_RESET_ENABLED);
#endif
/*
* Step 10: A Mode Register Set (MRS) cycle is issued to reset DLL.
* The application must write a three to the MODE field in the MPDDRC_MR
* and perform a write access to the DDR3-SDRAM to acknowledge this command.
* The write address must be chosen so that signals BA[2:0] are set to 0
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_LMR_CMD);
*((unsigned int *)ram_address) = 0;
udelay(50);
/*
* Step 11: A Calibration command (MRS) is issued to calibrate RTT and
* RON values for the Process Voltage Temperature (PVT).
* The application must write a six to the MODE field in the MPDDRC_MR
* and perform a write access to the DDR3-SDRAM to acknowledge this command.
* The write address must be chosen so that signals BA[2:0] are set to 0.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_DEEP_CMD);
*((unsigned int *)ram_address) = 0;
/*
* Step 12: A Normal Mode command is provided.
* Program the Normal mode in the MPDDRC_MR and perform a write access
* to any DDR3-SDRAM address to acknowledge this command.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_NORMAL_CMD);
*((unsigned int *)ram_address) = 0;
/*
* Step 13: Perform a write access to any DDR3-SDRAM address.
*/
*((unsigned int *)ram_address) = 0;
/*
* Step 14: Write the refresh rate into the COUNT field in the MPDDRC
* Refresh Timer Register (MPDDRC_RTR):
* refresh rate = delay between refresh cycles.
* The DDR3-SDRAM device requires a refresh every 7.81 us.
*/
write_ddramc(base_address, HDDRSDRC2_RTR, ddramc_config->rtr);
return 0;
}
int lpddr1_sdram_initialize(unsigned int base_address,
unsigned int ram_address,
struct ddramc_register *ddramc_config)
{
unsigned int ba_offset;
/* Compute BA[] offset according to CR configuration */
ba_offset = (ddramc_config->cr & AT91C_DDRC2_NC) + 8;
if (!(ddramc_config->cr & AT91C_DDRC2_DECOD_INTERLEAVED))
ba_offset += ((ddramc_config->cr & AT91C_DDRC2_NR) >> 2) + 11;
ba_offset += (ddramc_config->mdr & AT91C_DDRC2_DBW) ? 1 : 2;
dbg_very_loud(" ba_offset = %x ...\n", ba_offset);
/*
* Step 1: Program the memory device type in the MPDDRC Memory Device Register
*/
write_ddramc(base_address, HDDRSDRC2_MDR, ddramc_config->mdr);
/*
* Step 2: Program the features of the low-power DDR1-SDRAM device
* in the MPDDRC Configuration Register and in the MPDDRC Timing
* Parameter 0 Register/MPDDRC Timing Parameter 1 Register.
*/
write_ddramc(base_address, HDDRSDRC2_CR, ddramc_config->cr);
write_ddramc(base_address, HDDRSDRC2_T0PR, ddramc_config->t0pr);
write_ddramc(base_address, HDDRSDRC2_T1PR, ddramc_config->t1pr);
write_ddramc(base_address, HDDRSDRC2_T2PR, ddramc_config->t2pr);
/*
* Step 3: Program Temperature Compensated Self-refresh (TCR),
* Partial Array Self-refresh (PASR) and Drive Strength (DS) parameters
* in the MPDDRC Low-power Register.
*/
write_ddramc(base_address, HDDRSDRC2_LPR, ddramc_config->lpr);
/*
* Step 4: A NOP command is issued to the low-power DDR1-SDRAM.
* Program the NOP command in the MPDDRC Mode Register (MPDDRC_MR).
* The clocks which drive the low-power DDR1-SDRAM device
* are now enabled.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_NOP_CMD);
*((unsigned volatile int *)ram_address) = 0;
/*
* Step 5: A pause of at least 200 us must be observed before
* a signal toggle.
*/
udelay(200);
/*
* Step 6: A NOP command is issued to the low-power DDR1-SDRAM.
* Program the NOP command in the MPDDRC_MR. calibration request is
* now made to the I/O pad.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_NOP_CMD);
*((unsigned volatile int *)ram_address) = 0;
/*
* Step 7: An All Banks Precharge command is issued
* to the low-power DDR1-SDRAM.
* Program All Banks Precharge command in the MPDDRC_MR.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_PRCGALL_CMD);
*((unsigned volatile int *)ram_address) = 0;
/*
* Step 8: Two auto-refresh (CBR) cycles are provided.
* Program the Auto Refresh command (CBR) in the MPDDRC_MR.
* The application must write a four to the MODE field
* in the MPDDRC_MR. Perform a write access to any low-power
* DDR1-SDRAM location twice to acknowledge these commands.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_RFSH_CMD);
*((unsigned volatile int *)ram_address) = 0;
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_RFSH_CMD);
*((unsigned volatile int *)ram_address) = 0;
/*
* Step 9: An Extended Mode Register Set (EMRS) cycle is issued to
* program the low-power DDR1-SDRAM parameters (TCSR, PASR, DS).
* The application must write a five to the MODE field in the MPDDRC_MR
* and perform a write access to the SDRAM to acknowledge this command.
* The write address must be chosen so that signal BA[1] is set to 1
* and BA[0] is set to 0.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*((unsigned volatile int *)(ram_address + (0x2 << ba_offset))) = 0;
/*
* Step 10: A Mode Register Set (MRS) cycle is issued to program
* parameters of the low-power DDR1-SDRAM devices, in particular
* CAS latency.
* The application must write a three to the MODE field in the MPDDRC_MR
* and perform a write access to the SDRAM to acknowledge this command.
* The write address must be chosen so that signals BA[1:0] are set to 0.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_LMR_CMD);
*((unsigned volatile int *)(ram_address + (0x0 << ba_offset))) = 0;
/*
* Step 11: The application must enter Normal mode, write a zero
* to the MODE field in the MPDDRC_MR and perform a write access
* at any location in the SDRAM to acknowledge this command.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_NORMAL_CMD);
*((unsigned volatile int *)ram_address) = 0;
/*
* Step 12: Perform a write access to any low-power DDR1-SDRAM address.
*/
*((unsigned volatile int *)ram_address) = 0;
/*
* Step 14: Write the refresh rate into the COUNT field in the MPDDRC
* Refresh Timer Register (MPDDRC_RTR):
*/
write_ddramc(base_address, HDDRSDRC2_RTR, ddramc_config->rtr);
return 0;
}
