void lcd5510_command( unsigned char d ){
dc_set( 0 );
sce_set( 0 );
lcd5510_send_byte( d );
sce_set( 1 );
}
void lcd5510_data( unsigned char d ){
dc_set( 1 );
sce_set( 0 );
lcd5510_send_byte( d );
sce_set( 1 );
}
void hp_nanoprocessor_device::execute_one(uint8_t opcode)
{
// Instructions without mask
switch (opcode) {
case 0x00:
// INB
m_reg_A++;
if (m_reg_A == 0) {
BIT_SET(m_flags, NANO_E_BIT);
}
break;
case 0x01:
// DEB
m_reg_A--;
if (m_reg_A == 0xff) {
BIT_SET(m_flags, NANO_E_BIT);
}
break;
case 0x02:
// IND
// Handling of non-decimal digits is entirely arbitrary
m_reg_A++;
if ((m_reg_A & 0x0f) >= 10) {
m_reg_A += 6;
if (m_reg_A >= 0xa0) {
m_reg_A += 0x60;
BIT_SET(m_flags, NANO_E_BIT);
}
}
break;
case 0x03:
// DED
// Handling of non-decimal digits is entirely arbitrary
m_reg_A--;
if ((m_reg_A & 0x0f) >= 10) {
m_reg_A -= 6;
if (m_reg_A >= 0xa0) {
m_reg_A -= 0x60;
BIT_SET(m_flags, NANO_E_BIT);
}
}
break;
case 0x04:
// CLA
m_reg_A = 0;
break;
case 0x05:
// CMA
m_reg_A = ~m_reg_A;
break;
case 0x06:
// RSA
m_reg_A >>= 1;
break;
case 0x07:
// LSA
m_reg_A <<= 1;
break;
case 0x08:
// SGT
if (m_reg_A > m_reg_R[ 0 ]) {
skip();
}
break;
case 0x09:
// SLT
if (m_reg_A < m_reg_R[ 0 ]) {
skip();
}
break;
case 0x0a:
// SEQ
if (m_reg_A == m_reg_R[ 0 ]) {
skip();
}
break;
case 0x0b:
// SAZ
if (m_reg_A == 0) {
skip();
}
break;
case 0x0c:
// SLE
if (m_reg_A <= m_reg_R[ 0 ]) {
skip();
}
break;
case 0x0d:
// SGE
if (m_reg_A >= m_reg_R[ 0 ]) {
skip();
}
break;
case 0x0e:
// SNE
if (m_reg_A != m_reg_R[ 0 ]) {
skip();
}
break;
case 0x0f:
// SAN
if (m_reg_A != 0) {
skip();
}
break;
case 0x1f:
// SES
if (BIT(m_flags , NANO_E_BIT)) {
skip();
}
break;
case 0x3f:
// SEZ
if (!BIT(m_flags , NANO_E_BIT)) {
skip();
}
break;
case 0x5f:
// NOP
break;
case 0xb1:
// RTE
dc_set(HP_NANO_IE_DC);
// Intentional fall-through to RTI!
case 0xb0:
// RTI
m_reg_PA = m_reg_ISR;
break;
case 0xb4:
// STE
BIT_SET(m_flags, NANO_E_BIT);
break;
case 0xb5:
// CLE
BIT_CLR(m_flags, NANO_E_BIT);
break;
case 0xb9:
// RSE
dc_set(HP_NANO_IE_DC);
// Intentional fall-through to RTS!
case 0xb8:
// RTS
{
uint16_t tmp = m_reg_SSR;
m_reg_SSR = pa_offset(1);
m_reg_PA = tmp;
}
break;
case 0xcf:
// LDR
m_reg_A = fetch();
break;
default:
// Instructions with 0xf8 mask
switch (opcode & 0xf8) {
case 0x10:
// SBS
if (BIT(m_reg_A , opcode & 7)) {
skip();
}
break;
case 0x18:
// SFS
{
uint8_t tmp = m_read_dc_func();
tmp &= (uint8_t)(m_flags >> NANO_DC0_BIT);
if (BIT(tmp , opcode & 7)) {
skip();
}
}
break;
case 0x20:
// SBN
BIT_SET(m_reg_A, opcode & 7);
break;
case 0x28:
// STC
dc_set(opcode & 7);
break;
case 0x30:
// SBZ
if (!BIT(m_reg_A , opcode & 7)) {
skip();
}
break;
case 0x38:
// SFZ
{
uint8_t tmp = m_read_dc_func();
tmp &= (uint8_t)(m_flags >> NANO_DC0_BIT);
if (!BIT(tmp , opcode & 7)) {
skip();
}
}
break;
case 0x80:
// JMP
m_reg_PA = ((uint16_t)(opcode & 7) << 8) | fetch();
break;
case 0x88:
// JSB
{
uint16_t tmp = ((uint16_t)(opcode & 7) << 8) | fetch();
m_reg_SSR = m_reg_PA;
m_reg_PA = tmp;
}
break;
case 0x98:
// JAS
m_reg_SSR = pa_offset(1);
// Intentional fall-through to JAI!
case 0x90:
// JAI
// On HP doc there's a mysterious warning about JAI:
// "Due to the indexing structure, a JAI instruction executed with
// R03 set will be executed as a JAS instruction"
// My idea on the meaning: NP recycles the instruction register to form
// the bitwise OR of bits 3-0 of R0 and of opcode (see LDI/STI
// instructions). Presumably this was done to save on flip-flop count.
// So, if bit 3 of R0 (R03) is set when executing JAI the instruction
// register turns JAI into JAS.
// This effect is not simulated here at the moment.
{
uint16_t tmp = (uint16_t)((m_reg_R[ 0 ] | opcode) & 7) << 8;
m_reg_PA = tmp | m_reg_A;
}
break;
case 0xa0:
// CBN
BIT_CLR(m_reg_A, opcode & 7);
break;
case 0xa8:
// CLC
dc_clr(opcode & 7);
break;
default:
// Instructions with 0xf0 mask
switch (opcode & 0xf0) {
case 0x40:
// INA
m_reg_A = m_io->read_byte(opcode & 0xf);
break;
case 0x50:
// OTA
m_io->write_byte(opcode & 0xf , m_reg_A);
break;
case 0x60:
// LDA
m_reg_A = m_reg_R[ opcode & 0xf ];
break;
case 0x70:
// STA
m_reg_R[ opcode & 0xf ] = m_reg_A;
break;
case 0xc0:
// OTR
m_io->write_byte(opcode & 0xf , fetch());
break;
case 0xd0:
// STR
m_reg_R[ opcode & 0xf ] = fetch();
break;
case 0xe0:
// LDI
m_reg_A = m_reg_R[ (m_reg_R[ 0 ] | opcode) & 0xf ];
break;
case 0xf0:
// STI
m_reg_R[ (m_reg_R[ 0 ] | opcode) & 0xf ] = m_reg_A;
break;
default:
logerror("Unknown opcode %02x @ 0x03x\n" , opcode , m_reg_PA);
break;
}
}
}
}
