Beispiel #1
0
MACHINE_RESET_MEMBER(midwunit_state,midwunit)
{
	int i;

	/* reset sound */
	dcs_reset_w(machine(), 1);
	dcs_reset_w(machine(), 0);

	/* reset I/O shuffling */
	for (i = 0; i < 16; i++)
		m_ioshuffle[i] = i % 8;
}
Beispiel #2
0
MACHINE_RESET_MEMBER(midxunit_state,midxunit)
{
	int i;

	/* reset sound */
	dcs_reset_w(machine(), 1);
	dcs_reset_w(machine(), 0);

	/* reset I/O shuffling */
	for (i = 0; i < 16; i++)
		m_ioshuffle[i] = i % 8;

	dcs_set_io_callbacks(midxunit_dcs_output_full, NULL);
}
static WRITE32_HANDLER( kinst_control_w )
{
	UINT32 olddata;

	/* apply shuffling */
	offset = control_map[offset / 2];
	olddata = kinst_control[offset];
	COMBINE_DATA(&kinst_control[offset]);

	switch (offset)
	{
		case 0:		/* $80 - VRAM buffer control */
			if (data & 4)
				video_base = &rambase[0x58000/4];
			else
				video_base = &rambase[0x30000/4];
			break;

		case 1:		/* $88 - sound reset */
			dcs_reset_w(~data & 0x01);
			break;

		case 2:		/* $90 - sound control */
			if (!(olddata & 0x02) && (kinst_control[offset] & 0x02))
				dcs_data_w(kinst_control[3]);
			break;

		case 3:		/* $98 - sound data */
			break;
	}
}
static MACHINE_RESET( kinst )
{
	/* set the fastest DRC options */
	cpunum_set_info_int(0, CPUINFO_INT_MIPS3_DRC_OPTIONS, MIPS3DRC_FASTEST_OPTIONS);

	/* configure fast RAM regions for DRC */
	cpunum_set_info_int(0, CPUINFO_INT_MIPS3_FASTRAM_SELECT, 0);
	cpunum_set_info_int(0, CPUINFO_INT_MIPS3_FASTRAM_START, 0x08000000);
	cpunum_set_info_int(0, CPUINFO_INT_MIPS3_FASTRAM_END, 0x087fffff);
	cpunum_set_info_ptr(0, CPUINFO_PTR_MIPS3_FASTRAM_BASE, rambase2);
	cpunum_set_info_int(0, CPUINFO_INT_MIPS3_FASTRAM_READONLY, 0);

	cpunum_set_info_int(0, CPUINFO_INT_MIPS3_FASTRAM_SELECT, 1);
	cpunum_set_info_int(0, CPUINFO_INT_MIPS3_FASTRAM_START, 0x00000000);
	cpunum_set_info_int(0, CPUINFO_INT_MIPS3_FASTRAM_END, 0x0007ffff);
	cpunum_set_info_ptr(0, CPUINFO_PTR_MIPS3_FASTRAM_BASE, rambase);
	cpunum_set_info_int(0, CPUINFO_INT_MIPS3_FASTRAM_READONLY, 0);

	cpunum_set_info_int(0, CPUINFO_INT_MIPS3_FASTRAM_SELECT, 2);
	cpunum_set_info_int(0, CPUINFO_INT_MIPS3_FASTRAM_START, 0x1fc00000);
	cpunum_set_info_int(0, CPUINFO_INT_MIPS3_FASTRAM_END, 0x1fc7ffff);
	cpunum_set_info_ptr(0, CPUINFO_PTR_MIPS3_FASTRAM_BASE, rombase);
	cpunum_set_info_int(0, CPUINFO_INT_MIPS3_FASTRAM_READONLY, 1);

	/* keep the DCS held in reset at startup */
	dcs_reset_w(1);

	/* reset the IDE controller */
	ide_controller_reset(0);

	/* set a safe base location for video */
	video_base = &rambase[0x30000/4];
}
Beispiel #5
0
static WRITE32_HANDLER( kinst_control_w )
{
	kinst_state *state = space->machine().driver_data<kinst_state>();
	UINT32 olddata;

	/* apply shuffling */
	offset = state->m_control_map[offset / 2];
	olddata = state->m_control[offset];
	COMBINE_DATA(&state->m_control[offset]);

	switch (offset)
	{
		case 0:		/* $80 - VRAM buffer control */
			if (data & 4)
				state->m_video_base = &state->m_rambase[0x58000/4];
			else
				state->m_video_base = &state->m_rambase[0x30000/4];
			break;

		case 1:		/* $88 - sound reset */
			dcs_reset_w(space->machine(), ~data & 0x01);
			break;

		case 2:		/* $90 - sound control */
			if (!(olddata & 0x02) && (state->m_control[offset] & 0x02))
				dcs_data_w(space->machine(), state->m_control[3]);
			break;

		case 3:		/* $98 - sound data */
			break;
	}
}
Beispiel #6
0
MACHINE_RESET_MEMBER(midtunit_state,midtunit)
{
	/* reset sound */
	switch (chip_type)
	{
		case SOUND_ADPCM:
		case SOUND_ADPCM_LARGE:
			m_adpcm_sound->reset_write(1);
			m_adpcm_sound->reset_write(0);
			break;

		case SOUND_DCS:
			dcs_reset_w(machine(), 1);
			dcs_reset_w(machine(), 0);
			break;
	}
}
Beispiel #7
0
static MACHINE_INIT( kinst )
{
	/* set the fastest DRC options */
	cpunum_set_info_int(0, CPUINFO_INT_MIPS3_DRC_OPTIONS, MIPS3DRC_FASTEST_OPTIONS);

	/* both games map one logical 4k page at address 0 to physical address 0x8090000 */
	memory_install_read32_handler(0, ADDRESS_SPACE_PROGRAM, 0x00000000, 0x00000fff, 0, 0, MRA32_BANK1);
	memory_install_write32_handler(0, ADDRESS_SPACE_PROGRAM, 0x00000000, 0x00000fff, 0, 0, MWA32_BANK1);
	cpu_setbank(1, &rambase2[0x90000/4]);

	/* keep the DCS held in reset at startup */
	dcs_reset_w(1);

	/* reset the IDE controller */
	ide_controller_reset(0);

	/* set a safe base location for video */
	video_base = &rambase[0x30000/4];
}
Beispiel #8
0
void atlantis_state::machine_reset()
{
	dcs_reset_w(machine(), 1);
	dcs_reset_w(machine(), 0);
}