/*
* Initialize device structure. Returns success if
* initialization succeeded.
*/
static int gfar_probe(struct device_d *dev)
{
struct gfar_info_struct *gfar_info = dev->platform_data;
struct eth_device *edev;
struct gfar_private *priv;
size_t size;
char *p;
priv = xzalloc(sizeof(struct gfar_private));
if (NULL == priv)
return -ENODEV;
edev = &priv->edev;
priv->regs = dev_request_mem_region(dev, 0);
priv->phyregs = dev_request_mem_region(dev, 1);
priv->phyregs_sgmii = dev_request_mem_region(dev, 2);
priv->phyaddr = gfar_info->phyaddr;
priv->tbicr = gfar_info->tbicr;
priv->tbiana = gfar_info->tbiana;
/*
* Allocate descriptors 64-bit aligned. Descriptors
* are 8 bytes in size.
*/
size = ((TX_BUF_CNT * sizeof(struct txbd8)) +
(RX_BUF_CNT * sizeof(struct rxbd8))) + BUF_ALIGN;
p = (char *)xmemalign(BUF_ALIGN, size);
priv->txbd = (struct txbd8 *)p;
priv->rxbd = (struct rxbd8 *)(p + (TX_BUF_CNT * sizeof(struct txbd8)));
edev->priv = priv;
edev->init = gfar_init;
edev->open = gfar_open;
edev->halt = gfar_halt;
edev->send = gfar_send;
edev->recv = gfar_recv;
edev->get_ethaddr = gfar_get_ethaddr;
edev->set_ethaddr = gfar_set_ethaddr;
edev->parent = dev;
setbits_be32(priv->regs + GFAR_MACCFG1_OFFSET, GFAR_MACCFG1_SOFT_RESET);
udelay(2);
clrbits_be32(priv->regs + GFAR_MACCFG1_OFFSET, GFAR_MACCFG1_SOFT_RESET);
priv->miibus.read = gfar_miiphy_read;
priv->miibus.write = gfar_miiphy_write;
priv->miibus.priv = priv;
priv->miibus.parent = dev;
gfar_init_phy(edev);
mdiobus_register(&priv->miibus);
return eth_register(edev);
}
static int clps711x_gpio_probe(struct device_d *dev)
{
int err, id = dev->id;
void __iomem *dat, *dir = NULL, *dir_inv = NULL;
struct bgpio_chip *bgc;
if (dev->device_node)
id = of_alias_get_id(dev->device_node, "gpio");
if (id < 0 || id > 4)
return -ENODEV;
dat = dev_request_mem_region(dev, 0);
if (IS_ERR(dat))
return PTR_ERR(dat);
switch (id) {
case 3:
dir_inv = dev_request_mem_region(dev, 1);
if (IS_ERR(dir_inv))
return PTR_ERR(dir_inv);
break;
default:
dir = dev_request_mem_region(dev, 1);
if (IS_ERR(dir))
return PTR_ERR(dir);
break;
}
bgc = xzalloc(sizeof(struct bgpio_chip));
if (!bgc)
return -ENOMEM;
err = bgpio_init(bgc, dev, 1, dat, NULL, NULL, dir, dir_inv, 0);
if (err)
goto out_err;
bgc->gc.base = id * 8;
switch (id) {
case 4:
bgc->gc.ngpio = 3;
break;
default:
break;
}
err = gpiochip_add(&bgc->gc);
out_err:
if (err)
free(bgc);
return err;
}
static int imx28_wd_probe(struct device_d *dev)
{
struct imx28_wd *priv;
int rc;
priv = xzalloc(sizeof(struct imx28_wd));
priv->regs = dev_request_mem_region(dev, 0);
priv->wd.set_timeout = imx28_watchdog_set_timeout;
if (!(readl(priv->regs + MXS_RTC_STAT) & MXS_RTC_STAT_WD_PRESENT)) {
rc = -ENODEV;
goto on_error;
}
/* disable the debug feature to ensure a working WD */
writel(0x00000000, priv->regs + MXS_RTC_DEBUG);
rc = watchdog_register(&priv->wd);
if (rc != 0)
goto on_error;
if (IS_ENABLED(CONFIG_RESET_SOURCE))
imx28_detect_reset_source(priv);
dev->priv = priv;
return 0;
on_error:
free(priv);
return rc;
}
static int mxs_mci_probe(struct device_d *hw_dev)
{
struct mxs_mci_platform_data *pd = hw_dev->platform_data;
struct mxs_mci_host *mxs_mci;
struct mci_host *host;
unsigned long rate;
if (hw_dev->platform_data == NULL) {
dev_err(hw_dev, "Missing platform data\n");
return -EINVAL;
}
mxs_mci = xzalloc(sizeof(*mxs_mci));
host = &mxs_mci->host;
hw_dev->priv = mxs_mci;
host->hw_dev = hw_dev;
host->send_cmd = mxs_mci_request;
host->set_ios = mxs_mci_set_ios;
host->init = mxs_mci_initialize;
mxs_mci->regs = dev_request_mem_region(hw_dev, 0);
/* feed forward the platform specific values */
host->voltages = pd->voltages;
host->host_caps = pd->caps;
host->devname = pd->devname;
mxs_mci->clk = clk_get(hw_dev, NULL);
if (IS_ERR(mxs_mci->clk))
return PTR_ERR(mxs_mci->clk);
clk_enable(mxs_mci->clk);
rate = clk_get_rate(mxs_mci->clk);
if (pd->f_min == 0) {
host->f_min = rate / 254 / 256;
dev_dbg(hw_dev, "Min. frequency is %u Hz\n", host->f_min);
} else {
host->f_min = pd->f_min;
dev_dbg(hw_dev, "Min. frequency is %u Hz, could be %lu Hz\n",
host->f_min, rate / 254 / 256);
}
if (pd->f_max == 0) {
host->f_max = rate / 2 / 1;
dev_dbg(hw_dev, "Max. frequency is %u Hz\n", host->f_max);
} else {
host->f_max = pd->f_max;
dev_dbg(hw_dev, "Max. frequency is %u Hz, could be %lu Hz\n",
host->f_max, rate / 2 / 1);
}
if (IS_ENABLED(CONFIG_MCI_INFO)) {
mxs_mci->f_min = host->f_min;
mxs_mci->f_max = host->f_max;
hw_dev->info = mxs_mci_info;
}
return mci_register(host);
}
static int mxs_ocotp_probe(struct device_d *dev)
{
int err;
struct ocotp_priv *priv = xzalloc(sizeof (*priv));
priv->base = dev_request_mem_region(dev, 0);
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
priv->clk = clk_get(dev, NULL);
if (IS_ERR(priv->clk))
return PTR_ERR(priv->clk);
priv->cdev.dev = dev;
priv->cdev.ops = &mxs_ocotp_ops;
priv->cdev.priv = priv;
priv->cdev.size = cpu_is_mx23() ? 128 : 160;
priv->cdev.name = DRIVERNAME;
err = devfs_create(&priv->cdev);
if (err < 0)
return err;
if (IS_ENABLED(CONFIG_MXS_OCOTP_WRITABLE)) {
mxs_ocotp_ops.write = mxs_ocotp_cdev_write;
dev_add_param_bool(dev, "permanent_write_enable",
NULL, NULL, &priv->write_enable, NULL);
}
return 0;
}
static int i2c_versatile_probe(struct device_d *dev)
{
struct i2c_versatile *i2c;
int ret;
i2c = kzalloc(sizeof(struct i2c_versatile), GFP_KERNEL);
if (!i2c) {
ret = -ENOMEM;
goto err_release;
}
i2c->base = dev_request_mem_region(dev, 0);
if (!i2c->base) {
ret = -ENOMEM;
goto err_free;
}
writel(SCL | SDA, i2c->base + I2C_CONTROLS);
i2c->adap.algo_data = &i2c->algo;
i2c->adap.dev.parent = dev;
i2c->algo = i2c_versatile_algo;
i2c->algo.data = i2c;
i2c->adap.nr = dev->id;
ret = i2c_bit_add_numbered_bus(&i2c->adap);
if (ret >= 0) {
return 0;
}
err_free:
kfree(i2c);
err_release:
return ret;
}
static int imx_chipidea_probe(struct device_d *dev)
{
struct imxusb_platformdata *pdata = dev->platform_data;
int ret;
void __iomem *base;
struct imx_chipidea *ci;
uint32_t portsc;
ci = xzalloc(sizeof(*ci));
ci->dev = dev;
if (IS_ENABLED(CONFIG_OFDEVICE) && dev->device_node) {
ret = imx_chipidea_probe_dt(ci);
if (ret)
return ret;
} else {
if (!pdata) {
dev_err(dev, "no pdata!\n");
return -EINVAL;
}
ci->portno = dev->id;
ci->flags = pdata->flags;
ci->mode = pdata->mode;
}
base = dev_request_mem_region(dev, 0);
if (!base)
return -ENODEV;
ci->base = base;
ci->data.init = imx_chipidea_port_init;
ci->data.post_init = imx_chipidea_port_post_init;
ci->data.drvdata = ci;
if ((ci->flags & MXC_EHCI_PORTSC_MASK) == MXC_EHCI_MODE_HSIC)
imx_chipidea_port_init(ci);
if (ci->phymode != USBPHY_INTERFACE_MODE_UNKNOWN) {
portsc = readl(base + 0x184);
portsc &= ~MXC_EHCI_PORTSC_MASK;
portsc |= ci->flags & MXC_EHCI_PORTSC_MASK;
writel(portsc, base + 0x184);
}
ci->data.hccr = base + 0x100;
ci->data.hcor = base + 0x140;
ci->data.flags = EHCI_HAS_TT;
if (ci->mode == IMX_USB_MODE_HOST && IS_ENABLED(CONFIG_USB_EHCI)) {
ret = ehci_register(dev, &ci->data);
} else if (ci->mode == IMX_USB_MODE_DEVICE && IS_ENABLED(CONFIG_USB_GADGET_DRIVER_ARC)) {
ret = ci_udc_register(dev, base);
} else {
dev_err(dev, "No supported role\n");
ret = -ENODEV;
}
return ret;
};
static int cs8900_probe(struct device_d *dev)
{
struct eth_device *edev;
struct cs8900_priv *priv;
debug("cs8900_init()\n");
priv = (struct cs8900_priv *)xmalloc(sizeof(*priv));
priv->regs = dev_request_mem_region(dev, 0);
if (cs8900_check_id(priv)) {
free(priv);
return -1;
}
edev = (struct eth_device *)xmalloc(sizeof(struct eth_device));
edev->priv = priv;
edev->init = cs8900_dev_init;
edev->open = cs8900_open;
edev->send = cs8900_send;
edev->recv = cs8900_recv;
edev->halt = cs8900_halt;
edev->get_ethaddr = cs8900_get_ethaddr;
edev->set_ethaddr = cs8900_set_ethaddr;
edev->parent = dev;
eth_register(edev);
return 0;
}
static int imx_iomux_probe(struct device_d *dev)
{
base = dev_request_mem_region(dev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
return 0;
}
static int imx_chipidea_probe(struct device_d *dev)
{
struct imxusb_platformdata *pdata = dev->platform_data;
int ret;
void __iomem *base;
struct ehci_data data = {};
uint32_t portsc;
if (!pdata) {
dev_err(dev, "no pdata!\n");
return -EINVAL;
}
base = dev_request_mem_region(dev, 0);
if (!base)
return -ENODEV;
data.init = imx_chipidea_port_init;
data.post_init = imx_chipidea_port_post_init;
data.drvdata = dev;
portsc = readl(base + 0x184);
portsc &= ~MXC_EHCI_PORTSC_MASK;
portsc |= pdata->flags & MXC_EHCI_PORTSC_MASK;
writel(portsc, base + 0x184);
imx_chipidea_port_init(dev);
if ((pdata->flags & MXC_EHCI_PORTSC_MASK) == MXC_EHCI_MODE_ULPI) {
dev_dbg(dev, "using ULPI phy\n");
if (IS_ENABLED(CONFIG_USB_ULPI)) {
ret = ulpi_setup(base + 0x170, 1);
} else {
dev_err(dev, "no ULPI support available\n");
ret = -ENODEV;
}
if (ret)
return ret;
}
data.hccr = base + 0x100;
data.hcor = base + 0x140;
data.flags = EHCI_HAS_TT;
if (pdata->mode == IMX_USB_MODE_HOST && IS_ENABLED(CONFIG_USB_EHCI)) {
ret = ehci_register(dev, &data);
} else if (pdata->mode == IMX_USB_MODE_DEVICE && IS_ENABLED(CONFIG_USB_GADGET_DRIVER_ARC)) {
ret = ci_udc_register(dev, base);
} else {
dev_err(dev, "No supported role\n");
ret = -ENODEV;
}
return ret;
};
static int imx_pata_probe(struct device_d *dev)
{
struct ide_port *ide;
struct clk *clk;
void __iomem *base;
int ret;
const char *devname = NULL;
ide = xzalloc(sizeof(*ide));
base = dev_request_mem_region(dev, 0);
clk = clk_get(dev, NULL);
if (IS_ERR(clk)) {
ret = PTR_ERR(clk);
goto out_free;
}
imx_pata_setup_port(base + PATA_IMX_DRIVE_DATA,
base + PATA_IMX_DRIVE_CONTROL, &ide->io, 2);
/* deassert resets */
writel(PATA_IMX_ATA_CTRL_FIFO_RST_B |
PATA_IMX_ATA_CTRL_ATA_RST_B,
base + PATA_IMX_ATA_CONTROL);
pata_imx_set_bus_timing(base, clk_get_rate(clk), 4);
if (IS_ENABLED(CONFIG_OFDEVICE)) {
devname = of_alias_get(dev->device_node);
if (devname)
devname = xstrdup(devname);
}
ide->port.dev = dev;
ide->port.devname = devname;
dev->priv = ide;
dev->detect = pata_imx_detect;
ret = ide_port_register(ide);
if (ret) {
dev_err(dev, "Cannot register IDE interface: %s\n",
strerror(-ret));
goto out_free_clk;
}
return 0;
out_free_clk:
clk_put(clk);
out_free:
free(ide);
return ret;
}
static int ar231x_reset_probe(struct device_d *dev)
{
reset_base = dev_request_mem_region(dev, 0);
if (IS_ERR(reset_base)) {
dev_err(dev, "could not get memory region\n");
return PTR_ERR(reset_base);
}
return 0;
}
static int tegra20_pmc_probe(struct device_d *dev)
{
pmc_base = dev_request_mem_region(dev, 0);
if (!pmc_base) {
dev_err(dev, "could not get memory region\n");
return -ENODEV;
}
return 0;
}
static int imx53_ccm_probe(struct device_d *dev)
{
void __iomem *regs;
regs = dev_request_mem_region(dev, 0);
mx53_clocks_init(regs, 32768, 24000000, 22579200, 0); /* FIXME */
return 0;
}
static int imx28_ccm_probe(struct device_d *dev)
{
void __iomem *regs;
regs = dev_request_mem_region(dev, 0);
mx28_clocks_init(regs);
return 0;
}
static int __init i2c_fsl_probe(struct device_d *pdev)
{
struct fsl_i2c_struct *i2c_fsl;
struct i2c_platform_data *pdata;
int ret;
pdata = pdev->platform_data;
i2c_fsl = xzalloc(sizeof(*i2c_fsl));
#ifdef CONFIG_COMMON_CLK
i2c_fsl->clk = clk_get(pdev, NULL);
if (IS_ERR(i2c_fsl->clk)) {
ret = PTR_ERR(i2c_fsl->clk);
goto fail;
}
#endif
/* Setup i2c_fsl driver structure */
i2c_fsl->adapter.master_xfer = i2c_fsl_xfer;
i2c_fsl->adapter.nr = pdev->id;
i2c_fsl->adapter.dev.parent = pdev;
i2c_fsl->adapter.dev.device_node = pdev->device_node;
i2c_fsl->base = dev_request_mem_region(pdev, 0);
if (IS_ERR(i2c_fsl->base)) {
ret = PTR_ERR(i2c_fsl->base);
goto fail;
}
i2c_fsl_init_recovery(i2c_fsl, pdev);
i2c_fsl->dfsrr = -1;
/* Set up clock divider */
if (pdata && pdata->bitrate)
i2c_fsl_set_clk(i2c_fsl, pdata->bitrate);
else
i2c_fsl_set_clk(i2c_fsl, FSL_I2C_BIT_RATE);
/* Set up chip registers to defaults */
writeb(0, i2c_fsl->base + FSL_I2C_I2CR);
writeb(0, i2c_fsl->base + FSL_I2C_I2SR);
/* Add I2C adapter */
ret = i2c_add_numbered_adapter(&i2c_fsl->adapter);
if (ret < 0) {
dev_err(pdev, "registration failed\n");
goto fail;
}
return 0;
fail:
kfree(i2c_fsl);
return ret;
}
int mvebu_coreclk_probe(struct device_d *dev)
{
struct device_node *np = dev->device_node;
const struct of_device_id *match;
const struct coreclk_soc_desc *desc;
const char *tclk_name = "tclk";
const char *cpuclk_name = "cpuclk";
void __iomem *base;
unsigned long rate;
int n;
match = of_match_node(mvebu_coreclk_ids, np);
if (!match)
return -EINVAL;
desc = (const struct coreclk_soc_desc *)match->data;
/* Get SAR base address */
base = dev_request_mem_region(dev, 0);
if (!base)
return -EINVAL;
/* Allocate struct for TCLK, cpu clk, and core ratio clocks */
clk_data.clk_num = 2 + desc->num_ratios;
clk_data.clks = xzalloc(clk_data.clk_num * sizeof(struct clk *));
/* Register TCLK */
of_property_read_string_index(np, "clock-output-names", 0,
&tclk_name);
rate = desc->get_tclk_freq(base);
clk_data.clks[0] = clk_fixed(tclk_name, rate);
WARN_ON(IS_ERR(clk_data.clks[0]));
/* Register CPU clock */
of_property_read_string_index(np, "clock-output-names", 1,
&cpuclk_name);
rate = desc->get_cpu_freq(base);
clk_data.clks[1] = clk_fixed(cpuclk_name, rate);
WARN_ON(IS_ERR(clk_data.clks[1]));
/* Register fixed-factor clocks derived from CPU clock */
for (n = 0; n < desc->num_ratios; n++) {
const char *rclk_name = desc->ratios[n].name;
int mult, div;
of_property_read_string_index(np, "clock-output-names",
2+n, &rclk_name);
desc->get_clk_ratio(base, desc->ratios[n].id, &mult, &div);
clk_data.clks[2+n] = clk_fixed_factor(rclk_name, cpuclk_name,
mult, div, 0);
WARN_ON(IS_ERR(clk_data.clks[2+n]));
};
return of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
}
static int pxafb_probe(struct device_d *dev)
{
struct pxafb_platform_data *pdata = dev->platform_data;
struct pxafb_info *fbi;
struct fb_info *info;
int ret;
if (!pdata)
return -ENODEV;
fbi = xzalloc(sizeof(*fbi));
info = &fbi->info;
fbi->mode = pdata->mode;
fbi->regs = dev_request_mem_region(dev, 0);
if (IS_ERR(fbi->regs))
return PTR_ERR(fbi->regs);
fbi->dev = dev;
fbi->lcd_power = pdata->lcd_power;
fbi->backlight_power = pdata->backlight_power;
info->mode = &pdata->mode->mode;
info->fbops = &pxafb_ops;
info->xres = pdata->mode->mode.xres;
info->yres = pdata->mode->mode.yres;
info->bits_per_pixel = pdata->mode->bpp;
pxafb_decode_mach_info(fbi, pdata);
dev_info(dev, "PXA Framebuffer driver\n");
if (pdata->framebuffer)
fbi->info.screen_base = pdata->framebuffer;
else
fbi->info.screen_base =
PTR_ALIGN(dma_alloc_coherent(info->xres * info->yres *
(info->bits_per_pixel >> 3) + PAGE_SIZE),
PAGE_SIZE);
fbi->dma_buff = PTR_ALIGN(dma_alloc_coherent(sizeof(struct pxafb_dma_buff) + 16),
16);
pxafb_activate_var(fbi);
ret = register_framebuffer(&fbi->info);
if (ret < 0) {
dev_err(dev, "failed to register framebuffer\n");
return ret;
}
return 0;
}
static int pcs_probe(struct device_d *dev)
{
struct pinctrl_single *pcs;
struct device_node *np = dev->device_node;
int ret = 0;
pcs = xzalloc(sizeof(*pcs));
pcs->base = dev_request_mem_region(dev, 0);
pcs->pinctrl.dev = dev;
pcs->pinctrl.ops = &pcs_ops;
ret = of_property_read_u32(np, "pinctrl-single,register-width",
&pcs->width);
if (ret) {
dev_dbg(dev, "no pinctrl-single,register-width property\n");
goto out;
}
switch (pcs->width) {
case 8:
pcs->read = pcs_readb;
pcs->write = pcs_writeb;
break;
case 16:
pcs->read = pcs_readw;
pcs->write = pcs_writew;
break;
case 32:
pcs->read = pcs_readl;
pcs->write = pcs_writel;
break;
default:
ret = -EINVAL;
dev_dbg(dev, "invalid register width: %d\n", pcs->width);
goto out;
}
ret = pinctrl_register(&pcs->pinctrl);
if (ret)
goto out;
return 0;
out:
free(pcs);
return ret;
}
int mvebu_clk_gating_probe(struct device_d *dev)
{
struct device_node *np = dev->device_node;
const struct of_device_id *match;
const struct clk_gating_soc_desc *desc;
struct clk_gating_ctrl *ctrl;
struct gate *gate;
struct clk *clk;
void __iomem *base;
const char *default_parent = NULL;
int n;
match = of_match_node(mvebu_clk_gating_ids, np);
if (!match)
return -EINVAL;
desc = (const struct clk_gating_soc_desc *)match->data;
base = dev_request_mem_region(dev, 0);
if (!base)
return -EINVAL;
clk = of_clk_get(np, 0);
if (IS_ERR(clk))
return -EINVAL;
default_parent = clk->name;
ctrl = xzalloc(sizeof(*ctrl));
/* Count, allocate, and register clock gates */
for (n = 0; desc[n].name;)
n++;
ctrl->num_gates = n;
ctrl->gates = xzalloc(ctrl->num_gates * sizeof(*gate));
for (n = 0, gate = ctrl->gates; n < ctrl->num_gates; n++, gate++) {
const char *parent =
(desc[n].parent) ? desc[n].parent : default_parent;
gate->bit_idx = desc[n].bit_idx;
gate->clk = clk_gate(desc[n].name, parent,
base, desc[n].bit_idx, 0, 0);
WARN_ON(IS_ERR(gate->clk));
}
return of_clk_add_provider(np, clk_gating_get_src, ctrl);
}
static int omap_gpio_probe(struct device_d *dev)
{
struct omap_gpio_chip *omapgpio;
omapgpio = xzalloc(sizeof(*omapgpio));
omapgpio->base = dev_request_mem_region(dev, 0);
omapgpio->chip.ops = &omap_gpio_ops;
omapgpio->chip.base = dev->id * 32;
omapgpio->chip.ngpio = 32;
omapgpio->chip.dev = dev;
gpiochip_add(&omapgpio->chip);
dev_dbg(dev, "probed gpiochip%d with base %d\n",
dev->id, omapgpio->chip.base);
return 0;
}
static int imx_usbmisc_probe(struct device_d *dev)
{
struct imx_usb_misc_data *devtype;
int ret;
ret = dev_get_drvdata(dev, (unsigned long *)&devtype);
if (ret)
return ret;
usbmisc_base = dev_request_mem_region(dev, 0);
if (!usbmisc_base)
return -ENOMEM;
imxusbmisc_data = devtype;
return 0;
}
static int uemd_timer_probe(struct device_d *dev)
{
int mode;
struct clk *timer_clk;
/* use only one timer */
if (timer_base)
return -EBUSY;
timer_base = dev_request_mem_region(dev, 0);
if (IS_ERR(timer_base)) {
dev_err(dev, "could not get memory region\n");
return PTR_ERR(timer_base);
}
timer_clk = clk_get(dev, NULL);
if (IS_ERR(timer_clk)) {
int ret = PTR_ERR(timer_clk);
dev_err(dev, "clock not found: %d\n", ret);
return ret;
}
/* Stop timer */
__raw_writel(0, timer_base + TIMER_CONTROL);
/* Setup */
__raw_writel(0xffffffff, timer_base + TIMER_LOAD);
__raw_writel(0xffffffff, timer_base + TIMER_VALUE);
mode = TIMER_CTRL_32BIT |
TIMER_CTRL_PERIODIC |
TIMER_CTRL_P1;
__raw_writel(mode, timer_base + TIMER_CONTROL);
/* Fire it up! */
mode |= TIMER_CTRL_ENABLE;
__raw_writel(mode, timer_base + TIMER_CONTROL);
clocks_calc_mult_shift(&uemd_cs.mult, &uemd_cs.shift,
clk_get_rate(timer_clk), NSEC_PER_SEC, 10);
init_clock(&uemd_cs);
return 0;
}
static int tegra20_timer_probe(struct device_d *dev)
{
u32 reg;
/* use only one timer */
if (timer_base)
return -EBUSY;
timer_base = dev_request_mem_region(dev, 0);
if (!timer_base) {
dev_err(dev, "could not get memory region\n");
return -ENODEV;
}
/*
* calibrate timer to run at 1MHz
* TIMERUS_USEC_CFG selects the scale down factor with bits [0:7]
* representing the divisor and bits [8:15] representing the dividend
* each in n+1 form.
*/
switch (tegra_get_osc_clock()) {
case 12000000:
reg = 0x000b;
break;
case 13000000:
reg = 0x000c;
break;
case 19200000:
reg = 0x045f;
break;
case 26000000:
reg = 0x0019;
break;
default:
reg = 0;
dev_warn(dev, "unknown timer clock rate\n");
break;
}
writel(reg, timer_base + TIMERUS_USEC_CFG);
cs.mult = clocksource_hz2mult(1000000, cs.shift);
init_clock(&cs);
return 0;
}
static int pl010_probe(struct device_d *dev)
{
struct console_device *cdev;
cdev = xzalloc(sizeof(struct console_device));
dev->priv = dev_request_mem_region(dev, 0);
cdev->dev = dev;
cdev->tstc = pl010_tstc;
cdev->putc = pl010_putc;
cdev->getc = pl010_getc;
cdev->setbrg = pl010_setbaudrate;
pl010_init_port(cdev);
console_register(cdev);
return 0;
}
static int imx31_ccm_probe(struct device_d *dev)
{
void __iomem *base;
base = dev_request_mem_region(dev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
writel(0xffffffff, base + CCM_CGR0);
writel(0xffffffff, base + CCM_CGR1);
writel(0xffffffff, base + CCM_CGR2);
clks[ckih] = clk_fixed("ckih", 26000000);
clks[ckil] = clk_fixed("ckil", 32768);
clks[mpll] = imx_clk_pllv1("mpll", "ckih", base + CCM_MPCTL);
clks[spll] = imx_clk_pllv1("spll", "ckih", base + CCM_SRPCTL);
clks[upll] = imx_clk_pllv1("upll", "ckih", base + CCM_UPCTL);
clks[mcu_main] = imx_clk_mux("mcu_main", base + CCM_PMCR0, 31, 1,
mcu_main_sel, ARRAY_SIZE(mcu_main_sel));
clks[hsp] = imx_clk_divider("hsp", "mcu_main", base + CCM_PDR0, 11, 3);
clks[ahb] = imx_clk_divider("ahb", "mcu_main", base + CCM_PDR0, 3, 3);
clks[nfc] = imx_clk_divider("nfc", "ahb", base + CCM_PDR0, 8, 3);
clks[ipg] = imx_clk_divider("ipg", "ahb", base + CCM_PDR0, 6, 2);
clks[per_div] = imx_clk_divider("per_div", "upll", base + CCM_PDR0, 16, 5);
clks[per] = imx_clk_mux("per", base + CCM_CCMR, 24, 1, per_sel, ARRAY_SIZE(per_sel));
clkdev_add_physbase(clks[per], MX31_UART1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per], MX31_UART2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per], MX31_UART3_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per], MX31_UART4_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per], MX31_UART5_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per], MX31_I2C1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per], MX31_I2C2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per], MX31_I2C3_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX31_CSPI1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX31_CSPI2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX31_CSPI3_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per], MX31_SDHC1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per], MX31_SDHC2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per], MX31_GPT1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[hsp], MX31_IPU_CTRL_BASE_ADDR, NULL);
return 0;
}
static int at91sam9_smc_probe(struct device_d *dev)
{
int id = dev->id;
if (id < 0) {
id = 0;
} else if (id > 1) {
dev_warn(dev, "id > 1\n");
return -EIO;
}
smc_base_addr[id] = dev_request_mem_region(dev, 0);
if (!smc_base_addr[id]) {
dev_err(dev, "Impossible to request smc.%d\n", id);
return -ENOMEM;
}
return 0;
}
static int netx_serial_probe(struct device_d *dev)
{
struct console_device *cdev;
cdev = xzalloc(sizeof(struct console_device));
dev->priv = dev_request_mem_region(dev, 0);
cdev->dev = dev;
cdev->f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR;
cdev->tstc = netx_serial_tstc;
cdev->putc = netx_serial_putc;
cdev->getc = netx_serial_getc;
cdev->setbrg = netx_serial_setbaudrate;
netx_serial_init_port(cdev);
console_register(cdev);
return 0;
}
static int altera_serial_jtag_probe(struct device_d *dev) {
struct console_device *cdev;
struct altera_serial_jtag_priv *priv;
priv = xzalloc(sizeof(*priv));
cdev = &priv->cdev;
priv->regs = dev_request_mem_region(dev, 0);
cdev->dev = dev;
cdev->tstc = altera_serial_jtag_tstc;
cdev->putc = altera_serial_jtag_putc;
cdev->getc = altera_serial_jtag_getc;
cdev->setbrg = altera_serial_jtag_setbaudrate;
console_register(cdev);
return 0;
}
static int orion_timer_probe(struct device_d *dev)
{
struct clk *tclk;
uint32_t val;
timer_base = dev_request_mem_region(dev, 0);
tclk = clk_get(dev, "tclk");
/* setup TIMER0 as free-running clock source */
__raw_writel(~0, timer_base + TIMER0_VAL);
__raw_writel(~0, timer_base + TIMER0_RELOAD);
val = __raw_readl(timer_base + TIMER_CTRL);
__raw_writel(val | TIMER0_EN | TIMER0_RELOAD_EN,
timer_base + TIMER_CTRL);
clksrc.mult = clocksource_hz2mult(clk_get_rate(tclk), clksrc.shift);
init_clock(&clksrc);
return 0;
}
