Beispiel #1
0
static DISP_STATUS dsi_init(UINT32 fbVA, UINT32 fbPA, BOOL isLcmInited)
{
	if (!disp_drv_dsi_init_context())
		return DISP_STATUS_NOT_IMPLEMENTED;

	if(lcm_params->dsi.mode == CMD_MODE)
	{
		init_dsi(isLcmInited);
		MASKREG32(DSI_BASE + 0x10, 0x2, 0x2);
		if (NULL != lcm_drv->init && !isLcmInited)
		{
			lcm_drv->init();
			DSI_LP_Reset();
		}

		DSI_clk_HS_mode(1);

		DSI_SetMode(lcm_params->dsi.mode);
	}
	else {
        if (!isLcmInited)
        {
	        	//DSI_SetMode(0);
	       	 	//mdelay(100);
	        	//DSI_Stop();
        }
        else
        {
            is_video_mode_running = true;
        }
		
	init_dsi(isLcmInited);

	MASKREG32(DSI_BASE + 0x10, 0x2, 0x2);
	if (NULL != lcm_drv->init && !isLcmInited)
	{
		lcm_drv->init();
		DSI_LP_Reset();
	}

	DSI_SetMode(lcm_params->dsi.mode);
	}

	RDMASetTargetLine(0, lcm_params->height*4/5);

    dsi_config_ddp(fbPA);
	DPI_PowerOn();
	DPI_PowerOff();
#ifdef SPM_SODI_ENABLED
    if(lcm_params->dsi.mode == CMD_MODE)
    {
        spm_sodi_lcm_video_mode(FALSE);
    }
    else
    {
        spm_sodi_lcm_video_mode(TRUE);
    }
#endif
	return DISP_STATUS_OK;
}
static UINT32 dsi_get_working_buffer_bpp(void)
{
    disp_drv_dsi_init_context();

    if(lcm_params->dsi.mode != CMD_MODE) {
        return dsiTmpBufBpp;
    }

    return 0;
}
// protected by sem_flipping, sem_early_suspend, sem_overlay_buffer, sem_update_screen
static DISP_STATUS dsi_update_screen(BOOL isMuextLocked)
{
    disp_drv_dsi_init_context();

    DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE));

    //DSI_CHECK_RET(DSI_handle_TE());
    
    DSI_SetMode(lcm_params->dsi.mode);
#ifndef MT65XX_NEW_DISP
    LCD_CHECK_RET(LCD_StartTransfer(FALSE, isMuextLocked));
#endif

    if (lcm_params->type==LCM_TYPE_DSI && lcm_params->dsi.mode == CMD_MODE && !DDMS_capturing) {
        //if(1 != lcm_params->dsi.compatibility_for_nvk)
        if(1)
        {
            DSI_clk_HS_mode(1);
        }

        #ifndef MT65XX_NEW_DISP
            DSI_CHECK_RET(DSI_Start());
        #else
            DSI_CHECK_RET(DSI_StartTransfer(isMuextLocked));
        #endif
    }
    else if (lcm_params->type==LCM_TYPE_DSI && lcm_params->dsi.mode != CMD_MODE && !DDMS_capturing)
    {
        DSI_clk_HS_mode(1);
        #ifndef MT65XX_NEW_DISP
            DPI_CHECK_RET(DPI_EnableClk());
            DSI_CHECK_RET(DSI_Start());
        #else
            DSI_CHECK_RET(DSI_StartTransfer(isMuextLocked));
        #endif
        #ifndef BUILD_UBOOT
            is_video_mode_running = true;
            
            if(lcm_params->dsi.noncont_clock)
                DSI_set_noncont_clk(true, lcm_params->dsi.noncont_clock_period);
            
            if(lcm_params->dsi.lcm_int_te_monitor)
                DSI_set_int_TE(true, lcm_params->dsi.lcm_int_te_period);
        
        #endif		
    }
    
    if (DDMS_capturing)
        DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "[DISP] kernel - dsi_update_screen. DDMS is capturing. Skip one frame. \n");		
    
    return DISP_STATUS_OK;
}
static UINT32 dsi_get_working_buffer_size(void)
{
    disp_drv_dsi_init_context();

    if(lcm_params->dsi.mode != CMD_MODE) {

        return
            DISP_GetScreenWidth() *
            DISP_GetScreenHeight() *
            dsiTmpBufBpp *
            lcm_params->dsi.intermediat_buffer_num;
    }

    return 0;
}
Beispiel #5
0
static UINT32 dsi_get_working_buffer_size(void)
{
    disp_drv_dsi_init_context();

	if(lcm_params->dsi.mode != CMD_MODE) {

            return
            lcm_params->width *
            lcm_params->height *
            dsiTmpBufBpp *
            lcm_params->dsi.intermediat_buffer_num;
	}

    return 0;
}
static PANEL_COLOR_FORMAT dsi_get_panel_color_format(void)
{
    disp_drv_dsi_init_context();

    {
    
        switch(lcm_params->dsi.data_format.format)
        {
            case LCM_DSI_FORMAT_RGB565 : return PANEL_COLOR_FORMAT_RGB565;
            case LCM_DSI_FORMAT_RGB666 : return PANEL_COLOR_FORMAT_RGB666;
            case LCM_DSI_FORMAT_RGB888 : return PANEL_COLOR_FORMAT_RGB888;
            default : ASSERT(0);
        }
    
    }
}
// protected by sem_flipping, sem_early_suspend, sem_overlay_buffer, sem_update_screen
static DISP_STATUS dsi_update_screen(void)
{
    disp_drv_dsi_init_context();

    DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE));

    //DSI_CHECK_RET(DSI_handle_TE());

    DSI_SetMode(lcm_params->dsi.mode);

    LCD_CHECK_RET(LCD_StartTransfer(FALSE));

    if (lcm_params->type==LCM_TYPE_DSI && lcm_params->dsi.mode == CMD_MODE && !DDMS_capturing) {
        DSI_clk_HS_mode(1);
        DSI_CHECK_RET(DSI_EnableClk());
    }
    else if (lcm_params->type==LCM_TYPE_DSI && lcm_params->dsi.mode != CMD_MODE && !DDMS_capturing)
    {
#ifndef BUILD_UBOOT
        spin_lock(&g_handle_esd_lock);
#endif
        DSI_clk_HS_mode(1);
        DPI_CHECK_RET(DPI_EnableClk());
        DSI_CHECK_RET(DSI_EnableClk());

#ifndef BUILD_UBOOT
        dsi_vdo_streaming = true;

        if(lcm_params->dsi.noncont_clock)
            DSI_set_noncont_clk(true, lcm_params->dsi.noncont_clock_period);

        if(lcm_params->dsi.lcm_int_te_monitor)
            DSI_set_int_TE(true, lcm_params->dsi.lcm_int_te_period);

        spin_unlock(&g_handle_esd_lock);
#endif
    }

    if (DDMS_capturing)
        DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "[DISP] kernel - dsi_update_screen. DDMS is capturing. Skip one frame. \n");

    return DISP_STATUS_OK;
}
// protected by sem_early_suspend, sem_update_screen
static DISP_STATUS dsi_enable_power(BOOL enable)
{
    disp_drv_dsi_init_context();

    if(lcm_params->dsi.mode == CMD_MODE) {

        if (enable) {
#if 0
            // Switch bus to MIPI TX.
            DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE));
            DSI_PHY_clk_switch(1);
            DSI_PHY_clk_setting(lcm_params->dsi.pll_div1, lcm_params->dsi.pll_div2, lcm_params->dsi.LANE_NUM);
            DSI_CHECK_RET(DSI_PowerOn());
            DSI_WaitForNotBusy();
            DSI_clk_HS_mode(0);
            DSI_clk_ULP_mode(0);
            DSI_lane0_ULP_mode(0);
            DSI_Reset();
            LCD_CHECK_RET(LCD_PowerOn());
#else

            DSI_PHY_clk_switch(1);
            DSI_CHECK_RET(DSI_PowerOn());
            if(Need_Wait_ULPS())
                Wait_ULPS_Mode();

            DSI_PHY_clk_setting(lcm_params->dsi.pll_div1, lcm_params->dsi.pll_div2, lcm_params->dsi.LANE_NUM);
            DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE));

            Wait_WakeUp();

            LCD_CHECK_RET(LCD_PowerOn());

#endif
        } else {
            LCD_CHECK_RET(LCD_PowerOff());
            DSI_clk_HS_mode(0);
            DSI_lane0_ULP_mode(1);
            DSI_clk_ULP_mode(1);
            DSI_CHECK_RET(DSI_PowerOff());
            DSI_PHY_clk_switch(0);
            // Switch bus to GPIO, then power level will be decided by GPIO setting.
            DSI_CHECK_RET(DSI_enable_MIPI_txio(FALSE));
        }
    } else {
#if 0
#ifndef BUILD_UBOOT
        spin_lock(&g_handle_esd_lock);
#endif
#endif
        if (enable) {
#if 0
            // Switch bus to MIPI TX.
            DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE));
            DSI_PHY_clk_switch(1);
            DSI_PHY_clk_setting(lcm_params->dsi.pll_div1, lcm_params->dsi.pll_div2, lcm_params->dsi.LANE_NUM);
            DSI_CHECK_RET(DSI_PowerOn());
            DSI_clk_ULP_mode(0);
            DSI_lane0_ULP_mode(0);
            DSI_clk_HS_mode(0);
            DSI_Reset();
            DPI_CHECK_RET(DPI_PowerOn());
            LCD_CHECK_RET(LCD_PowerOn());
#else
            DSI_PHY_clk_switch(1);
            DSI_CHECK_RET(DSI_PowerOn());
            if(Need_Wait_ULPS())
                Wait_ULPS_Mode();

            DSI_PHY_clk_setting(lcm_params->dsi.pll_div1, lcm_params->dsi.pll_div2, lcm_params->dsi.LANE_NUM);
            DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE));

            Wait_WakeUp();

            DPI_CHECK_RET(DPI_PowerOn());
            LCD_CHECK_RET(LCD_PowerOn());
#endif
        } else {

#ifndef BUILD_UBOOT
            dsi_vdo_streaming = false;

            if(lcm_params->dsi.noncont_clock)
                DSI_set_noncont_clk(false, lcm_params->dsi.noncont_clock_period);

            if(lcm_params->dsi.lcm_int_te_monitor)
                DSI_set_int_TE(false, lcm_params->dsi.lcm_int_te_period);
#endif
            LCD_CHECK_RET(LCD_PowerOff());
            DPI_CHECK_RET(DPI_PowerOff());

            DSI_lane0_ULP_mode(1);
            DSI_clk_ULP_mode(1);
            DSI_CHECK_RET(DSI_PowerOff());

            DSI_PHY_clk_switch(0);
            // Switch bus to GPIO, then power level will be decided by GPIO setting.
            DSI_CHECK_RET(DSI_enable_MIPI_txio(FALSE));
        }
#if 0
#ifndef BUILD_UBOOT
        spin_unlock(&g_handle_esd_lock);
#endif
#endif
    }

    return DISP_STATUS_OK;
}
static DISP_STATUS dsi_init(UINT32 fbVA, UINT32 fbPA, BOOL isLcmInited)
{
    if (!disp_drv_dsi_init_context())
        return DISP_STATUS_NOT_IMPLEMENTED;

    if(lcm_params->dsi.mode == CMD_MODE) {

        init_lcd();
        init_dsi(isLcmInited);

        if (NULL != lcm_drv->init && !isLcmInited)
        {
            lcm_drv->init();
        }

        DSI_clk_HS_mode(0);

        DSI_SetMode(lcm_params->dsi.mode);

        DPI_PowerOn();
        DPI_PowerOff();

        init_lcd_te_control();
    }
    else {

#ifndef BUILD_UBOOT
        spin_lock(&g_handle_esd_lock);
#endif

        init_intermediate_buffers(fbPA);

        init_lcd();
        init_dpi(isLcmInited);
        init_dsi(isLcmInited);

        if (NULL != lcm_drv->init && !isLcmInited) {
            lcm_drv->init();
        }

        DSI_SetMode(lcm_params->dsi.mode);

#ifndef BUILD_UBOOT
        if(lcm_params->dsi.lcm_ext_te_monitor)
        {
            dsi_vdo_streaming = false;
            LCD_TE_SetMode(LCD_TE_MODE_VSYNC_ONLY);
            LCD_TE_SetEdgePolarity(LCM_POLARITY_RISING);
            LCD_TE_Enable(FALSE);
        }

        if(lcm_params->dsi.noncont_clock)
            DSI_set_noncont_clk(false, lcm_params->dsi.noncont_clock_period);

        if(lcm_params->dsi.lcm_int_te_monitor)
            DSI_set_int_TE(false, lcm_params->dsi.lcm_int_te_period);

        spin_unlock(&g_handle_esd_lock);
#endif
    }

    return DISP_STATUS_OK;
}
// protected by sem_early_suspend, sem_update_screen
static DISP_STATUS dsi_enable_power(BOOL enable)
{
    disp_drv_dsi_init_context();
    
    if(lcm_params->dsi.mode == CMD_MODE) {
    
        if (enable) {
            #if 0
                // Switch bus to MIPI TX.
                DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE));
                DSI_PHY_clk_switch(TRUE, lcm_params);
                DSI_PHY_clk_setting(lcm_params->dsi.pll_div1, lcm_params->dsi.pll_div2, lcm_params->dsi.LANE_NUM);
                DSI_CHECK_RET(DSI_PowerOn());
                DSI_WaitForNotBusy();		
                DSI_clk_HS_mode(0);
                DSI_clk_ULP_mode(0);			
                DSI_lane0_ULP_mode(0);	
                DSI_Reset();
                LCD_CHECK_RET(LCD_PowerOn());

            #else
                #ifndef MT65XX_NEW_DISP
                    DSI_PHY_clk_switch(TRUE, lcm_params); 
                    DSI_CHECK_RET(DSI_PowerOn());
                    if(Need_Wait_ULPS())
                        Wait_ULPS_Mode();
                    
                    DSI_PHY_clk_setting(lcm_params->dsi.pll_div1, lcm_params->dsi.pll_div2, lcm_params->dsi.LANE_NUM);

                #else
                    // enable MMSYS CG
                    DSI_CHECK_RET(DSI_PowerOn());

                    // initialize clock setting
                    DSI_PHY_clk_setting(lcm_params);
					
					// initialize dsi timing
                    DSI_PHY_TIMCONFIG(lcm_params);

                    // restore dsi register
                    DSI_CHECK_RET(DSI_RestoreRegisters());

                    // enable sleep-out mode
                    DSI_CHECK_RET(DSI_SleepOut());

                    // enter HS mode
                    DSI_PHY_clk_switch(TRUE, lcm_params); 

                    // enter wakeup
                    DSI_CHECK_RET(DSI_Wakeup());

                    // enable clock
                    DSI_CHECK_RET(DSI_EnableClk());

                    // engine reset
                    DSI_Reset();
                #endif
                DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE));
                
                #ifndef MT65XX_NEW_DISP
                    Wait_WakeUp();
                #endif
            
            #endif
        }
        else {
            // backup dsi register
            DSI_CHECK_RET(DSI_WaitForEngineNotBusy());
            DSI_CHECK_RET(DSI_BackupRegisters());

            // enter ULPS mode
            DSI_clk_ULP_mode(1);
            DSI_lane0_ULP_mode(1);
            mdelay(1);
            
            // disable engine clock
            DSI_CHECK_RET(DSI_DisableClk());
            
            // disable CG
            DSI_CHECK_RET(DSI_PowerOff());

            // disable mipi pll
            DSI_PHY_clk_switch(FALSE, lcm_params);

            // Switch bus to GPIO, then power level will be decided by GPIO setting.
            DSI_CHECK_RET(DSI_enable_MIPI_txio(FALSE));
        }
    } 
    else {
        if (enable) {
            #if 0
                // Switch bus to MIPI TX.
                DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE));
                DSI_PHY_clk_switch(TRUE, lcm_params);
                DSI_PHY_clk_setting(lcm_params->dsi.pll_div1, lcm_params->dsi.pll_div2, lcm_params->dsi.LANE_NUM);
                DSI_CHECK_RET(DSI_PowerOn());			
                DSI_clk_ULP_mode(0);			
                DSI_lane0_ULP_mode(0);
                DSI_clk_HS_mode(0);	
                DSI_Reset();
                DPI_CHECK_RET(DPI_PowerOn());
                LCD_CHECK_RET(LCD_PowerOn());
            #else
                #ifndef MT65XX_NEW_DISP
                    DSI_PHY_clk_switch(TRUE, lcm_params); 
                    DSI_CHECK_RET(DSI_PowerOn());
                    if(Need_Wait_ULPS())
                        Wait_ULPS_Mode();
                    
                    DSI_PHY_clk_setting(lcm_params->dsi.pll_div1, lcm_params->dsi.pll_div2, lcm_params->dsi.LANE_NUM);
                #else
                    needStartDSI = true;

                    // enable MMSYS CG
                    DSI_CHECK_RET(DSI_PowerOn());

                    // initialize clock setting
                    DSI_PHY_clk_setting(lcm_params);
					
					// initialize dsi timing
                    DSI_PHY_TIMCONFIG(lcm_params);

                    // restore dsi register
                    DSI_CHECK_RET(DSI_RestoreRegisters());

                    // enable sleep-out mode
                    DSI_CHECK_RET(DSI_SleepOut());
                    
                    // enter HS mode
                    DSI_PHY_clk_switch(TRUE, lcm_params); 

                    // enter wakeup
                    DSI_CHECK_RET(DSI_Wakeup());

                    // enable clock
                    DSI_CHECK_RET(DSI_EnableClk());

                    // engine reset
                    DSI_Reset();

                #endif
                DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE));
                
                #ifndef MT65XX_NEW_DISP
                    Wait_WakeUp();
                #endif
            #endif
        }
        else {
            #ifndef BUILD_UBOOT
                is_video_mode_running = false;
                
                if(lcm_params->dsi.noncont_clock)
                    DSI_set_noncont_clk(false, lcm_params->dsi.noncont_clock_period);
                
                if(lcm_params->dsi.lcm_int_te_monitor)
                    DSI_set_int_TE(false, lcm_params->dsi.lcm_int_te_period);
            #endif

            // backup dsi register
            DSI_CHECK_RET(DSI_WaitForEngineNotBusy());
            DSI_CHECK_RET(DSI_BackupRegisters());

            // enter ULPS mode
            DSI_clk_ULP_mode(1);
            DSI_lane0_ULP_mode(1);
            mdelay(1);

            // disable engine clock
            DSI_CHECK_RET(DSI_DisableClk());

            // disable CG
            DSI_CHECK_RET(DSI_PowerOff());

            // disable mipi pll
            DSI_PHY_clk_switch(FALSE, lcm_params);

            // Switch bus to GPIO, then power level will be decided by GPIO setting.
            DSI_CHECK_RET(DSI_enable_MIPI_txio(FALSE));
        }
    }
    
    return DISP_STATUS_OK;
}
static DISP_STATUS dsi_init(UINT32 fbVA, UINT32 fbPA, BOOL isLcmInited)
{
    // DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "%s, line:%d\n", __func__, __LINE__);
    if (!disp_drv_dsi_init_context()) 
        return DISP_STATUS_NOT_IMPLEMENTED;

    // DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "%s, line:%d\n", __func__, __LINE__);
    if(lcm_params->dsi.mode == CMD_MODE) {
        #ifndef MT65XX_NEW_DISP
            init_lcd();
        #endif

        init_dsi(isLcmInited);
        mdelay(1);
        
        // DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "%s, line:%d\n", __func__, __LINE__);
        if (NULL != lcm_drv->init && !isLcmInited) 
        {
            lcm_drv->init();
            DSI_LP_Reset();
        }
        // DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "%s, line:%d\n", __func__, __LINE__);
        #ifndef MT65XX_NEW_DISP
            DSI_clk_HS_mode(0);
        #else
            DSI_clk_HS_mode(1);
        #endif

        // DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "%s, line:%d\n", __func__, __LINE__);
        DSI_SetMode(lcm_params->dsi.mode);
        #ifndef MT65XX_NEW_DISP
            init_lcd_te_control();
        #endif
    }
    else {
        #ifndef MT65XX_NEW_DISP
            init_intermediate_buffers(fbPA);
            
            init_lcd();
            init_dpi(isLcmInited);
        #endif

        if (!isLcmInited)
        {
            DSI_SetMode(0);
            mdelay(100);
            DSI_Stop();
        }
        else
        {
            is_video_mode_running = true;
        }
        init_dsi(isLcmInited);
        mdelay(1);
        
        if (NULL != lcm_drv->init && !isLcmInited) {
            lcm_drv->init();
            DSI_LP_Reset();
        }
        
        DSI_SetMode(lcm_params->dsi.mode);
        
        #ifndef BUILD_UBOOT	
            if(lcm_params->dsi.lcm_ext_te_monitor)
            {
                is_video_mode_running = false;
                LCD_TE_SetMode(LCD_TE_MODE_VSYNC_ONLY);
                LCD_TE_SetEdgePolarity(LCM_POLARITY_RISING);
                LCD_TE_Enable(FALSE);
            }
            
            if(lcm_params->dsi.noncont_clock)
                DSI_set_noncont_clk(false, lcm_params->dsi.noncont_clock_period);
            
            if(lcm_params->dsi.lcm_int_te_monitor)
                DSI_set_int_TE(false, lcm_params->dsi.lcm_int_te_period);			
        #endif			
    }

#ifdef MT65XX_NEW_DISP
    {
        struct disp_path_config_struct config = {0};
        config.srcModule = DISP_MODULE_OVL;
        config.bgROI.x = 0;
        config.bgROI.y = 0;
        config.bgROI.width = DISP_GetScreenWidth();
        config.bgROI.height = DISP_GetScreenHeight();
        config.bgColor = 0x0;	// background color

        config.pitch = ALIGN_TO(DISP_GetScreenWidth(),32)*2;
        config.srcROI.x = 0;config.srcROI.y = 0;
        config.srcROI.height= DISP_GetScreenHeight();
        config.srcROI.width= DISP_GetScreenWidth();
        config.ovl_config.source = OVL_LAYER_SOURCE_MEM; 

        config.ovl_config.layer = FB_LAYER;
        config.ovl_config.layer_en = 1; 
        config.ovl_config.fmt = OVL_INPUT_FORMAT_RGB565;
        config.ovl_config.addr = fbPA;	
        config.ovl_config.vaddr = fbVA;	
        config.ovl_config.source = OVL_LAYER_SOURCE_MEM; 
        config.ovl_config.src_x = 0;
        config.ovl_config.src_y = 0;
        config.ovl_config.src_w = DISP_GetScreenWidth();
        config.ovl_config.src_h = DISP_GetScreenHeight();
        config.ovl_config.dst_x = 0;	   // ROI
        config.ovl_config.dst_y = 0;
        config.ovl_config.dst_w = DISP_GetScreenWidth();
        config.ovl_config.dst_h = DISP_GetScreenHeight();
        config.ovl_config.src_pitch = ALIGN_TO(DISP_GetScreenWidth(),32)*2; //pixel number
        config.ovl_config.keyEn = 0;
        config.ovl_config.key = 0xFF;	   // color key
        config.ovl_config.aen = 0;			  // alpha enable
        config.ovl_config.alpha = 0;	

        if(lcm_params->dsi.mode == CMD_MODE)
            config.dstModule = DISP_MODULE_DSI_CMD;// DISP_MODULE_WDMA1
        else
            config.dstModule = DISP_MODULE_DSI_VDO;// DISP_MODULE_WDMA1

        config.outFormat = RDMA_OUTPUT_FORMAT_ARGB; 

        LCD_LayerSetAddress(FB_LAYER, fbPA);
        LCD_LayerSetFormat(FB_LAYER, LCD_LAYER_FORMAT_RGB565);
        LCD_LayerSetOffset(FB_LAYER, 0, 0);
        LCD_LayerSetSize(FB_LAYER,DISP_GetScreenWidth(),DISP_GetScreenHeight());
        LCD_LayerSetPitch(FB_LAYER, ALIGN_TO(DISP_GetScreenWidth(),32) * 2);
        LCD_LayerEnable(FB_LAYER, TRUE);                    

#if defined(MTK_M4U_EXT_PAGE_TABLE)
        if(lcm_params->dsi.mode != CMD_MODE)
        {
            DSI_Wait_VDO_Idle();
            disp_path_get_mutex();
        }

        disp_path_config(&config);
        
        #if 1
        // Config FB_Layer port to be physical.
        {
            M4U_PORT_STRUCT portStruct;
            
            portStruct.ePortID = M4U_PORT_LCD_OVL;		   //hardware port ID, defined in M4U_PORT_ID_ENUM
            portStruct.Virtuality = 1;
            portStruct.Security = 0;
            portStruct.domain = 3;			  //domain : 0 1 2 3
            portStruct.Distance = 1;
            portStruct.Direction = 0;
            m4u_config_port(&portStruct);
        }
        // hook m4u debug callback function
        m4u_set_tf_callback(M4U_CLNTMOD_DISP, &disp_m4u_dump_reg);
        #endif

        if(lcm_params->dsi.mode != CMD_MODE)
        {
            disp_path_release_mutex();
            DSI_Start();
        }
        
#else
        if(lcm_params->dsi.mode != CMD_MODE){

            #define TIMECNT  1000000
            unsigned int reg1 = 0, reg2 = 0, reg3 = 0;
            unsigned int timeout_cnt = 0;
            unsigned int irq_mask;

            // dump before modification
            printk("[DISP] pa:0x%x, va:0x%x \n", fbPA, fbVA);		
            
            // enable frame done interrupt
            disp_path_get_mutex();
            OVLEnableIrq(0x2);
            disp_path_release_mutex();
            
            while (timeout_cnt < TIMECNT)
            {
                reg1 = DISP_REG_GET(DISP_REG_OVL_INTSTA);
                reg2 = DISP_REG_GET(DISP_REG_OVL_STA);
                // frame done interrupt
                if (((reg1 & 0x2) == 0x2) && ((reg2 & 0x1) == 0x0))
                {
                    DISP_REG_SET(DISP_REG_OVL_INTSTA, ~reg1);     

                    local_irq_save(irq_mask);
                    disp_path_get_mutex();
                    disp_path_config(&config);
                    disp_path_release_mutex();

                    #if 1  // defined(MTK_M4U_SUPPORT)
                    {
                        M4U_PORT_STRUCT portStruct;
                        
                        portStruct.ePortID = M4U_PORT_LCD_OVL;		   //hardware port ID, defined in M4U_PORT_ID_ENUM
                        portStruct.Virtuality = 1;
                        portStruct.Security = 0;
                        portStruct.domain = 3;			  //domain : 0 1 2 3
                        portStruct.Distance = 1;
                        portStruct.Direction = 0;
                        m4u_config_port(&portStruct);
                    }
                    // hook m4u debug callback function
                    m4u_set_tf_callback(M4U_CLNTMOD_DISP, &disp_m4u_dump_reg);
                    #endif
                    local_irq_restore(irq_mask);

                    break;
                }
                timeout_cnt++;
            }
            // sw timeout
            if (timeout_cnt >= TIMECNT)
            {
                printk("[DISP] timeout:%d \n", timeout_cnt);		
                ASSERT(0);
            }
            // dump after modification
            printk("[DISP] cnt:%d \n", timeout_cnt);		
        }
        else
        {
            disp_path_config(&config);

            #if 1  // defined(MTK_M4U_SUPPORT)
            {
                M4U_PORT_STRUCT portStruct;
                
                portStruct.ePortID = M4U_PORT_LCD_OVL;		   //hardware port ID, defined in M4U_PORT_ID_ENUM
                portStruct.Virtuality = 1;
                portStruct.Security = 0;
                portStruct.domain = 3;			  //domain : 0 1 2 3
                portStruct.Distance = 1;
                portStruct.Direction = 0;
                m4u_config_port(&portStruct);
            }
            // hook m4u debug callback function
            m4u_set_tf_callback(M4U_CLNTMOD_DISP, &disp_m4u_dump_reg);
            #endif
        }
#endif

    }
#endif

    printk("%s, config done\n", __func__);

    return DISP_STATUS_OK;
}
Beispiel #12
0
// protected by sem_early_suspend, sem_update_screen
static DISP_STATUS dsi_enable_power(BOOL enable)
{
	disp_drv_dsi_init_context();
	
	if(lcm_params->dsi.mode == CMD_MODE) {

		if (enable) {
#if 0
			// Switch bus to MIPI TX.
			DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE));
			DSI_PHY_clk_switch(1);
			DSI_PHY_clk_setting(lcm_params->dsi.pll_div1, lcm_params->dsi.pll_div2, lcm_params->dsi.LANE_NUM);
			DSI_CHECK_RET(DSI_PowerOn());
			DSI_WaitForNotBusy();		
			DSI_clk_HS_mode(0);
			DSI_clk_ULP_mode(0);			
			DSI_lane0_ULP_mode(0);	
			DSI_Reset();
			LCD_CHECK_RET(LCD_PowerOn());
#else

			DSI_PHY_clk_switch(1); 
#ifndef MT65XX_NEW_DISP
			DSI_CHECK_RET(DSI_PowerOn());
			if(Need_Wait_ULPS())
				Wait_ULPS_Mode();
			
			DSI_PHY_clk_setting(lcm_params->dsi.pll_div1, lcm_params->dsi.pll_div2, lcm_params->dsi.LANE_NUM);
#else	
			if(lcm_params->dsi.pll_select == 1)
			{
					ASSERT(0 == enable_pll(LVDSPLL,"mtk_dsi"));
  		  }
			DSI_PHY_clk_setting(lcm_params);
			DSI_CHECK_RET(DSI_PowerOn());
			DSI_clk_ULP_mode(0);			
			DSI_lane0_ULP_mode(0);
//			DSI_clk_HS_mode(1);	
#endif
			DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE));

#ifndef MT65XX_NEW_DISP
			Wait_WakeUp();
			LCD_CHECK_RET(LCD_PowerOn());		
#endif

#endif
		} else {
#ifndef MT65XX_NEW_DISP
			LCD_CHECK_RET(LCD_PowerOff());
#endif
			DSI_clk_HS_mode(0);
			DSI_lane0_ULP_mode(1);
			DSI_clk_ULP_mode(1);
//			DSI_CHECK_RET(DSI_PowerOff());
			DSI_PHY_clk_switch(0);
			DSI_CHECK_RET(DSI_PowerOff());
			// Switch bus to GPIO, then power level will be decided by GPIO setting.
			DSI_CHECK_RET(DSI_enable_MIPI_txio(FALSE));
			if(lcm_params->dsi.pll_select == 1)
				ASSERT(0 == disable_pll(LVDSPLL,"mtk_dsi"));
		}
	} else {
	    if (enable) {
#if 0
			// Switch bus to MIPI TX.
			DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE));
			DSI_PHY_clk_switch(1);
			DSI_PHY_clk_setting(lcm_params->dsi.pll_div1, lcm_params->dsi.pll_div2, lcm_params->dsi.LANE_NUM);
			DSI_CHECK_RET(DSI_PowerOn());			
			DSI_clk_ULP_mode(0);			
			DSI_lane0_ULP_mode(0);
			DSI_clk_HS_mode(0);	
			DSI_Reset();
			DPI_CHECK_RET(DPI_PowerOn());
			LCD_CHECK_RET(LCD_PowerOn());
#else
			DSI_PHY_clk_switch(1); 
#ifndef MT65XX_NEW_DISP
			DSI_CHECK_RET(DSI_PowerOn());
			if(Need_Wait_ULPS())
				Wait_ULPS_Mode();
			
			DSI_PHY_clk_setting(lcm_params->dsi.pll_div1, lcm_params->dsi.pll_div2, lcm_params->dsi.LANE_NUM);
#else
			needStartDSI = true;
			if(lcm_params->dsi.pll_select == 1)
			{
					ASSERT(0 == enable_pll(LVDSPLL,"mtk_dsi"));
			}
			DSI_PHY_clk_setting(lcm_params);
			DSI_CHECK_RET(DSI_PowerOn());
			DSI_clk_ULP_mode(0);			
			DSI_lane0_ULP_mode(0);
			DSI_clk_HS_mode(0);	
#endif
			DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE));

#ifndef MT65XX_NEW_DISP
			Wait_WakeUp();
			DPI_CHECK_RET(DPI_PowerOn());
			LCD_CHECK_RET(LCD_PowerOn());		
#endif
#endif
	    } else {
#ifndef BUILD_UBOOT
			is_video_mode_running = false;
#ifndef MT65XX_NEW_DISP
			if(lcm_params->dsi.noncont_clock)
				DSI_set_noncont_clk(false, lcm_params->dsi.noncont_clock_period);
			
			if(lcm_params->dsi.lcm_int_te_monitor)
				DSI_set_int_TE(false, lcm_params->dsi.lcm_int_te_period);
#endif
#endif
#ifndef MT65XX_NEW_DISP
			LCD_CHECK_RET(LCD_PowerOff());		
			DPI_CHECK_RET(DPI_PowerOff());
#endif
#if 1
			DSI_lane0_ULP_mode(1);
			DSI_clk_ULP_mode(1);	
			DSI_CHECK_RET(DSI_PowerOff());
#endif			
			DSI_PHY_clk_switch(0);
			// Switch bus to GPIO, then power level will be decided by GPIO setting.
			DSI_CHECK_RET(DSI_enable_MIPI_txio(FALSE));
			if(lcm_params->dsi.pll_select == 1)
				ASSERT(0 == disable_pll(LVDSPLL,"mtk_dsi"));
	    }
	}

    return DISP_STATUS_OK;
}
Beispiel #13
0
static DISP_STATUS dsi_init(UINT32 fbVA, UINT32 fbPA, BOOL isLcmInited)
{
	if (!disp_drv_dsi_init_context()) 
		return DISP_STATUS_NOT_IMPLEMENTED;

	if(lcm_params->dsi.mode == CMD_MODE) {
#ifndef MT65XX_NEW_DISP
		init_lcd();
#endif
		init_dsi(isLcmInited);

		if (NULL != lcm_drv->init && !isLcmInited) 
		{
			lcm_drv->init();
			DSI_LP_Reset();
		}
#ifndef MT65XX_NEW_DISP
		DSI_clk_HS_mode(0);
#else
		DSI_clk_HS_mode(1);
#endif
		DSI_SetMode(lcm_params->dsi.mode);
#ifndef MT65XX_NEW_DISP
		DPI_PowerOn();
		DPI_PowerOff();

		init_lcd_te_control();
#endif
	}
	else {
#ifndef MT65XX_NEW_DISP
		init_intermediate_buffers(fbPA);

	    init_lcd();
		init_dpi(isLcmInited);
#endif
        if (!isLcmInited)
        {
        DSI_SetMode(0);
        mdelay(100);
        DSI_DisableClk();
        }
        else
        {
            is_video_mode_running = true;
        }
		init_dsi(isLcmInited);

		if (NULL != lcm_drv->init && !isLcmInited) {
			lcm_drv->init();
			DSI_LP_Reset();
		}

		DSI_SetMode(lcm_params->dsi.mode);

#ifndef BUILD_UBOOT	
#ifndef MT65XX_NEW_DISP
		if(lcm_params->dsi.lcm_ext_te_monitor)
		{
			is_video_mode_running = false;
			LCD_TE_SetMode(LCD_TE_MODE_VSYNC_ONLY);
			LCD_TE_SetEdgePolarity(LCM_POLARITY_RISING);
			LCD_TE_Enable(FALSE);
		}

		if(lcm_params->dsi.noncont_clock)
			DSI_set_noncont_clk(false, lcm_params->dsi.noncont_clock_period);

		if(lcm_params->dsi.lcm_int_te_monitor)
			DSI_set_int_TE(false, lcm_params->dsi.lcm_int_te_period);			
#endif
#endif			
	}
#ifdef MT65XX_NEW_DISP
		{
			struct disp_path_config_struct config = {0};
			config.srcModule = DISP_MODULE_OVL;
				config.bgROI.x = 0;
				config.bgROI.y = 0;
				config.bgROI.width = DISP_GetScreenWidth();
				config.bgROI.height = DISP_GetScreenHeight();
				config.bgColor = 0x0;	// background color
	
				config.pitch = DISP_GetScreenWidth()*2;
				config.srcROI.x = 0;config.srcROI.y = 0;
				config.srcROI.height= DISP_GetScreenHeight();config.srcROI.width= DISP_GetScreenWidth();
				config.ovl_config.source = OVL_LAYER_SOURCE_MEM; 
	
        if(lcm_params->dsi.mode != CMD_MODE)
        {
            config.ovl_config.layer = FB_LAYER;
            config.ovl_config.layer_en = 0;
            disp_path_get_mutex();
            disp_path_config_layer(&config.ovl_config);
            disp_path_release_mutex();
            disp_path_wait_reg_update();
        }
        // Config FB_Layer port to be physical.
        {
            M4U_PORT_STRUCT portStruct;
            portStruct.ePortID = M4U_PORT_OVL_CH3;		   //hardware port ID, defined in M4U_PORT_ID_ENUM
            portStruct.Virtuality = 1;
            portStruct.Security = 0;
            portStruct.domain = 3;			  //domain : 0 1 2 3
            portStruct.Distance = 1;
            portStruct.Direction = 0;
            m4u_config_port(&portStruct);
        }
        config.ovl_config.layer = FB_LAYER;
        config.ovl_config.layer_en = 1; 
        config.ovl_config.fmt = OVL_INPUT_FORMAT_RGB565;
        config.ovl_config.addr = fbPA;	
        config.ovl_config.source = OVL_LAYER_SOURCE_MEM; 
        config.ovl_config.src_x = 0;
        config.ovl_config.src_y = 0;
        config.ovl_config.dst_x = 0;	   // ROI
        config.ovl_config.dst_y = 0;
        config.ovl_config.dst_w = DISP_GetScreenWidth();
        config.ovl_config.dst_h = DISP_GetScreenHeight();
        config.ovl_config.src_pitch = ALIGN_TO(DISP_GetScreenWidth(),32)*2; //pixel number
        config.ovl_config.keyEn = 0;
        config.ovl_config.key = 0xFF;	   // color key
        config.ovl_config.aen = 0;			  // alpha enable
        config.ovl_config.alpha = 0;	

        LCD_LayerSetAddress(FB_LAYER, fbPA);
        LCD_LayerSetFormat(FB_LAYER, LCD_LAYER_FORMAT_RGB565);
        LCD_LayerSetOffset(FB_LAYER, 0, 0);
        LCD_LayerSetSize(FB_LAYER,DISP_GetScreenWidth(),DISP_GetScreenHeight());
        LCD_LayerSetPitch(FB_LAYER, ALIGN_TO(DISP_GetScreenWidth(),32) * 2);
        LCD_LayerEnable(FB_LAYER, TRUE);                    
        if(lcm_params->dsi.mode == CMD_MODE)
            config.dstModule = DISP_MODULE_DSI_CMD;// DISP_MODULE_WDMA1
        else
            config.dstModule = DISP_MODULE_DSI_VDO;// DISP_MODULE_WDMA1
        config.outFormat = RDMA_OUTPUT_FORMAT_ARGB; 
        if(lcm_params->dsi.mode != CMD_MODE)
            disp_path_get_mutex();

        disp_path_config(&config);

        if(lcm_params->dsi.mode != CMD_MODE)
            disp_path_release_mutex();

        // Disable LK UI layer (Layer2)
        if(lcm_params->dsi.mode != CMD_MODE)
        {
            config.ovl_config.layer = FB_LAYER-1;
            config.ovl_config.layer_en = 0;
            disp_path_get_mutex();
            disp_path_config_layer(&config.ovl_config);
            disp_path_release_mutex();
            disp_path_wait_reg_update();
        }

        // Config LK UI layer port to be physical.
        {
            M4U_PORT_STRUCT portStruct;
            portStruct.ePortID = M4U_PORT_OVL_CH2;		   //hardware port ID, defined in M4U_PORT_ID_ENUM
            portStruct.Virtuality = 1;
            portStruct.Security = 0;
            portStruct.domain = 3;			  //domain : 0 1 2 3
            portStruct.Distance = 1;
            portStruct.Direction = 0;
            m4u_config_port(&portStruct);
        }
		}
#endif

	return DISP_STATUS_OK;
}
Beispiel #14
0
// protected by sem_early_suspend, sem_update_screen
static DISP_STATUS dsi_enable_power(BOOL enable)
{
	disp_drv_dsi_init_context();

	if(lcm_params->dsi.mode == CMD_MODE)
	{
		if (enable)
		{
			// enable MMSYS CG
			DSI_CHECK_RET(DSI_PowerOn());

			// initialize clock setting
			DSI_PHY_clk_setting(lcm_params);

			// restore dsi register
			DSI_CHECK_RET(DSI_RestoreRegisters());

			// enable sleep-out mode
			DSI_CHECK_RET(DSI_SleepOut());

			// enter HS mode
			DSI_PHY_clk_switch(1);

			// enter wakeup
			DSI_CHECK_RET(DSI_Wakeup());

			// enable clock
			DSI_CHECK_RET(DSI_EnableClk());

			DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE));
			DSI_Reset();
		}
		else
		{
			// backup dsi register
			DSI_CHECK_RET(DSI_WaitForNotBusy());
			DSI_CHECK_RET(DSI_BackupRegisters());

			// enter ULPS mode
			DSI_clk_ULP_mode(1);
			DSI_lane0_ULP_mode(1);
			DSI_clk_HS_mode(0);
			// disable clock
			DSI_CHECK_RET(DSI_DisableClk());
			DSI_CHECK_RET(DSI_PowerOff());

			// disable mipi pll
			DSI_PHY_clk_switch(0);

			// Switch bus to GPIO, then power level will be decided by GPIO setting.
			DSI_CHECK_RET(DSI_enable_MIPI_txio(FALSE));
		}
	}
	else
	{
		if (enable)
		{
			// enable MMSYS CG
			DSI_CHECK_RET(DSI_PowerOn());

			// initialize clock setting
			DSI_PHY_clk_setting(lcm_params);

			// restore dsi register
			DSI_CHECK_RET(DSI_RestoreRegisters());

			// enable sleep-out mode
			DSI_CHECK_RET(DSI_SleepOut());

			// enter HS mode
			DSI_PHY_clk_switch(1);

			// enter wakeup
			DSI_CHECK_RET(DSI_Wakeup());
			DSI_clk_HS_mode(0);
			// enable clock
			DSI_CHECK_RET(DSI_EnableClk());

			DSI_CHECK_RET(DSI_enable_MIPI_txio(TRUE));
			DSI_Reset();
			needStartDSI = true;
		}
		else
		{
			is_video_mode_running = false;

			// backup dsi register
			DSI_CHECK_RET(DSI_WaitForNotBusy());
			DSI_CHECK_RET(DSI_BackupRegisters());

			// enter ULPS mode
			DSI_clk_ULP_mode(1);
			DSI_lane0_ULP_mode(1);

			// disable clock
			DSI_CHECK_RET(DSI_DisableClk());
			DSI_CHECK_RET(DSI_PowerOff());

			// disable mipi pll
			DSI_PHY_clk_switch(0);

			// Switch bus to GPIO, then power level will be decided by GPIO setting.
			DSI_CHECK_RET(DSI_enable_MIPI_txio(FALSE));
	    	}
	}

	return DISP_STATUS_OK;
}
static DISP_STATUS dsi_init(UINT32 fbVA, UINT32 fbPA, BOOL isLcmInited)
{
    // DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "%s, line:%d\n", __func__, __LINE__);
    if (!disp_drv_dsi_init_context()) 
        return DISP_STATUS_NOT_IMPLEMENTED;

    // DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "%s, line:%d\n", __func__, __LINE__);
    if(lcm_params->dsi.mode == CMD_MODE) 
    {
        #ifndef MT65XX_NEW_DISP
            init_lcd();
        #endif

        init_dsi(isLcmInited);
        mdelay(1);
        
        // DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "%s, line:%d\n", __func__, __LINE__);
        if (NULL != lcm_drv->init && !isLcmInited) 
        {
            lcm_drv->init();
            DSI_LP_Reset();
        }
        // DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "%s, line:%d\n", __func__, __LINE__);
        #ifndef MT65XX_NEW_DISP
            DSI_clk_HS_mode(0);
        #else
            DSI_clk_HS_mode(1);
        #endif

        // DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "%s, line:%d\n", __func__, __LINE__);
        DSI_SetMode(lcm_params->dsi.mode);
        #ifndef MT65XX_NEW_DISP
            init_lcd_te_control();
        #endif
    }
    else 
    {
        #ifndef MT65XX_NEW_DISP
            init_intermediate_buffers(fbPA);
            
            init_lcd();
            init_dpi(isLcmInited);
        #endif

        if (!isLcmInited)
        {
            DSI_SetMode(0);
            mdelay(100);
            DSI_Stop();
        }
        else
        {
            is_video_mode_running = true;
        }
        init_dsi(isLcmInited);
        mdelay(1);
        
        if (NULL != lcm_drv->init && !isLcmInited) 
        {
            lcm_drv->init();
            DSI_LP_Reset();
        }
        
        DSI_SetMode(lcm_params->dsi.mode);
        
        #ifndef BUILD_UBOOT	
            if(lcm_params->dsi.lcm_ext_te_monitor)
            {
                is_video_mode_running = false;
                LCD_TE_SetMode(LCD_TE_MODE_VSYNC_ONLY);
                LCD_TE_SetEdgePolarity(LCM_POLARITY_RISING);
                LCD_TE_Enable(FALSE);
            }
            
            if(lcm_params->dsi.noncont_clock)
                DSI_set_noncont_clk(false, lcm_params->dsi.noncont_clock_period);
            
            if(lcm_params->dsi.lcm_int_te_monitor)
                DSI_set_int_TE(false, lcm_params->dsi.lcm_int_te_period);			
        #endif			
    }

    dsi_config_ddp(fbPA);

    printk("%s, config done\n", __func__);

    return DISP_STATUS_OK;
}