/*
*********************************************************************************************************
* disp_clk_cfg
*
* Description : Config PLL and mclk depend on all kinds of display devices
*
* Arguments : screen_id <display channel>
* type <display device type: tv/vga/hdmi/lcd>
* mode <display mode of tv/vga/hdmi: 480i, ntsc...>
*
* Returns : success <DIS_SUCCESS>
* fail <DIS_FAIL>
*
* Note : None.
*
*********************************************************************************************************
*/
__s32 disp_clk_cfg(__u32 screen_id, __u32 type, __u8 mode)
{
__u32 pll_freq = 297000000, tve_freq = 27000000;
__u32 hdmi_freq = 74250000;
__s32 videopll_sel, pre_scale = 1;
__u32 lcd_clk_div = 0;
__u32 pll_2x = 0;
if(type == DISP_OUTPUT_TYPE_TV || type == DISP_OUTPUT_TYPE_HDMI) {
pll_freq = clk_tab.tv_clk_tab[mode].pll_clk;
tve_freq = clk_tab.tv_clk_tab[mode].tve_clk;
pre_scale = clk_tab.tv_clk_tab[mode].pre_scale;
hdmi_freq = clk_tab.tv_clk_tab[mode].hdmi_clk;
pll_2x = clk_tab.tv_clk_tab[mode].pll_2x;
} else if(type == DISP_OUTPUT_TYPE_VGA) {
pll_freq = clk_tab.vga_clk_tab[mode].pll_clk;
tve_freq = clk_tab.vga_clk_tab[mode].tve_clk;
pre_scale = clk_tab.vga_clk_tab[mode].pre_scale;
pll_2x = clk_tab.vga_clk_tab[mode].pll_2x;
} else if(type == DISP_OUTPUT_TYPE_LCD) {
pll_freq = LCD_PLL_Calc(screen_id, (__panel_para_t*)&gpanel_info[screen_id], &lcd_clk_div);
pre_scale = 1;
#if (!defined CONFIG_ARCH_SUN7I)
__disp_ccmu_coef coef;
#if defined (CONFIG_A50_FPGA)
if(gpanel_info[screen_id].lcd_if != LCD_IF_LVDS) {
lcd_clk_div = 3;
}
#endif
tcon0_set_dclk_div(screen_id,lcd_clk_div);
disp_mipipll_calc_coefficient(297000000, pll_freq, &coef);
disp_mipipll_set_coefficient(&coef);
return DIS_SUCCESS;
#endif
} else {
return DIS_SUCCESS;
}
if ( (videopll_sel = disp_pll_assign(screen_id, pll_freq)) == -1) {
DE_WRN("===pll assign fail====\n");
return DIS_FAIL;
}
disp_pll_set(screen_id, videopll_sel, pll_freq, tve_freq, pre_scale, lcd_clk_div, hdmi_freq, pll_2x, type);
if(videopll_sel == 0) {
gdisp.screen[screen_id].pll_use_status |= VIDEO_PLL0_USED;
} else if(videopll_sel == 1) {
gdisp.screen[screen_id].pll_use_status |= VIDEO_PLL1_USED;
}
return DIS_SUCCESS;
}
/*
*********************************************************************************************************
* disp_clk_cfg
*
* Description : Config PLL and mclk depend on all kinds of display devices
*
* Arguments : sel <display channel>
* type <display device type: tv/vga/hdmi/lcd>
* mode <display mode of tv/vga/hdmi: 480i, ntsc...>
*
* Returns : success <DIS_SUCCESS>
* fail <DIS_FAIL>
*
* Note : None.
*
*********************************************************************************************************
*/
__s32 disp_clk_cfg(__u32 sel, __u32 type, __u8 mode)
{ __u32 pll_freq = 297000000, tve_freq = 27000000;
__u32 hdmi_freq = 74250000;
__s32 videopll_sel, pre_scale = 1;
__u32 lcd_clk_div = 0;
__u32 pll_2x = 0;
if(type == DISP_OUTPUT_TYPE_TV || type == DISP_OUTPUT_TYPE_HDMI)
{
pll_freq = clk_tab.tv_clk_tab[mode].pll_clk;
tve_freq = clk_tab.tv_clk_tab[mode].tve_clk;
pre_scale = clk_tab.tv_clk_tab[mode].pre_scale;
hdmi_freq = clk_tab.tv_clk_tab[mode].hdmi_clk;
pll_2x = clk_tab.tv_clk_tab[mode].pll_2x;
}
else if(type == DISP_OUTPUT_TYPE_VGA)
{
pll_freq = clk_tab.vga_clk_tab[mode].pll_clk;
tve_freq = clk_tab.vga_clk_tab[mode].tve_clk;
pre_scale = clk_tab.vga_clk_tab[mode].pre_scale;
pll_2x = clk_tab.vga_clk_tab[mode].pll_2x;
}
else if(type == DISP_OUTPUT_TYPE_LCD)
{
pll_freq = LCD_PLL_Calc(sel, (__panel_para_t*)&gpanel_info[sel], &lcd_clk_div);
pre_scale = 1;
}
else
{
return DIS_SUCCESS;
}
if ( (videopll_sel = disp_pll_assign(sel, pll_freq)) == -1)
{
return DIS_FAIL;
}
disp_pll_set(sel, videopll_sel, pll_freq, tve_freq, pre_scale, lcd_clk_div, hdmi_freq, pll_2x, type);
if(videopll_sel == 0)
{
gdisp.screen[sel].pll_use_status |= VIDEO_PLL0_USED;
}
else if(videopll_sel == 1)
{
gdisp.screen[sel].pll_use_status |= VIDEO_PLL1_USED;
}
return DIS_SUCCESS;
}