static void dispc_layer_init(struct sprdfb_device *dev)
{
uint32_t reg_val = 0;
FB_PRINT("sprdfb:[%s]\n",__FUNCTION__);
dispc_clear_bits((1<<0),DISPC_IMG_CTRL);
dispc_clear_bits((1<<0),DISPC_OSD_CTRL);
/******************* OSD layer setting **********************/
/*enable OSD layer*/
reg_val |= (1 << 0);
/*disable color key */
/* alpha mode select - block alpha*/
reg_val |= (1 << 2);
/* data format */
/* RGB565 */
reg_val |= (5 << 4);
/* B2B3B0B1 */
reg_val |= (2 << 8);
dispc_write(reg_val, DISPC_OSD_CTRL);
/* OSD layer alpha value */
dispc_write(0xff, DISPC_OSD_ALPHA);
/* OSD layer size */
reg_val = ( dev->panel->width& 0xfff) | ((dev->panel->height & 0xfff ) << 16);
dispc_write(reg_val, DISPC_OSD_SIZE_XY);
/* OSD layer start position */
dispc_write(0, DISPC_OSD_DISP_XY);
/* OSD layer pitch */
reg_val = ( dev->panel->width & 0xfff) ;
dispc_write(reg_val, DISPC_OSD_PITCH);
/*OSD base address*/
dispc_write(dev->smem_start, DISPC_OSD_BASE_ADDR);
/* OSD color_key value */
dispc_set_osd_ck(0x0);
/* DISPC workplane size */
dispc_set_disp_size(dev);
FB_PRINT("DISPC_OSD_CTRL: 0x%x\n", dispc_read(DISPC_OSD_CTRL));
FB_PRINT("DISPC_OSD_ALPHA: 0x%x\n", dispc_read(DISPC_OSD_ALPHA));
FB_PRINT("DISPC_OSD_SIZE_XY: 0x%x\n", dispc_read(DISPC_OSD_SIZE_XY));
FB_PRINT("DISPC_OSD_DISP_XY: 0x%x\n", dispc_read(DISPC_OSD_DISP_XY));
FB_PRINT("DISPC_OSD_PITCH: 0x%x\n", dispc_read(DISPC_OSD_PITCH));
FB_PRINT("DISPC_OSD_BASE_ADDR: 0x%x\n", dispc_read(DISPC_OSD_BASE_ADDR));
}
static void dispc_layer_init(struct panel_spec *panel)
{
uint32_t reg_val = 0;
// dispc_clear_bits((1<<0),DISPC_IMG_CTRL);
dispc_write(0x0, DISPC_IMG_CTRL);
dispc_clear_bits((1<<0),DISPC_OSD_CTRL);
/******************* OSD layer setting **********************/
/*enable OSD layer*/
reg_val |= (1 << 0);
/*disable color key */
/* alpha mode select - block alpha*/
reg_val |= (1 << 2);
/* data format */
//if (var->bits_per_pixel == 32) {
if(1){
/* ABGR */
reg_val |= (3 << 4);
/* rb switch */
reg_val |= (1 << 15);
} else {
/* RGB565 */
reg_val |= (5 << 4);
/* B2B3B0B1 */
reg_val |= (2 << 8);
}
dispc_write(reg_val, DISPC_OSD_CTRL);
/* OSD layer alpha value */
dispc_write(0xff, DISPC_OSD_ALPHA);
/* OSD layer size */
reg_val = ( panel->width & 0xfff) | (( panel->height & 0xfff ) << 16);
dispc_write(reg_val, DISPC_OSD_SIZE_XY);
/* OSD layer start position */
dispc_write(0, DISPC_OSD_DISP_XY);
/* OSD layer pitch */
reg_val = ( panel->width & 0xfff) ;
dispc_write(reg_val, DISPC_OSD_PITCH);
/* OSD color_key value */
dispc_set_osd_ck(0x0);
/* DISPC workplane size */
reg_val = ( panel->width & 0xfff) | ((panel->height & 0xfff ) << 16);
dispc_write(reg_val, DISPC_SIZE_XY);
}
