static void __init netx_timer_init(void)
{
/* disable timer initially */
writel(0, NETX_GPIO_COUNTER_CTRL(0));
/* Reset the timer value to zero */
writel(0, NETX_GPIO_COUNTER_CURRENT(0));
writel(LATCH, NETX_GPIO_COUNTER_MAX(0));
/* acknowledge interrupt */
writel(COUNTER_BIT(0), NETX_GPIO_IRQ);
/* Enable the interrupt in the specific timer
* register and start timer
*/
writel(COUNTER_BIT(0), NETX_GPIO_IRQ_ENABLE);
writel(NETX_GPIO_COUNTER_CTRL_IRQ_EN | NETX_GPIO_COUNTER_CTRL_RUN,
NETX_GPIO_COUNTER_CTRL(0));
setup_irq(NETX_IRQ_TIMER0, &netx_timer_irq);
/* Setup timer one for clocksource */
writel(0, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKSOURCE));
writel(0, NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKSOURCE));
writel(0xffffffff, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKSOURCE));
writel(NETX_GPIO_COUNTER_CTRL_RUN,
NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKSOURCE));
clocksource_netx.mult =
clocksource_hz2mult(CLOCK_TICK_RATE, clocksource_netx.shift);
clocksource_register(&clocksource_netx);
netx_clockevent.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC,
netx_clockevent.shift);
netx_clockevent.max_delta_ns =
clockevent_delta2ns(0xfffffffe, &netx_clockevent);
/* with max_delta_ns >= delta2ns(0x800) the system currently runs fine.
* Adding some safety ... */
netx_clockevent.min_delta_ns =
clockevent_delta2ns(0xa00, &netx_clockevent);
netx_clockevent.cpumask = cpumask_of(0);
clockevents_register_device(&netx_clockevent);
}
void __init at91sam926x_clockevent_init(void)
{
/* Reset time-stamp counter */
at91_sys_write(AT91_PIT_MR, 0);
at91_sys_read(AT91_PIT_PIVR);
/* Make IRQs happen for the system timer. */
setup_irq(AT91_ID_SYS, &at91sam926x_timer_irq);
clockevent_at91sam926x.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC,
clockevent_at91sam926x.shift);
clockevent_at91sam926x.max_delta_ns =
clockevent_delta2ns(0xffffe, &clockevent_at91sam926x);
clockevent_at91sam926x.min_delta_ns =
clockevent_delta2ns(0xf, &clockevent_at91sam926x);
clockevent_at91sam926x.cpumask = cpumask_of_cpu(0);
clockevents_register_device(&clockevent_at91sam926x);
}
static void sh_tmu_clock_event_start(struct sh_tmu_priv *p, int periodic)
{
struct clock_event_device *ced = &p->ced;
sh_tmu_enable(p);
/* TODO: calculate good shift from rate and counter bit width */
ced->shift = 32;
ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift);
ced->max_delta_ns = clockevent_delta2ns(0xffffffff, ced);
ced->min_delta_ns = 5000;
if (periodic) {
p->periodic = (p->rate + HZ/2) / HZ;
sh_tmu_set_next(p, p->periodic, 1);
}
}
void __init timer_init(int irq)
{
timer_config();
set_tcr2ns_scale(CLOCK_TICK_RATE);
ckevt.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, ckevt.shift);
ckevt.max_delta_ns = clockevent_delta2ns(MAX_DELTA, &ckevt);
ckevt.min_delta_ns = clockevent_delta2ns(MIN_DELTA, &ckevt);
ckevt.cpumask = cpumask_of(0);
cksrc.mult = clocksource_hz2mult(CLOCK_TICK_RATE, cksrc.shift);
setup_irq(irq, &timer_irq);
clocksource_register(&cksrc);
clockevents_register_device(&ckevt);
}
static void sh_cmt_clock_event_start(struct sh_cmt_priv *p, int periodic)
{
struct clock_event_device *ced = &p->ced;
sh_cmt_start(p, FLAG_CLOCKEVENT);
/* TODO: calculate good shift from rate and counter bit width */
ced->shift = 32;
ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift);
ced->max_delta_ns = clockevent_delta2ns(p->max_match_value, ced);
ced->min_delta_ns = clockevent_delta2ns(0x1f, ced);
if (periodic)
sh_cmt_set_next(p, (p->rate + HZ/2) / HZ);
else
sh_cmt_set_next(p, p->max_match_value);
}
static void arch_timer_setup(unsigned int cpu)
{
unsigned int txdivtime;
struct clock_event_device *clk = &per_cpu(local_clockevent, cpu);
char *name = per_cpu(local_clockevent_name, cpu);
txdivtime = __core_reg_get(TXDIVTIME);
txdivtime &= ~TXDIVTIME_DIV_BITS;
txdivtime |= (HARDWARE_DIV & TXDIVTIME_DIV_BITS);
__core_reg_set(TXDIVTIME, txdivtime);
sprintf(name, "META %d", cpu);
clk->name = name;
clk->features = CLOCK_EVT_FEAT_ONESHOT,
clk->rating = 200,
clk->shift = 12,
clk->irq = tbisig_map(TBID_SIGNUM_TRT),
clk->set_mode = metag_timer_set_mode,
clk->set_next_event = metag_timer_set_next_event,
clk->mult = div_sc(hwtimer_freq, NSEC_PER_SEC, clk->shift);
clk->max_delta_ns = clockevent_delta2ns(0x7fffffff, clk);
clk->min_delta_ns = clockevent_delta2ns(0xf, clk);
clk->cpumask = cpumask_of(cpu);
clockevents_register_device(clk);
/*
* For all non-boot CPUs we need to synchronize our free
* running clock (TXTIMER) with the boot CPU's clock.
*
* While this won't be accurate, it should be close enough.
*/
if (cpu) {
unsigned int thread0 = cpu_2_hwthread_id[0];
unsigned long val;
val = core_reg_read(TXUCT_ID, TXTIMER_REGNUM, thread0);
__core_reg_set(TXTIMER, val);
}
}
/*
* Set up timer interrupt, and return the current time in seconds.
*/
void mxs_nomatch_timer_init(struct mxs_sys_timer *timer)
{
if (online_timer)
return;
online_timer = timer;
cksrc_mxs_nomatch.mult = clocksource_hz2mult(CLOCK_TICK_RATE,
cksrc_mxs_nomatch.shift);
ckevt_timrot.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC,
ckevt_timrot.shift);
ckevt_timrot.min_delta_ns = clockevent_delta2ns(2, &ckevt_timrot);
ckevt_timrot.max_delta_ns = clockevent_delta2ns(0xFFF, &ckevt_timrot);
ckevt_timrot.cpumask = cpumask_of(0);
/* clear two timers */
__raw_writel(0, online_timer->base + HW_TIMROT_TIMCOUNTn(0));
__raw_writel(0, online_timer->base + HW_TIMROT_TIMCOUNTn(1));
/* configure them */
__raw_writel(
(8 << BP_TIMROT_TIMCTRLn_SELECT) | /* 32 kHz */
BM_TIMROT_TIMCTRLn_RELOAD |
BM_TIMROT_TIMCTRLn_UPDATE |
BM_TIMROT_TIMCTRLn_IRQ_EN,
online_timer->base + HW_TIMROT_TIMCTRLn(0));
__raw_writel(
(8 << BP_TIMROT_TIMCTRLn_SELECT) | /* 32 kHz */
BM_TIMROT_TIMCTRLn_RELOAD |
BM_TIMROT_TIMCTRLn_UPDATE |
BM_TIMROT_TIMCTRLn_IRQ_EN,
online_timer->base + HW_TIMROT_TIMCTRLn(1));
__raw_writel(CLOCK_TICK_RATE / HZ - 1,
online_timer->base + HW_TIMROT_TIMCOUNTn(0));
__raw_writel(0xFFFF, online_timer->base + HW_TIMROT_TIMCOUNTn(1));
setup_irq(IRQ_TIMER0, &mxs_nomatch_timer_irq);
clocksource_register(&cksrc_mxs_nomatch);
clockevents_register_device(&ckevt_timrot);
}
static void __init godarm_timer_init(void){
edb_trace();
setup_irq(TIMER01_IRQ, &godarm_timer_irq);
setup_irq(TIMER01_IRQ, &godarm_freetimer_irq);
godarm_clocksource_init();
timer0_clockevent.mult =
div_sc(timer0_clk_hz, NSEC_PER_SEC, timer0_clockevent.shift);
timer0_clockevent.max_delta_ns =
clockevent_delta2ns(0xffffffff, &timer0_clockevent);
timer0_clockevent.min_delta_ns =
clockevent_delta2ns(0xf, &timer0_clockevent);
timer0_clockevent.cpumask = cpumask_of(0);
clockevents_register_device(&timer0_clockevent);
edb_trace();
}
static inline void setup_clkevt(u32 freq)
{
unsigned int cmp;
struct clock_event_device *evt = &gpt_clockevent;
struct gpt_device *dev = id_to_dev(GPT_CLKEVT_ID);
evt->mult = div_sc(freq, NSEC_PER_SEC, evt->shift);
evt->max_delta_ns = clockevent_delta2ns(0xffffffff, evt);
evt->min_delta_ns = clockevent_delta2ns(3, evt);
evt->cpumask = cpumask_of(0);
setup_gpt_dev_locked(dev, GPT_REPEAT, GPT_CLK_SRC_SYS, GPT_CLK_DIV_1,
freq / HZ, clkevt_handler, GPT_ISR);
__gpt_get_cmp(dev, &cmp);
pr_alert("GPT1_CMP = %d, HZ = %d\n", cmp, HZ);
clockevents_register_device(evt);
}
static int __init mxc_clockevent_init(void)
{
unsigned int clock;
clock = clk_get_rate(timer_clk);
clockevent_mxc.mult = div_sc(clock, NSEC_PER_SEC,
clockevent_mxc.shift);
clockevent_mxc.max_delta_ns =
clockevent_delta2ns(0xfffffffe, &clockevent_mxc);
clockevent_mxc.min_delta_ns =
clockevent_delta2ns(0xff, &clockevent_mxc);
clockevent_mxc.cpumask = cpumask_of_cpu(0);
clockevents_register_device(&clockevent_mxc);
return 0;
}
static void __init omap2_gp_clockevent_init(void)
{
u32 tick_rate;
int src;
inited = 1;
gptimer = omap_dm_timer_request_specific(gptimer_id);
BUG_ON(gptimer == NULL);
gptimer_wakeup = gptimer;
#if defined(CONFIG_OMAP_32K_TIMER)
src = OMAP_TIMER_SRC_32_KHZ;
#else
src = OMAP_TIMER_SRC_SYS_CLK;
WARN(gptimer_id == 12, "WARNING: GPTIMER12 can only use the "
"secure 32KiHz clock source\n");
#endif
if (gptimer_id != 12)
WARN(IS_ERR_VALUE(omap_dm_timer_set_source(gptimer, src)),
"timer-gp: omap_dm_timer_set_source() failed\n");
tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer));
pr_info("OMAP clockevent source: GPTIMER%d at %u Hz\n",
gptimer_id, tick_rate);
omap2_gp_timer_irq.dev_id = (void *)gptimer;
setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq);
omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
clockevent_gpt.mult = div_sc(tick_rate, NSEC_PER_SEC,
clockevent_gpt.shift);
clockevent_gpt.max_delta_ns =
clockevent_delta2ns(0xffffffff, &clockevent_gpt);
clockevent_gpt.min_delta_ns =
clockevent_delta2ns(3, &clockevent_gpt);
/* Timer internal resynch latency. */
clockevent_gpt.cpumask = cpumask_of(0);
clockevents_register_device(&clockevent_gpt);
}
static void __init tcc88xx_timer_init(void)
{
unsigned long rate;
rate = TCC_TIMER_FREQ;
pTIMER = (volatile PTIMER) tcc_p2v(HwTMR_BASE);
pPIC = (volatile PPIC) tcc_p2v(HwPIC_BASE);
pTIMER->TC32EN = 1; /* Timer disable, Prescale is one */
BITSET(pTIMER->TC32EN, Hw24); /* Timer Enable */
if (pTIMER->TC32IRQ & Hw31) /* IRQ clear */
BITSET(pTIMER->TC32IRQ, Hw31);
ckevt_tcc88xx_osmr0.mult =
div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, ckevt_tcc88xx_osmr0.shift);
ckevt_tcc88xx_osmr0.max_delta_ns =
clockevent_delta2ns(0x7fffffff, &ckevt_tcc88xx_osmr0);
ckevt_tcc88xx_osmr0.min_delta_ns =
clockevent_delta2ns(4, &ckevt_tcc88xx_osmr0) + 1;
ckevt_tcc88xx_osmr0.cpumask = cpumask_of(0);
cksrc_tcc88xx_oscr.mult =
clocksource_hz2mult(CLOCK_TICK_RATE, cksrc_tcc88xx_oscr.shift);
BITSET(pPIC->SEL0, TCC_ENABLE_BIT(INT_TC32));
BITSET(pPIC->IEN0, TCC_ENABLE_BIT(INT_TC32));
BITSET(pPIC->INTMSK0, TCC_ENABLE_BIT(INT_TC32));
BITSET(pPIC->MODEA0, TCC_ENABLE_BIT(INT_TC32));
setup_irq(INT_TC32, &tcc88xx_timer_irq);
clocksource_register(&cksrc_tcc88xx_oscr);
clockevents_register_device(&ckevt_tcc88xx_osmr0);
/*
* Set scale and timer for sched_clock
*/
setup_sched_clock(CLOCK_TICK_RATE);
clock_valid = 1;
}
void __init
orion_time_init(u32 _bridge_base, u32 _bridge_timer1_clr_mask,
unsigned int irq, unsigned int tclk)
{
u32 u;
/*
*/
bridge_base = (void __iomem *)_bridge_base;
bridge_timer1_clr_mask = _bridge_timer1_clr_mask;
ticks_per_jiffy = (tclk + HZ/2) / HZ;
/*
*/
setup_sched_clock(orion_read_sched_clock, 32, tclk);
/*
*/
writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
u = readl(bridge_base + BRIDGE_MASK_OFF);
writel(u & ~BRIDGE_INT_TIMER0, bridge_base + BRIDGE_MASK_OFF);
u = readl(timer_base + TIMER_CTRL_OFF);
writel(u | TIMER0_EN | TIMER0_RELOAD_EN, timer_base + TIMER_CTRL_OFF);
clocksource_mmio_init(timer_base + TIMER0_VAL_OFF, "orion_clocksource",
tclk, 300, 32, clocksource_mmio_readl_down);
/*
*/
setup_irq(irq, &orion_timer_irq);
orion_clkevt.mult = div_sc(tclk, NSEC_PER_SEC, orion_clkevt.shift);
orion_clkevt.max_delta_ns = clockevent_delta2ns(0xfffffffe, &orion_clkevt);
orion_clkevt.min_delta_ns = clockevent_delta2ns(1, &orion_clkevt);
orion_clkevt.cpumask = cpumask_of(0);
clockevents_register_device(&orion_clkevt);
}
static void __init s3c64xx_clock_event_init(void)
{
unsigned long clock_rate;
clock_rate = clk_get_rate(event_in);
clock_count_per_tick = clock_rate / HZ;
s3c64xx_clock_event_device.mult = div_sc(clock_rate,
NSEC_PER_SEC, s3c64xx_clock_event_device.shift);
s3c64xx_clock_event_device.max_delta_ns =
clockevent_delta2ns(-1, &s3c64xx_clock_event_device);
s3c64xx_clock_event_device.min_delta_ns =
clockevent_delta2ns(1, &s3c64xx_clock_event_device);
s3c64xx_clock_event_device.cpumask = cpumask_of(0);
clockevents_register_device(&s3c64xx_clock_event_device);
setup_irq(IRQ_TIMER3, &s3c64xx_clock_event_irq);
}
static void __init sa1100_timer_init(void)
{
OIER = 0; /* disable any timer interrupts */
OSSR = 0xf; /* clear status on all timers */
ckevt_sa1100_osmr0.mult =
div_sc(3686400, NSEC_PER_SEC, ckevt_sa1100_osmr0.shift);
ckevt_sa1100_osmr0.max_delta_ns =
clockevent_delta2ns(0x7fffffff, &ckevt_sa1100_osmr0);
ckevt_sa1100_osmr0.min_delta_ns =
clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_sa1100_osmr0) + 1;
cksrc_sa1100_oscr.mult =
clocksource_hz2mult(CLOCK_TICK_RATE, cksrc_sa1100_oscr.shift);
setup_irq(IRQ_OST0, &sa1100_timer_irq);
clocksource_register(&cksrc_sa1100_oscr);
clockevents_register_device(&ckevt_sa1100_osmr0);
}
static int __init tcc_clockevent_init(struct clk *clock)
{
unsigned int c = clk_get_rate(clock);
clocksource_mmio_init(timer_base + TC32MCNT_OFFS, "tcc_tc32", c,
200, 32, clocksource_mmio_readl_up);
clockevent_tcc.mult = div_sc(c, NSEC_PER_SEC,
clockevent_tcc.shift);
clockevent_tcc.max_delta_ns =
clockevent_delta2ns(0xfffffffe, &clockevent_tcc);
clockevent_tcc.min_delta_ns =
clockevent_delta2ns(0xff, &clockevent_tcc);
clockevent_tcc.cpumask = cpumask_of(0);
clockevents_register_device(&clockevent_tcc);
return 0;
}
static void __init pxa_timer_init(void)
{
OIER = 0;
OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;
ckevt_pxa_osmr0.mult =
div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, ckevt_pxa_osmr0.shift);
ckevt_pxa_osmr0.max_delta_ns =
clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0);
ckevt_pxa_osmr0.min_delta_ns =
clockevent_delta2ns(MIN_OSCR_DELTA, &ckevt_pxa_osmr0) + 1;
cksrc_pxa_oscr0.mult =
clocksource_hz2mult(CLOCK_TICK_RATE, cksrc_pxa_oscr0.shift);
setup_irq(IRQ_OST0, &pxa_ost0_irq);
clocksource_register(&cksrc_pxa_oscr0);
clockevents_register_device(&ckevt_pxa_osmr0);
}
static int __init mxc_clockevent_init(struct clk *timer_clk)
{
unsigned int c = clk_get_rate(timer_clk);
if (timer_is_v2())
clockevent_mxc.set_next_event = v2_set_next_event;
clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC,
clockevent_mxc.shift);
clockevent_mxc.max_delta_ns =
clockevent_delta2ns(0xfffffffe, &clockevent_mxc);
clockevent_mxc.min_delta_ns =
clockevent_delta2ns(0xff, &clockevent_mxc);
clockevent_mxc.cpumask = cpumask_of(0);
clockevents_register_device(&clockevent_mxc);
return 0;
}
/*
* Setup the local clock events for a CPU.
*/
void __cpuinit twd_timer_setup(struct clock_event_device *clk)
{
twd_calibrate_rate();
clk->name = "local_timer";
clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
CLOCK_EVT_FEAT_C3STOP;
clk->rating = 350;
clk->set_mode = twd_set_mode;
clk->set_next_event = twd_set_next_event;
clk->shift = 20;
clk->mult = div_sc(twd_timer_rate, NSEC_PER_SEC, clk->shift);
clk->max_delta_ns = clockevent_delta2ns(0xffffffff, clk);
clk->min_delta_ns = clockevent_delta2ns(0xf, clk);
/* Make sure our local interrupt controller has this enabled */
gic_enable_ppi(clk->irq);
clockevents_register_device(clk);
}
static void mv_init_timer(void)
{
/*
* Setup clocksource free running timer (no interrupt on reload)
*/
MV_REG_WRITE(CNTMR_VAL_REG(CLOCKSOURCE), 0xffffffff);
MV_REG_WRITE(CNTMR_RELOAD_REG(CLOCKSOURCE), 0xffffffff);
MV_REG_BIT_RESET(BRIDGE_INT_MASK_REG, BRIDGE_INT_TIMER(CLOCKSOURCE));
MV_REG_BIT_SET(CNTMR_CTRL_REG, TIMER_RELOAD_EN(CLOCKSOURCE) |
TIMER_EN(CLOCKSOURCE));
kw_clkevt.cpumask = cpumask_of(0);
/*
* Register clocksource
*/
kw_clksrc.mult =
clocksource_hz2mult(mvBoardTclkGet(), kw_clksrc.shift);
clocksource_register(&kw_clksrc);
/*
* Connect and enable tick handler
*/
setup_irq(IRQ_BRIDGE, &kw_timer_irq);
/*
* Register clockevent
*/
kw_clkevt.mult =
div_sc(mvBoardTclkGet(), NSEC_PER_SEC, kw_clkevt.shift);
kw_clkevt.max_delta_ns =
clockevent_delta2ns(0xfffffffe, &kw_clkevt);
kw_clkevt.min_delta_ns =
clockevent_delta2ns(1, &kw_clkevt);
/*
* Setup clockevent timer (interrupt-driven.)
*/
clockevents_register_device(&kw_clkevt);
}
/*
* Set up timer interrupt, and return the current time in seconds.
*/
static void __init versatile_timer_init(void)
{
u32 val;
/*
* set clock frequency:
* VERSATILE_REFCLK is 32KHz
* VERSATILE_TIMCLK is 1MHz
*/
val = readl(__io_address(VERSATILE_SCTL_BASE));
writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
(VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
(VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
(VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
__io_address(VERSATILE_SCTL_BASE));
/*
* Initialise to a known state (all timers off)
*/
writel(0, TIMER0_VA_BASE + TIMER_CTRL);
writel(0, TIMER1_VA_BASE + TIMER_CTRL);
writel(0, TIMER2_VA_BASE + TIMER_CTRL);
writel(0, TIMER3_VA_BASE + TIMER_CTRL);
/*
* Make irqs happen for the system timer
*/
setup_irq(IRQ_TIMERINT0_1, &versatile_timer_irq);
versatile_clocksource_init();
timer0_clockevent.mult =
div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
timer0_clockevent.max_delta_ns =
clockevent_delta2ns(0xffffffff, &timer0_clockevent);
timer0_clockevent.min_delta_ns =
clockevent_delta2ns(0xf, &timer0_clockevent);
timer0_clockevent.cpumask = cpumask_of(0);
clockevents_register_device(&timer0_clockevent);
}
static void __init bcm_clockevent_init(unsigned int rate)
{
bcm_clkevt.mult = div_sc(rate, NSEC_PER_SEC, bcm_clkevt.shift);
bcm_clkevt.max_delta_ns = clockevent_delta2ns(0xfffffffe, &bcm_clkevt);
bcm_clkevt.min_delta_ns = clockevent_delta2ns(0, &bcm_clkevt);
bcm_clkevt.cpumask = cpumask_of(0);
bcm_clkevt.features = CLOCK_EVT_FEAT_ONESHOT;
if (config.ce_module == TIMER_MODULE_GPT) {
bcm_clkevt.set_mode = bcm_gpt_clkevt_mode;
bcm_clkevt.set_next_event = bcm_gpt_set_nextevt;
bcm_clkevt.features |= CLOCK_EVT_FEAT_PERIODIC;
} else if (config.ce_module == TIMER_MODULE_SLEEP_TIMER) {
bcm_clkevt.set_mode = bcm_slptmr_clkevt_mode;
bcm_clkevt.set_next_event = bcm_slptmr_set_nextevt;
writel(1, config.ce_base + SLPTMR_SMTDCLR); /* Setup the Load Register */
}
clockevents_register_device(&bcm_clkevt);
return;
}
/*
* Set up timer interrupt, and return the current time in seconds.
*/
static void __init bcm2708_timer_init(void)
{
/*
* Initialise to a known state (all timers off)
*/
writel(0, __io_address(ARM_T_CONTROL));
/*
* Make irqs happen for the system timer
*/
setup_irq(IRQ_TIMER3, &bcm2708_timer_irq);
timer0_clockevent.mult =
div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
timer0_clockevent.max_delta_ns =
clockevent_delta2ns(0xffffffff, &timer0_clockevent);
timer0_clockevent.min_delta_ns =
clockevent_delta2ns(0xf, &timer0_clockevent);
timer0_clockevent.cpumask = cpumask_of(0);
clockevents_register_device(&timer0_clockevent);
}
void __init sp804_clockevents_init(void __iomem *base, unsigned int irq,
const char *name)
{
struct clock_event_device *evt = &sp804_clockevent;
long rate = sp804_get_clock_rate(name);
if (rate < 0)
return;
clkevt_base = base;
clkevt_reload = DIV_ROUND_CLOSEST(rate, HZ);
evt->name = name;
evt->irq = irq;
evt->mult = div_sc(rate, NSEC_PER_SEC, evt->shift);
evt->max_delta_ns = clockevent_delta2ns(0xffffffff, evt);
evt->min_delta_ns = clockevent_delta2ns(0xf, evt);
setup_irq(irq, &sp804_timer_irq);
clockevents_register_device(evt);
}
static void __init meson_clockevent_init(void)
{
CLEAR_CBUS_REG_MASK(ISA_TIMER_MUX, TIMER_A_INPUT_MASK | TIMER_C_INPUT_MASK);
SET_CBUS_REG_MASK(ISA_TIMER_MUX,
(TIMER_UNIT_1us << TIMER_A_INPUT_BIT) |
(TIMER_UNIT_1us << TIMER_C_INPUT_BIT));
WRITE_CBUS_REG(ISA_TIMERA, 9999);
clockevent_meson_1mhz.mult =
div_sc(1000000, NSEC_PER_SEC, clockevent_meson_1mhz.shift);
clockevent_meson_1mhz.max_delta_ns =
clockevent_delta2ns(0xfffe, &clockevent_meson_1mhz);
clockevent_meson_1mhz.min_delta_ns =
clockevent_delta2ns(1, &clockevent_meson_1mhz);
clockevent_meson_1mhz.cpumask = cpumask_of(0);
clockevents_register_device(&clockevent_meson_1mhz);
/* Set up the IRQ handler */
setup_irq(INT_TIMER_A, &meson_timer_irq);
setup_irq(INT_TIMER_C, &meson_timer_irq);
}
static void __init s5pv310_clockevent_init(void)
{
unsigned long clock_rate;
clock_rate = clk_get_rate(timerclk);
clock_count_per_tick = clock_rate / HZ;
sys_tick_event_device.mult =
div_sc(clock_rate, NSEC_PER_SEC, sys_tick_event_device.shift);
sys_tick_event_device.max_delta_ns =
clockevent_delta2ns(-1, &sys_tick_event_device);
sys_tick_event_device.min_delta_ns =
clockevent_delta2ns(0x1, &sys_tick_event_device);
sys_tick_event_device.cpumask = cpumask_of(0);
clockevents_register_device(&sys_tick_event_device);
s5pv310_systimer_write(S5PV310_INT_TICK_EN | S5PV310_INT_EN, S5PV310_INT_CSTAT);
setup_irq(IRQ_SYSTEM_TIMER, &s5pv310_clock_event_irq);
}
static int __cpuinit sprd_local_timer_setup(struct clock_event_device *evt)
{
int cpu = smp_processor_id();
evt->irq = irq_nr[cpu];
evt->name = "local_timer";
evt->features = CLOCK_EVT_FEAT_ONESHOT;
evt->rating = 200;
evt->set_mode = __gptimer_set_mode;
evt->set_next_event = __gptimer_set_next_event;
evt->shift = 32;
evt->mult = div_sc(32768, NSEC_PER_SEC, evt->shift);
evt->max_delta_ns = clockevent_delta2ns(0xf0000000, evt);
evt->min_delta_ns = clockevent_delta2ns(4, evt);
local_evt[cpu] = evt;
irq_set_affinity(evt->irq, cpumask_of(cpu));
clockevents_register_device(evt);
return 0;
}
static void sprd_gptimer_clockevent_init(unsigned int irq, const char *name,
unsigned long hz)
{
struct clock_event_device *evt = &bctimer_event;
int ret = 0;
__raw_writel(TIMER_DISABLE, TIMER_CTL(BC_CPU, BC_TIMER));
__raw_writel(TIMER_INT_CLR, TIMER_INT(BC_CPU, BC_TIMER));
evt->name = name;
evt->irq = irq;
evt->mult = div_sc(hz, NSEC_PER_SEC, evt->shift);
evt->max_delta_ns = clockevent_delta2ns(ULONG_MAX, evt);
evt->min_delta_ns = clockevent_delta2ns(2, evt);
evt->cpumask = cpu_all_mask;
ret = setup_irq(irq, &bctimer_irq);
if (ret)
BUG_ON(1);
clockevents_register_device(evt);
}
static void __init setup_itimer(void)
{
int err;
err = request_irq(TIMER_IRQ, um_timer, 0, "timer", NULL);
if (err != 0)
printk(KERN_ERR "register_timer : request_irq failed - "
"errno = %d\n", -err);
itimer_clockevent.mult = div_sc(HZ, NSEC_PER_SEC, 32);
itimer_clockevent.max_delta_ns =
clockevent_delta2ns(60 * HZ, &itimer_clockevent);
itimer_clockevent.min_delta_ns =
clockevent_delta2ns(1, &itimer_clockevent);
err = clocksource_register_hz(&itimer_clocksource, USEC_PER_SEC);
if (err) {
printk(KERN_ERR "clocksource_register_hz returned %d\n", err);
return;
}
clockevents_register_device(&itimer_clockevent);
}
static inline void setup_clkevt(void)
{
unsigned int cmp;
struct clock_event_device *evt = &mt6582_gpt.clockevent;
struct gpt_device *dev = id_to_dev(GPT_CLKEVT_ID);
evt->mult = div_sc(SYS_CLK_RATE, NSEC_PER_SEC, evt->shift);
evt->max_delta_ns = clockevent_delta2ns(0xffffffff, evt);
evt->min_delta_ns = clockevent_delta2ns(3, evt);
evt->cpumask = cpumask_of(0);
#ifndef CONFIG_MT6582_FPGA
setup_gpt_dev_locked(dev, GPT_REPEAT, GPT_CLK_SRC_SYS, GPT_CLK_DIV_1,
SYS_CLK_RATE / HZ, clkevt_handler, GPT_ISR);
#else
setup_gpt_dev_locked(dev, GPT_REPEAT, GPT_CLK_SRC_SYS, GPT_CLK_DIV_1,
SYS_CLK_RATE / HZ, clkevt_handler, GPT_ISR);
#endif
__gpt_get_cmp(dev, &cmp);
printk("GPT1_CMP = %d, HZ = %d\n", cmp, HZ);
}
