/* Set PHY operationg mode */
rt_inline void phy_mode_set(rt_uint32_t media_mode)
{
rt_uint16_t phy_reg4 = 0x01e1, phy_reg0 = 0x1000;
if (!(media_mode & DM9000_AUTO))
{
switch (media_mode)
{
case DM9000_10MHD:
phy_reg4 = 0x21;
phy_reg0 = 0x0000;
break;
case DM9000_10MFD:
phy_reg4 = 0x41;
phy_reg0 = 0x1100;
break;
case DM9000_100MHD:
phy_reg4 = 0x81;
phy_reg0 = 0x2000;
break;
case DM9000_100MFD:
phy_reg4 = 0x101;
phy_reg0 = 0x3100;
break;
}
dm9000_phy_write(4, phy_reg4); /* Set PHY media mode */
dm9000_phy_write(0, phy_reg0); /* Tmp */
}
dm9000_reg_write(DM9000_REG_GPCR, 0x01); /* Let GPIO0 output */
dm9000_reg_write(DM9000_REG_GPR, 0x00); /* Enable PHY */
}
int dm9000_send(unsigned char *datas, int len)
{
int i;
unsigned short *ds = (unsigned short *)datas;
dm9000_reg_write(DM9000_ISR, 1 << 1);
//把数据包写到TX FIFO SRAM
writeb(DM9000_MWCMD, DM9000_ADDR_PORT);
for(i = 0; i < len; i += 2)
writew(*ds++, DM9000_DATA_PORT);
//设定发送数据包的长度
dm9000_reg_write(DM9000_TXPLL, len & 0xff);
dm9000_reg_write(DM9000_TXPLH, (len >> 8) & 0xff);
//启动发送功能
dm9000_reg_write(DM9000_TCR, 0x1);
//等待数据包发送完成
while(!(dm9000_reg_read(DM9000_ISR) & (1 << 1)));
while(!(dm9000_reg_read(DM9000_NSR) & 0xc));
return len;
}
/* interrupt service routine */
void rt_dm9000_isr()
{
rt_uint16_t isr_status;
rt_uint16_t save_reg;
save_reg = DM9000_REG_ADDR;
/* Disable all interrupts */
dm9000_reg_write(DM9000_REG_IMR, IMR_PAR);
/* Got DM9000 interrupt status */
isr_status = dm9000_reg_read(DM9000_REG_ISR); /* Got ISR */
dm9000_reg_write(DM9000_REG_ISR, isr_status); /* Clear ISR status */
DM9000_TRACE("dm9000 isr: int status %04x\n", isr_status);
/* receive overflow */
if (isr_status & ISR_ROS)
{
rt_kprintf("overflow\n");
}
if (isr_status & ISR_ROOS)
{
rt_kprintf("overflow counter overflow\n");
}
/* Received the coming packet */
if (isr_status & ISR_PRS)
{
/* disable receive interrupt */
dm9000_device.imr_all = IMR_PAR | IMR_PTI;
/* a frame has been received */
eth_device_ready(&(dm9000_device.parent));
}
/* Transmit Interrupt check */
if (isr_status & ISR_PTS)
{
/* transmit done */
int tx_status = dm9000_reg_read(DM9000_REG_NSR); /* Got TX status */
if (tx_status & (NSR_TX2END | NSR_TX1END))
{
dm9000_device.packet_cnt --;
if (dm9000_device.packet_cnt > 0)
{
DM9000_TRACE("dm9000 isr: tx second packet\n");
/* transmit packet II */
/* Set TX length to DM9000 */
dm9000_reg_write(DM9000_REG_TXPLL, dm9000_device.queue_packet_len & 0xff);
dm9000_reg_write(DM9000_REG_TXPLH, (dm9000_device.queue_packet_len >> 8) & 0xff);
/* Issue TX polling command */
dm9000_reg_write(DM9000_REG_TCR, TCR_TXREQ); /* Cleared after TX complete */
}
/* Read a word from phyxcer */
rt_inline rt_uint16_t dm9000_phy_read(rt_uint16_t reg)
{
rt_uint16_t val;
/* Fill the phyxcer register into REG_0C */
dm9000_reg_write(DM9000_REG_EPAR, DM9000_PHY | reg);
dm9000_reg_write(DM9000_REG_EPCR, 0xc); /* Issue phyxcer read command */
delay_ms(100); /* Wait read complete */
dm9000_reg_write(DM9000_REG_EPCR, 0x0); /* Clear phyxcer read command */
val = (dm9000_reg_read(DM9000_REG_EPDRH) << 8) | dm9000_reg_read(DM9000_REG_EPDRL);
return val;
}
/* Write a word to phyxcer */
rt_inline void dm9000_phy_write(rt_uint16_t phy_reg, rt_uint16_t value)
{
/* Fill the phyxcer register into REG_0C */
dm9000_reg_write(DM9000_REG_EPAR, DM9000_PHY | phy_reg);
/* Fill the written data into REG_0D & REG_0E */
dm9000_reg_write(DM9000_REG_EPDRL, (value & 0xff));
dm9000_reg_write(DM9000_REG_EPDRH, ((value >> 8) & 0xff));
dm9000_reg_write(DM9000_REG_EPCR, 0xa); /* Issue phyxcer write command */
delay_ms(500); /* Wait write complete */
//dm9000_reg_write(DM9000_REG_EPCR, 0x0); /* Clear phyxcer write command */
while (dm9000_reg_read(DM9000_REG_EPCR) & 0x01); /* 查寻是否执行结束 */
dm9000_reg_write(DM9000_REG_EPCR, 0x08); /* 清除写入命令 */
}
void dm9000_init()
{
unsigned short vid;
int i;
vid = (dm9000_reg_read(DM9000_VIDH) << 8) | dm9000_reg_read(DM9000_VIDL);
if(0x0a46 == vid)
printf("dm9000 device found ... \r\n");
else
{
printf("dm9000 device not found ... \r\n");
return;
}
//激活内部PHY
dm9000_reg_write(DM9000_GPCR, 0x01);
dm9000_reg_write(DM9000_GPR, 0x0);
//reset dm9000
dm9000_reg_write(DM9000_NCR, 0x3);
delayms(1);
dm9000_reg_write(DM9000_NCR, 0x0);
dm9000_reg_write(DM9000_NCR, 0x3);
delayms(1);
dm9000_reg_write(DM9000_NCR, 0x0);
//clear TX status
dm9000_reg_write(DM9000_NSR, 0x2c);
//设置mac地址
for(i = 0; i < 6; i++)
dm9000_reg_write(DM9000_PAR + i, mac_addr[i]);
dm9000_reg_write(DM9000_IMR, 0x80); /* 屏蔽所有中断，采用查询方式 */
dm9000_reg_write(DM9000_RCR, 0x31); /* 使能接收数据包功能 */
}
/*******************************************************************************
* 函数名: dm9k_reset
* 参 数: 无
* 返 回: 无
* 功 能: 对DM9000AE进行软件复位
*/
void dm9000_reset(void)
{
dm9000_reg_write(DM9000_REG_NCR, DM9000_REG_RESET); /* 对 DM9000A 进行软件重置 */
dm9k_udelay(10); /* delay 10us */
dm9000_reg_write(DM9000_REG_NCR, DM9000_REG_RESET); /* 对 DM9000A 进行软件重置 */
dm9k_udelay(10); /* delay 10us */
/* 基本记存器相关设置 */
dm9000_reg_write(DM9000_REG_IMR, DM9000_IMR_OFF); /* 开启内存自环模式 */
dm9000_reg_write(DM9000_REG_TCR2, DM9000_TCR2_SET); /* 设置 LED 显示模式1:全双工亮，半双工灭 */
/* 清除多余资讯 */
dm9000_reg_write(DM9000_REG_NSR, 0x2c);
dm9000_reg_write(DM9000_REG_TCR, 0x00);
dm9000_reg_write(DM9000_REG_ISR, 0x3f);
#ifdef DM9000A_FLOW_CONTROL
dm9000_reg_write(DM9000_REG_BPTR, DM9000_BPTR_SET); /* 半双工流控设置 */
dm9000_reg_write(DM9000_REG_FCTR, DM9000_FCTR_SET); /* 全双工流控设置 */
dm9000_reg_write(DM9000_REG_FCR, DM9000_FCR_SET); /* 开启流控设置 */
#endif
#ifdef DM9000A_UPTO_100M
/* DM9000A无此寄存器 */
dm9000_reg_write(DM9000_REG_OTCR, DM9000_OTCR_SET); /* 工作频率到 100Mhz 设置 */
#endif
#ifdef Rx_Int_enable
dm9000_reg_write(DM9000_REG_IMR, DM9000_IMR_SET); /* 开启 中断模式 */
#else
dm9000_reg_write(DM9000_REG_IMR, DM9000_IMR_OFF); /* 关闭 中断模式 */
#endif
dm9000_reg_write(DM9000_REG_RCR, DM9000_RCR_SET); /* 开启 接收工能 */
}
