static int ifxmips_mii_dev_init(struct net_device *dev)
{
int i;
struct ifxmips_mii_priv *priv;
ether_setup(dev);
printk(KERN_INFO "ifxmips_mii0: %s is up\n", dev->name);
dev->open = ifxmips_ifxmips_mii_open;
dev->stop = ifxmips_mii_release;
dev->hard_start_xmit = ifxmips_mii_tx;
dev->get_stats = ifxmips_get_stats;
dev->tx_timeout = ifxmips_mii_tx_timeout;
dev->watchdog_timeo = 10 * HZ;
memset(dev->priv, 0, sizeof(struct ifxmips_mii_priv));
priv = dev->priv;
priv->dma_device = dma_device_reserve("PPE");
if (!priv->dma_device) {
BUG();
return -ENODEV;
}
priv->dma_device->buffer_alloc = &ifxmips_etop_dma_buffer_alloc;
priv->dma_device->buffer_free = &ifxmips_etop_dma_buffer_free;
priv->dma_device->intr_handler = &dma_intr_handler;
priv->dma_device->max_rx_chan_num = 4;
for (i = 0; i < priv->dma_device->max_rx_chan_num; i++) {
priv->dma_device->rx_chan[i]->packet_size = ETHERNET_PACKET_DMA_BUFFER_SIZE;
priv->dma_device->rx_chan[i]->control = IFXMIPS_DMA_CH_ON;
}
for (i = 0; i < priv->dma_device->max_tx_chan_num; i++)
if (i == 0)
priv->dma_device->tx_chan[i]->control = IFXMIPS_DMA_CH_ON;
else
priv->dma_device->tx_chan[i]->control = IFXMIPS_DMA_CH_OFF;
dma_device_register(priv->dma_device);
printk(KERN_INFO "ifxmips_mii0: using mac=");
for (i = 0; i < 6; i++) {
dev->dev_addr[i] = mac_addr[i];
printk("%02X%c", dev->dev_addr[i], (i == 5) ? ('\n') : (':'));
}
return 0;
}
/** Register with DMA device core driver */
static int dma_setup_init(void)
{
int i, ret;
g_dma_device=dma_device_reserve("PPE");
if(!g_dma_device) {
printk(KERN_ERR "%s[%d]: Reserved with DMA core driver failed!!!\n", __func__,__LINE__);
return -ENODEV;
}
g_dma_device->buffer_alloc = &etop_dma_buffer_alloc;
g_dma_device->buffer_free = &etop_dma_buffer_free;
g_dma_device->intr_handler = &dma_intr_handler;
g_dma_device->num_rx_chan = 4;
/* one channel is enough for one network device(eth0) */
g_dma_device->num_tx_chan = 1;
g_dma_device->tx_burst_len = DMA_TX_BURST_LEN;
g_dma_device->rx_burst_len = DMA_RX_BURST_LEN;
g_dma_device->tx_endianness_mode = IFX_DMA_ENDIAN_TYPE3;
g_dma_device->rx_endianness_mode = IFX_DMA_ENDIAN_TYPE3;
/*g_dma_device->port_packet_drop_enable = IFX_DISABLE; */
for (i = 0; i < g_dma_device->num_rx_chan; i++) {
g_dma_device->rx_chan[i]->packet_size = ETH_PKT_BUF_SIZE;
g_dma_device->rx_chan[i]->control = IFX_DMA_CH_ON;
}
for (i = 0; i < g_dma_device->num_tx_chan; i++) {
if ( i == 0 ) /* TODO: Used only one DMA Tx channel */
g_dma_device->tx_chan[i]->control = IFX_DMA_CH_ON;
else
g_dma_device->tx_chan[i]->control = IFX_DMA_CH_OFF;
}
#ifdef CONFIG_NAPI_ENABLED
g_dma_device->activate_poll = eth_activate_poll;
g_dma_device->inactivate_poll = eth_inactivate_poll;
#endif
ret = dma_device_register (g_dma_device);
if ( ret != IFX_SUCCESS)
printk(KERN_ERR "%s[%d]: Register with DMA core driver Failed!!!\n", __func__,__LINE__);
return ret;
}
static void md5_init(void *ctx)
{
/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
struct md5_ctx *mctx = ctx;
unsigned long flag;
#ifndef ONLY_IN_MEM
volatile struct deu_hash_t *hash = (struct hash_t *) HASH_START;
#else
struct deu_hash_t *hash = NULL;
unsigned char *prin = NULL;
/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
hash = (struct deu_hash_t *) kmalloc(sizeof(*hash), GFP_KERNEL);
memset(hash, 0, sizeof(*hash));
prin = (unsigned char *) hash;
#endif
local_irq_save(flag);
//hexdump(mctx,sizeof(*mctx));
/*mctx->hash[0] = 0x67452301;
mctx->hash[1] = 0xefcdab89;
mctx->hash[2] = 0x98badcfe;
mctx->hash[3] = 0x10325476;
*/
mctx->byte_count = 0;
//struct deu_hash_t *hash = (struct hash_t*) HASH_START;
#ifdef DEBUG_MD5
printk("md5_init running\n");
hexdump(hash, sizeof(*hash));
#endif //DEBUG_MD5
hash->controlr.SM = 1;
hash->controlr.ALGO = 1; // 1 = md5 0 = sha1
hash->controlr.INIT = 1; // Initialize the hash operation by writing a '1' to the INIT bit.
/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
#ifdef CONFIG_CRYPTO_DEV_DANUBE_DMA
struct dma_device_info *dma_device;
volatile struct deu_dma_t *dma = (struct deu_dma_t *) DMA_CON;
int i = 0;
/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
dma_device = dma_device_reserve("DEU");
if(!dma_device) return; //-1;
ifx_deu[0].dma_device = dma_device;
dma->controlr.ALGO = 2; //10
//dma->controlr.BS = 1;
dma->controlr.EN = 1;
dma_device->num_rx_chan = 0;
dma_device->num_tx_chan = 1;
for(i = 0; i < dma_device->num_tx_chan; i++)
{
//dma_device->rx_chan[i]->packet_size=pDev->packet_size;
dma_device->tx_chan[i]->control = DANUBE_DMA_CH_ON;
}
//--------------------------------------------------------------------------------
// register the call-back functions provided by dma driver
//--------------------------------------------------------------------------------
dma_device->buffer_alloc = &deu_dma_buffer_alloc;
dma_device->buffer_free = &deu_dma_buffer_free;
dma_device->intr_handler = &deu_dma_intr_handler;
dma_device_register(dma_device);
#endif // CONFIG_CRYPTO_DEV_DANUBE_DMA
#ifdef DEBUG_MD5
hexdump(hash, sizeof(*hash));
#endif //DEBUG_MD5
local_irq_restore(flag);
}
