/**
****************************************************************************************
* @brief Proprietary initialization
* @param[in] preamble_num Preamble length
* @param[in] crc_num CRC length
* @param[in] bit_order Bit order
* @param[in] data_rate Data rate
*****************************************************************************************
*/
void prop_init(enum PROP_PREAMBLE_NUM_TYPE preamble_num, enum PROP_CRC_NUM_TYPE crc_num, enum PROP_DATA_RATE_TYPE data_rate)
{
dp_dp_SetReg(0x00, ((uint32_t)0x1 << DP_POS_DET_MODE)
| ((uint32_t)0x3 << DP_POS_RX_MODE)
| ((uint32_t)0x1 << DP_POS_TX_EN_SEL)
| ((uint32_t)0x1 << DP_POS_RX_EN_SEL)
| ((uint32_t)0x80<< DP_POS_RX_H_IDX)
| ((uint32_t)0x1 << DP_POS_PDU_LEN_SEL)
| ((uint32_t)0x1 << DP_POS_AA_SEL));
dp_dp_SetReg(0x04, ((uint32_t)0x5 << DP_POS_TX_POWER_DN_TIME)
| ((uint32_t)0x0 << DP_POS_PROP_DIRECTION_MODE)
| ((uint32_t)0x0 << DP_POS_PROP_DIRECTION_RATE)
| ((uint32_t)data_rate << DP_POS_PROP_DATA_RATE)
| ((uint32_t)preamble_num << DP_POS_PROP_PRE_NUM)
| ((uint32_t)crc_num << DP_POS_PROP_CRC_NUM));
prop_prop_SetCrWithMask(QN_PROP, PROP_MASK_BIT_ORDER, PROP_BIT_ORDER_MSB);
prop_ctrl_reset();
dma_init();
}
mp_uint_t sdcard_read_blocks(uint8_t *dest, uint32_t block_num, uint32_t num_blocks) {
// check that dest pointer is aligned on a 4-byte boundary
if (((uint32_t)dest & 3) != 0) {
return SD_ERROR;
}
// check that SD card is initialised
if (sd_handle.Instance == NULL) {
return SD_ERROR;
}
HAL_SD_ErrorTypedef err = SD_OK;
if (query_irq() == IRQ_STATE_ENABLED) {
// we must disable USB irqs to prevent MSC contention with SD card
uint32_t basepri = raise_irq_pri(IRQ_PRI_OTG_FS);
dma_init(&sd_rx_dma, DMA_STREAM_SDIO_RX, &dma_init_struct_sdio,
DMA_CHANNEL_SDIO_RX, DMA_PERIPH_TO_MEMORY, &sd_handle);
sd_handle.hdmarx = &sd_rx_dma;
err = HAL_SD_ReadBlocks_BlockNumber_DMA(&sd_handle, (uint32_t*)dest, block_num, SDCARD_BLOCK_SIZE, num_blocks);
if (err == SD_OK) {
// wait for DMA transfer to finish, with a large timeout
err = HAL_SD_CheckReadOperation(&sd_handle, 100000000);
}
dma_deinit(sd_handle.hdmarx);
sd_handle.hdmarx = NULL;
restore_irq_pri(basepri);
} else {
err = HAL_SD_ReadBlocks_BlockNumber(&sd_handle, (uint32_t*)dest, block_num, SDCARD_BLOCK_SIZE, num_blocks);
}
return err;
}
mp_uint_t sdcard_write_blocks(const uint8_t *buff, uint32_t sector, uint32_t count)
{
HAL_SD_ErrorTypedef err;
// If buffer is unaligned or located in CCM don't use DMA.
if (CCM_BUFFER(buff) || UNALIGNED_BUFFER(buff)) {
if (UNALIGNED_BUFFER(buff)) {
printf("unaligned write buf:%p count%lu \n", buff, count);
}
// This transfer has to be done in an atomic section.
mp_uint_t atomic_state = MICROPY_BEGIN_ATOMIC_SECTION();
err = HAL_SD_WriteBlocks(&SDHandle, (uint32_t*)buff,
sector * SDCARD_BLOCK_SIZE, SDCARD_BLOCK_SIZE, count);
MICROPY_END_ATOMIC_SECTION(atomic_state);
} else {
// Disable USB IRQ to prevent FatFS/MSC contention
HAL_NVIC_DisableIRQ(OTG_FS_IRQn); __DSB(); __ISB();
dma_init(SDIO_TXRX_STREAM, SDIO_TXRX_CHANNEL, DMA_MEMORY_TO_PERIPH);
err = HAL_SD_WriteBlocks_DMA(&SDHandle, (uint32_t*)buff,
sector * SDCARD_BLOCK_SIZE, SDCARD_BLOCK_SIZE, count);
if (err == SD_OK) {
err = HAL_SD_CheckWriteOperation(&SDHandle, SDIO_TIMEOUT);
}
if (err != SD_OK) {
printf("write buf:%p addr:%lu count%lu error:%d\n", buff, sector, count, err);
}
dma_deinit();
HAL_NVIC_EnableIRQ(OTG_FS_IRQn);
}
return (err != SD_OK);
}
int main(void) {
if (PM->RCAUSE.reg & (PM_RCAUSE_POR | PM_RCAUSE_BOD12 | PM_RCAUSE_BOD33)) {
// On powerup, force a clean reset of the MT7620
pin_low(PIN_SOC_RST);
pin_out(PIN_SOC_RST);
// turn off 3.3V to SoC
pin_low(PIN_SOC_PWR);
pin_out(PIN_SOC_PWR);
// pull 1.8V low
pin_low(PIN_18_V);
pin_out(PIN_18_V);
clock_init_crystal(GCLK_SYSTEM, GCLK_32K);
timer_clock_enable(TC_BOOT);
// hold everything low
boot_delay_ms(50); // power off for 50ms
pin_high(PIN_SOC_PWR);
boot_delay_ms(2); // 2ms until 1.8 rail comes on
pin_high(PIN_18_V);
boot_delay_ms(50); // 50ms before soc rst comes on
} else {
clock_init_crystal(GCLK_SYSTEM, GCLK_32K);
}
pin_mux(PIN_USB_DM);
pin_mux(PIN_USB_DP);
usb_init();
usb_attach();
NVIC_SetPriority(USB_IRQn, 0xff);
pin_high(PIN_LED);
pin_out(PIN_LED);
pin_in(PIN_SOC_RST);
pin_high(PIN_SOC_PWR);
pin_out(PIN_SOC_PWR);
pin_low(PORT_A.power);
pin_out(PORT_A.power);
pin_low(PORT_B.power);
pin_out(PORT_B.power);
pin_pull_up(PIN_BRIDGE_CS);
pin_pull_up(PIN_FLASH_CS);
pin_pull_up(PIN_SERIAL_TX);
pin_pull_up(PIN_SERIAL_RX);
dma_init();
NVIC_EnableIRQ(DMAC_IRQn);
NVIC_SetPriority(DMAC_IRQn, 0xff);
eic_init();
NVIC_EnableIRQ(EIC_IRQn);
NVIC_SetPriority(EIC_IRQn, 0xff);
evsys_init();
NVIC_EnableIRQ(EVSYS_IRQn);
NVIC_SetPriority(EVSYS_IRQn, 0);
adc_init(GCLK_SYSTEM, ADC_REFCTRL_REFSEL_INTVCC1);
dac_init(GCLK_32K);
bridge_init();
port_init(&port_a, 1, &PORT_A, GCLK_PORT_A,
TCC_PORT_A, DMA_PORT_A_TX, DMA_PORT_A_RX);
port_init(&port_b, 2, &PORT_B, GCLK_PORT_B,
TCC_PORT_B, DMA_PORT_B_TX, DMA_PORT_B_RX);
__enable_irq();
SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk;
init_systick();
while (1) { __WFI(); }
}
int main()
{
struct zynq_ipif ipif;
int i, test = 0x01020304;
char cmd[256];
int ret = 0;
for (i = 0; i < ARRAY_SIZE(test_buf[0]); i++)
test_buf[0][i] = test + i * 0x04040404;
zynq_ipif_init(&ipif, &ipif_config);
reg_write(regmap, 0x0, 0x1f);
reg_write(regmap, 0x0, 0x0);
reg_write(regmap, 0x1c, 10000);
dma_init(&ipif.dma[0], &dma_config[0]);
dma_init(&ipif.dma[2], &dma_config[2]);
zynq_ipif_prepare_dma_share(&ipif.dma_share);
/* Fill the ring buffer as the initialization */
dma_write_buffer(&ipif.dma[0], (u8 *)test_buf[0], BUF_SIZE);
dma_enable(&ipif.dma[0], 1);
dma_enable(&ipif.dma[2], 1);
reg_write(regmap, 0x4, 0x1f);
reg_write(regmap, 0x8, 0x6667);
sleep(2);
reg_write(regmap, 0x8, 0x0);
reg_write(regmap, 0x4, 0x0);
dma_enable(&ipif.dma[0], 0);
dma_enable(&ipif.dma[2], 0);
zynq_ipif_unprepare_dma_share(&ipif.dma_share);
dma_exit(&ipif.dma[0]);
dma_exit(&ipif.dma[2]);
for (i = 0; i < ARRAY_SIZE(test_buf[0]); i++)
if (test_buf[0][i] != test_buf[1][i])
ret++;
printf("test %s, %d, %d\n", ret ? "failed" : "succeed",
ipif.dma[0].io_ptr, ipif.dma[2].io_ptr);
zynq_ipif_exit(&ipif);
printf("dumping results...\n");
sprintf(cmd, "rm -f dump");
system(cmd);
for (i = 0; i < ARRAY_SIZE(test_buf[0]); i++) {
sprintf(cmd, "echo '%x - %x' >> dump",
test_buf[0][i], test_buf[1][i]);
system(cmd);
}
return 0;
}
void play_music(unsigned int start_addr, unsigned int len)
{
dma_init(start_addr, len);
AC_GLBCTRL |= 2 << 12;
DMACConfiguration = 0x01;
}
void pf_hci_transport_init(void)
{
#ifdef _RTK8723_INTERFACE_INFO_
#ifndef _SUPPORT_3BITS_HCI_SELECTION_
POW_OPTION_AND_32K_CTRL_S_TYPE pow_option;
BTON_INTERFACE_CTRL_REG_S_TYPE bton_interface_info;
pow_option.d32 = VENDOR_READ(BTON_POW_OPTION_AND_32K_CTRL);
bton_interface_info.d32 = VENDOR_READ(BTON_INTERFACE_CTRL_REG);
/* to fixed RTL8723A bton_interface_info.b.bt_fen_sts BUG */
if (bton_interface_info.b.hci_uart_fen_sts)
{
bton_interface_info.b.bt_fen_sts = 1;
}
g_fun_interface_info.b.hci_sel = pow_option.b.hci_selection;
g_fun_interface_info.b.bt_fun_sts= bton_interface_info.b.bt_fen_sts;
#ifdef _CCH_RETENTION_FLOW_FOR_DLPS_
if(sleep_mode_param.dlps_restore_flow == FALSE)
#endif
{
RT_BT_LOG(BLUE,PACKAGE_TO_HCI,1,g_fun_interface_info.b.hci_sel);
}
switch (pow_option.b.hci_selection)
{
//case RTK8723_S:
case PACKAGE_SDIO_UART:
#ifndef _BT_ONLY_
case PACKAGE_PCIE_UART:
#endif
g_fun_interface_info.b.bt_interface = UART_INTERFACE;
#ifndef _8821A_BTON_DESIGN_
g_fun_interface_info.b.bt_fun_sts= bton_interface_info.b.bt_fen_sts;
g_fun_interface_info.b.gps_fun_sts = 0;
#endif
//RT_BT_LOG(BLUE,RTK8723_SDIO_UART,1,pow_option.b.hci_selection);
break;
//case RTK8723_U:
case PACKAGE_USB_USB:
g_fun_interface_info.b.bt_interface = USB_INTERFACE;
#ifndef _8821A_BTON_DESIGN_
g_fun_interface_info.b.bt_fun_sts= bton_interface_info.b.bt_fen_sts;
g_fun_interface_info.b.gps_fun_sts = bton_interface_info.b.usb_gps_fen_sts;
g_fun_interface_info.b.gps_interface = USB_INTERFACE;
#endif
//RT_BT_LOG(BLUE,RTK8723_USB_MULTI,1,pow_option.b.hci_selection);
break;
#ifndef _REMOVE_HCI_PCIE_
#if !defined(_RTL8703B_SPECIFIC_) && !defined(_RTL8822B_SPECIFIC_)
case RTK8723_EE:
g_fun_interface_info.b.bt_interface = PCIE_INTERFACE;
#ifndef _8821A_BTON_DESIGN_
g_fun_interface_info.b.bt_fun_sts= bton_interface_info.b.bt_fen_sts;
g_fun_interface_info.b.gps_fun_sts = bton_interface_info.b.pcie_gps_fen_sts;
g_fun_interface_info.b.gps_interface = PCIE_INTERFACE;
#endif
//RT_BT_LOG(BLUE,RTK8723_PCIE_MULTI,1,pow_option.b.hci_selection);
break;
#else
case RTK8822B_ME:
g_fun_interface_info.b.bt_interface = USB_INTERFACE;
break;
#endif
#endif
#if defined(_BT_ONLY_) || (!defined(_RTL8703B_SPECIFIC_) && !defined(_RTL8822B_SPECIFIC_))
//case RTK8723_E:
case PACKAGE_PCIE_USB:
g_fun_interface_info.b.bt_interface = USB_INTERFACE;
#ifndef _8821A_BTON_DESIGN_
g_fun_interface_info.b.bt_fun_sts= bton_interface_info.b.bt_fen_sts;
g_fun_interface_info.b.gps_fun_sts = bton_interface_info.b.pcie_gps_fen_sts;
g_fun_interface_info.b.gps_interface = PCIE_INTERFACE;
#endif
//RT_BT_LOG(BLUE,RTK8723_PCIE_USB,1,pow_option.b.hci_selection);
break;
#endif
default:
break;
}
#else
#if defined(_BT_ONLY_)//dape mark since seems all ruled by _BT_ONLY ||!defined(_SUPPORT_INFO_FROM_SYSTEM_ON_)
POW_OPTION_AND_32K_CTRL_S_TYPE pow_option;
BTON_INTERFACE_CTRL_REG_S_TYPE bton_interface_info;
pow_option.d32 = VENDOR_READ(BTON_POW_OPTION_AND_32K_CTRL);
bton_interface_info.d32 = VENDOR_READ(BTON_INTERFACE_CTRL_REG);
g_fun_interface_info.b.hci_sel = pow_option.b.hci_selection;
#else
//PAGE0_REG_0xF5_BYTE_READ_S page0_hci_sel;
BTON_INTERFACE_CTRL_REG_S_TYPE bton_interface_info;
//page0_hci_sel.d8 = RD_8BIT_COMBO_SYSON_IO(PAGE0_REG_0xF5);
bton_interface_info.d32 = VENDOR_READ(BTON_INTERFACE_CTRL_REG);
//g_fun_interface_info.b.hci_sel = page0_hci_sel.b.hci_selection;
g_fun_interface_info.b.hci_sel = getfinalhci();
#endif
/* to fixed RTL8723A bton_interface_info.b.bt_fen_sts BUG */
if (bton_interface_info.b.hci_uart_fen_sts)
{
bton_interface_info.b.bt_fen_sts = 1;
}
g_fun_interface_info.b.bt_fun_sts= bton_interface_info.b.bt_fen_sts;
#ifdef _CCH_RETENTION_FLOW_FOR_DLPS_
if(sleep_mode_param.dlps_restore_flow == FALSE)
#endif
{
RT_BT_LOG(BLUE,PACKAGE_TO_HCI,1,g_fun_interface_info.b.hci_sel);
}
switch (g_fun_interface_info.b.hci_sel)
{
case PACKAGE_SDIO_UART:
case PACKAGE_PCIE_UART:
#ifdef _RTL8822B_SPECIFIC_
case PACKAGE_MPCIE_UART:
#endif
g_fun_interface_info.b.bt_interface = UART_INTERFACE;
#ifndef _8821A_BTON_DESIGN_
g_fun_interface_info.b.bt_fun_sts= bton_interface_info.b.bt_fen_sts;
g_fun_interface_info.b.gps_fun_sts = 0;
#endif
//RT_BT_LOG(BLUE,RTK8723_SDIO_UART,1,pow_option.b.hci_selection);
break;
case PACKAGE_USB_USB:
#ifdef _RTL8822B_SPECIFIC_
case PACKAGE_MPCIE_USB:
#endif
case PACKAGE_PCIE_USB:
g_fun_interface_info.b.bt_interface = USB_INTERFACE;
#ifndef _8821A_BTON_DESIGN_
g_fun_interface_info.b.bt_fun_sts= bton_interface_info.b.bt_fen_sts;
g_fun_interface_info.b.gps_fun_sts = bton_interface_info.b.usb_gps_fen_sts;
g_fun_interface_info.b.gps_interface = USB_INTERFACE;
#endif
//RT_BT_LOG(BLUE,RTK8723_USB_MULTI,1,pow_option.b.hci_selection);
break;
/*
#if defined(_BT_ONLY_)||!defined(_RTL8703B_SPECIFIC_)
case RTK8723_E:
g_fun_interface_info.b.bt_interface = USB_INTERFACE;
#ifndef _8821A_BTON_DESIGN_
g_fun_interface_info.b.bt_fun_sts= bton_interface_info.b.bt_fen_sts;
g_fun_interface_info.b.gps_fun_sts = bton_interface_info.b.pcie_gps_fen_sts;
g_fun_interface_info.b.gps_interface = PCIE_INTERFACE;
#endif
//RT_BT_LOG(BLUE,RTK8723_PCIE_USB,1,pow_option.b.hci_selection);
break;
#endif
*/
default:
RT_BT_LOG(RED,PACKAGE_ERROR_SELECTION,0,0);
break;
}
#endif /* end of #else _SUPPORT_3BITS_HCI_SELECTION_ */
#ifdef _CCH_RETENTION_FLOW_FOR_DLPS_
if(sleep_mode_param.dlps_restore_flow == FALSE)
#endif
{
#ifndef _8821A_BTON_DESIGN_
RT_BT_LOG(BLUE,RTK8723_INTERFACE_INFO,4,g_fun_interface_info.b.bt_fun_sts,
g_fun_interface_info.b.bt_interface,
g_fun_interface_info.b.gps_fun_sts,
g_fun_interface_info.b.gps_interface);
#else
RT_BT_LOG(BLUE,RTK8723_INTERFACE_INFO2,5,g_fun_interface_info.b.bt_fun_sts,
g_fun_interface_info.b.bt_interface,
bton_interface_info.b.bt_fen_sts,
bton_interface_info.b.hci_uart_fen_sts,
bton_interface_info.b.gpio_reset_rf_sts);
#endif
}
if (bton_interface_info.b.hci_uart_fen_sts)
{
g_fun_interface_info.b.bt_interface = UART_INTERFACE;
// RT_BT_LOG(BLUE,DATA_UART_EN,0,0);
}
#else
#ifdef _ENABLE_UART_DMA_
g_fun_interface_info.b.bt_interface = UART_INTERFACE;
#elif _ENABLE_PCIE_DMA_
#ifndef _REMOVE_HCI_PCIE_
g_fun_interface_info.b.bt_interface = PCIE_INTERFACE;
#endif
#else
g_fun_interface_info.b.bt_interface = USB_INTERFACE;
#endif
#endif
/* Added by Wallice Su for USB LPM. 2012/03/01 */
/* be ware of besl or hird */
// 0xFE65[3]: BESEL enable
// 0xFE65[4]: Baseline BESL value
// 0xFE65[5]: deep BESL value
//RT_BT_LOG(BLUE, MSG_USBLPM_REG,1,bton_USB_LPM_reg.d32);
if ((g_fun_interface_info.b.bt_interface == USB_INTERFACE))
{
#ifdef _SUPPORT_USB_LOG_ENABLE_
// force to NYET first
g_usb_misc = otp_str_data.USB_misc;
#endif
//RT_BT_LOG(YELLOW, YL_DBG_HEX_1, 1,g_usb_misc);
BTON_USB_LPM_REG_S_TYPE bton_USB_LPM_reg;
bton_USB_LPM_reg.d32 = 0x0;
#ifndef _SUPPORT_POLLING_BASED_LPM_L1_
if (otp_str_data.USB_LPM_Allow == 0x1)
{
bton_USB_LPM_reg.b.LPM_Allow = 1;
}
#else
g_lpm_poll_control_s = (LPM_POLL_CONTROL)(otp_str_data.USB_LPM_Control);
bton_USB_LPM_reg.b.LPM_Allow = g_lpm_poll_control_s.b.lpm_en;
#ifdef _SUPPORT_FW_INDIRECT_READ_SIE_
USB_SIE_0x65_REG_S_TYPE sieReg0x65;
sieReg0x65.d8 = (UINT8)safe_indirect_read_sie(READ_SIE_BYTE, SIE_REG_0x65);
if( sieReg0x65.b.besl_en != 0)
{ // BESL
if(sieReg0x65.b.baseline_besl_valid != 0 )
{ // set baseline BESL to bton reg
USB_SIE_0x7A_REG_S_TYPE sieReg0x7A;
sieReg0x7A.d8 = safe_indirect_read_sie(READ_SIE_BYTE, SIE_REG_0x7A);
*((unsigned char *)&bton_USB_LPM_reg) = sieReg0x7A.b.baseline_besl_value;//from wifi efuse
}
}
else
#endif
#endif
{ // HIRD
*((unsigned char *)&bton_USB_LPM_reg) = otp_str_data.USB_LPM_HIRDBESL_Thrd;// from bt efuse
}
VENDOR_WRITE(BTON_USB_LPM, bton_USB_LPM_reg.d32);// for hird
#ifdef _CCH_RETENTION_FLOW_FOR_DLPS_
if(sleep_mode_param.dlps_restore_flow == FALSE)
#endif
{
RT_BT_LOG(BLUE, MSG_USBLPM_REG,1,bton_USB_LPM_reg.d32);
}
}
/* End Added by Wallice Su for USB LPM. 2012/03/01 */
g_baudRate = otp_str_data.SYS_hci_uart_baudrate;
#ifdef _RTK8723_UART_INIT_
// New EFUSE parameters
*(UINT32*)&g_data_uart_settings = otp_str_data.rtl8723_data_uart_settings;
#ifdef _UART_H5
*(UINT32*)&g_data_uart_settings_2 = otp_str_data.rtl8723_data_uart_settings_2;
*(UINT32*)&g_data_uart_settings_3 = otp_str_data.rtl8723_data_uart_settings_3;
#ifdef _UART_BAUD_ESTIMATE_
g_efuse_baud_est_setting_1.d16 = otp_str_data.efuse_baud_est_setting_1_d16;
g_efuse_baud_est_setting_2.d16 = otp_str_data.efuse_baud_est_setting_2_d16;
g_efuse_baud_est_setting_3.d16 = otp_str_data.efuse_baud_est_setting_3_d16;
g_efuse_baud_est_setting_4.d16 = otp_str_data.efuse_baud_est_setting_4_d16;
#endif
#ifdef _UART_H5_FPGA_EFUSE_FORCE
// TODO: To be included into EFUSE
g_data_uart_settings.baud_default_en = 0;
#ifdef _YL_H5_MODE_ENABLE
g_data_uart_settings_3.parity_en = 1; // 1b
g_data_uart_settings_3.parity_even = 1; // 1b
g_data_uart_settings_3.hw_fctrl_on = 0; // 1b
#else
/* H4 Mode EFUSE Setting */
g_data_uart_settings_3.parity_en = 0; // 1b
g_data_uart_settings_3.parity_even = 0; // 1b
#ifdef _IN_BQB_
g_data_uart_settings_3.hw_fctrl_on = 0; // 1b
#else
g_data_uart_settings_3.hw_fctrl_on = 1; // 1b
#endif
#endif
g_data_uart_settings_3.long_break_duration = 3; // 3b; 2^(x)*10ms
#ifdef _YL_H5_MODE_ENABLE
g_data_uart_settings_2.h5_en = 1; // 1b
#else
/* H4 Mode EFUSE Setting */
g_data_uart_settings_2.h5_en = 0; // 1b
#endif
g_data_uart_settings_3.h5_poll_wake_duration = 5; // 3b; 7: persistent poll; else: 2^(2x)*10ms
g_data_uart_settings_3.h5_retry_alarm_opt = H5_WAKEUP_OPT_NONE; // 2b; 0: nothing, 1: sent short break, 2: send long break; 3: poll_wake
g_data_uart_settings_3.h5_retry_fail_opt = H5_WAKEUP_OPT_NONE; // 2b; 0: nothing, 1: sent short break, 2: send long break; 3: poll_wake
g_data_uart_settings_3.h5_lowpow_wakeup_opt = H5_WAKEUP_OPT_NONE; // 2b; if(sleep_msg_state==1 && RX is to be send to HCI DMA), 0: nothing, 1: sent short break, 2: send long break; 3: poll_wake
#ifdef _YL_H5_FORCE_SLEEP_MSG_EN
g_data_uart_settings_3.h5_lowpow_sleep_msg_en = 1; // 1b; 1: send_sleep_msg() before go to sleep
#else
g_data_uart_settings_3.h5_lowpow_sleep_msg_en = 0; // 1b; 1: send_sleep_msg() before go to sleep
#endif
#ifdef _YL_H5_FORCE_SCO_REL
g_data_uart_settings_3.h5_scounrel_force_en = 1; // required? 1b
g_data_uart_settings_3.h5_scounrel_force_value = 0; // required? 1b; valid when force_en = 1, 0: reliable, 1: unreliable
#else
g_data_uart_settings_3.h5_scounrel_force_en = 0; // 1b
g_data_uart_settings_3.h5_scounrel_force_value = 0; // 1b; valid when force_en = 1, 0: reliable, 1: unreliable
#endif
g_data_uart_settings_3.h5_resend_time_adapt_en = 1; // 1b; enable retry_limit adaption according to baudrate and g_hci_uart_resend_target
// should not be enabled when "baud_det_en & (det_wait_en = 0 | det_timeout_en)" ==> Baudrate may be strange
g_data_uart_settings_3.h5_resend_time_adapt_max = 5; // 3b; the maximum adapted resend_to_val;
g_data_uart_settings_3.h5_resend_time_adapt_min = 3; // 3b; the minimum adapted resend_to_val
g_data_uart_settings_3.h5_resend_target = 0; // 2b; valid when resend_time_adapt_en = 1; target resend timing for adaption = 250ms/2^x
g_data_uart_settings_3.h5_retry_limit_adapt_en = 1; // 1b; valid when resend_time_adapt_en = 1; enable retry_limit adaption according baud and resend_to_val
g_data_uart_settings_3.h5_trx_active_mask_opt = 0; // 1b;
#ifdef _YL_H4_FORCE_ERR_EVT_DLYW1C_EN
g_data_uart_settings_3.err_send_event_delayw1c_opt = _YL_H4_FORCE_ERR_EVT_DLYW1C_VALUE; // 3b
#else
g_data_uart_settings_3.err_send_event_delayw1c_opt = 0; // 3b
#endif
g_data_uart_settings_2.h5_host_to_val = 0; // 2b; HCI TX abort timeout(to avoid hangup bugs); 2^(2x+10) characters; 3: never timeout
g_data_uart_settings_2.h5_active_sync = 0; // 1b
#ifdef _YL_H5_FORCE_ACTIVE_IGNORE_SYNC
g_data_uart_settings_2.h5_ignore_sync = 1; // 1b; 1: ignore SYNC at ACTIVE STATE
#else
g_data_uart_settings_2.h5_ignore_sync = 0; // 1b; 1: ignore SYNC at ACTIVE STATE
#endif
g_data_uart_settings_2.h5_force_oof_ctrl = 0; // 1b; force out-of-frame software flow control ON (XON/XOFF)
g_data_uart_settings_2.h5_force_no_oof = 0; // 1b; force out-of-frame software flow control OFF (XON/XOFF)
g_data_uart_settings_2.h5_retry_limit = 7; // 3b; LinkFailure: 2^(x+1) retries; LinkAlarm: 2^(x) retries
g_data_uart_settings_2.h5_resend_to_val = 3; // 3b; 0~5; resend(retry) period: 2^(x+9) T_char; 115200: T_char ~ 95.5us; 921600: T_char ~ 11.9us
g_data_uart_settings_2.h5_sync_to_val = 3; // 3b; 0~4; link establishment period; 2^(2x+6) T_char; 115200: T_char ~ 95.5us; 921600: T_char ~ 11.9us
g_data_uart_settings_2.h5_ack_to_val = 0; // 2b; 0~3; pure ACK wait time: 2^(2x+2) T_char; 115200: T_char ~ 95.5us; 921600: T_char ~ 11.9us
g_data_uart_settings_2.h5_wake_to_val = 1; // 2b; WAKEUP period; 2^(2x+2) T_char; 115200: T_char ~ 95.5us; 921600: T_char ~ 11.9us
g_data_uart_settings_2.h5_int_en = (BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6|BIT7 |BIT9); // 16b; No PARK_OK_INT
// #ifdef _YL_H5_FORCE_LINKRESET_RESTART
// g_data_uart_settings_2.h5_linkreset_restart = 1;
// #else
// g_data_uart_settings_2.h5_linkreset_restart = 0;
// #endif
g_data_uart_settings_2.h5_lowpow_sleep_msg_wait_en = 0; // 1b; valid when h5_lowpow_sleep_msg_en = 1; 0: exit hci_uart_h5_send_sleep_msg_wait_done() without waiting done
#ifdef _YL_H5_FORCE_RETRY_NOT_CLEAR_WHEN_TRX
g_data_uart_settings_2.h5_retry_state_clr_when_trx = 0; // 1b;
#else
g_data_uart_settings_2.h5_retry_state_clr_when_trx = 1; // 1b;
#endif
g_data_uart_settings.err_event_err_code_opt = 0; // 1b;
#ifdef _YL_H5_FORCE_LINKFAIL_CLR_UNACK
g_data_uart_settings.h5_linkfail_clr_unack = 1; // 1b;
#else
g_data_uart_settings.h5_linkfail_clr_unack = 0; // 1b;
#endif
#ifdef _8821A_BTON_DESIGN_
g_data_uart_settings.hci_uart_mcr_rtsn = 0;
#endif
#ifdef _YL_H5_FORCE_BAUD_DETECT
// hci_uart_man_sram.hci_uart_man_sram_valid_signature = 0;
g_data_uart_settings.baud_det_en = 0;
g_data_uart_settings.baud_mon_log_en = 1;
g_data_uart_settings.baud_est_baud_det_fail_redet_en = 1;
g_data_uart_settings.baud_est_use_original_buad_det_only = 0;
g_data_uart_settings.baud_est_use_original_buad_det_once = 1;
g_data_uart_settings.baud_record_at_rx_vendor_sync = 0; // ????
g_data_uart_settings.baud_est_baud_det_trial_redet_en = 0;
g_data_uart_settings.baud_est_delay_before_h5_state_check = 1;
g_data_uart_settings.buad_est_bypass_mon_valid_check = 1;
g_data_uart_settings.baud_record_at_h5_link_est = 0;
g_data_uart_settings.baud_det_init_with_reset = 1;
g_data_uart_settings.baud_est_wr_bton_en_at_h5link_uartsync = 0;
g_data_uart_settings.h5_sign_linkrst_signature = 1;
g_data_uart_settings.h5_linkrst_sign_fw_trig_wdg = 0;
g_data_uart_settings.baud_est_stop_at_rx_vendor_sync = 1;
g_data_uart_settings.baud_mon_resume_every_log = 1;
g_efuse_baud_est_setting_1.baud_mon_en = 1;
g_efuse_baud_est_setting_1.baud_est_en = 1;
g_efuse_baud_est_setting_1.baud_recov_at_fw_trig_wdg = 1;
if (_YL_H5_FORCE_BAUD_DETECT_MODE==1)
{
g_efuse_baud_est_setting_1.baud_recov_at_h5_linkreset = 0;
}
else
{
g_efuse_baud_est_setting_1.baud_recov_at_h5_linkreset = 1;
}
g_efuse_baud_est_setting_1.baud_recov_at_reinit = 0;
g_efuse_baud_est_setting_1.baud_recov_at_other_wdg = 0;
if (_YL_H5_FORCE_BAUD_DETECT_MODE==1)
{
g_efuse_baud_est_setting_1.baud_recov_at_state_stop_postset = 0;
}
else
{
g_efuse_baud_est_setting_1.baud_recov_at_state_stop_postset = 1;
}
g_efuse_baud_est_setting_1.baud_recov_at_state_stop_preset = 0;
if (_YL_H5_FORCE_BAUD_DETECT_MODE==1)
{
g_efuse_baud_est_setting_1.baud_est_restart_at_h5_linkreset = 1;
}
else
{
g_efuse_baud_est_setting_1.baud_est_restart_at_h5_linkreset = 0;
}
g_efuse_baud_est_setting_1.exec_baud_est_init_post_at_reinit = 1;
g_efuse_baud_est_setting_1.baud_est_update_at_h5_initialized = 1;
g_efuse_baud_est_setting_1.baud_est_restart_at_baud_sram_recov_0 = 1;
g_efuse_baud_est_setting_1.baud_est_ovsrx8_grid = 0;
g_efuse_baud_est_setting_1.min_low_falling_udfl_th_opt = 2;
g_efuse_baud_est_setting_2.baud_est_falling_cnt_th_1st = 3;
g_efuse_baud_est_setting_2.baud_est_combine_opt = 1;
g_efuse_baud_est_setting_2.baud_est_combine_opt_both_udfl = 1;
g_efuse_baud_est_setting_2.min_falling_ovfl_chg_to_min_low = 1;
g_efuse_baud_est_setting_2.min_low_udfl_chg_to_min_falling = 1;
g_efuse_baud_est_setting_2.ignore_invalid_falling_low_ratio = 0;
g_efuse_baud_est_setting_2.est_bias_value = 0;
g_efuse_baud_est_setting_2.est_bias_sign = 0;
g_efuse_baud_est_setting_2.baud_det_finetune_by_exhaust_est = 0;
g_efuse_baud_est_setting_3.det_allow_table = 0xFFF;
g_efuse_baud_est_setting_3.baud_est_ovsr_low_bound = 4;
g_efuse_baud_est_setting_3.w1c_at_fallint_cnt_intr_end = 1;
g_efuse_baud_est_setting_4.baud_est_opt = _YL_H5_FORCE_BAUD_DETECT_OPT;
g_efuse_baud_est_setting_4.det_err_chg_to_est_th = 3;
g_efuse_baud_est_setting_4.baud_est_delay = 2;
g_efuse_baud_est_setting_4.hci_uart_baud_est_h5init_retry_th = 3;
g_efuse_baud_est_setting_4.baud_est_by_low_period_at_h5_initialized = 0;
g_efuse_baud_est_setting_4.baud_est_falling_cnt_th_2nd = 14;
#endif // End of #ifdef _YL_H5_FORCE_BAUD_DETECT
#endif // End of #ifdef _UART_H5_EFUSE_FORCE
#endif // End of #ifdef _UART_H5
#endif
#if defined(_8821A_NEW_UART_DESIGN_) && defined(_RTK8723_UART_INIT_)
// g_uart_clk = _HCI_UART_CLK_FREQ;
#else
g_uart_clk = otp_str_data.crystal_clk;
#endif
#ifdef _CCH_RETENTION_FLOW_FOR_DLPS_
if(sleep_mode_param.dlps_restore_flow == FALSE)
#endif
{
dma_init(INIT_FIRST);
}
#ifdef _CCH_RETENTION_FLOW_FOR_DLPS_
else
{
dma_init(INIT_FROM_DLPS);
}
#endif
}
/**
****************************************************************************************
* @brief Read ADC conversion result
* @param[in] S ADC read configuration, contains work mode, trigger source, start/end channel
* @param[in] buf ADC result buffer
* @param[in] samples Sample number
* @param[in] callback callback after all the samples conversion finish
* @description
* This function is used to read ADC specified channel conversion result.
* @note
* When use scaning mode, only can select first 6 channel (AIN0,AIN1,AIN2,AIN3,AIN01,AIN23)
*****************************************************************************************
*/
void adc_read(const adc_read_configuration *S, int16_t *buf, uint32_t samples, void (*callback)(void))
{
uint32_t reg;
uint32_t mask;
int i = 0;
adc_env.mode = S->mode;
adc_env.trig_src = S->trig_src;
adc_env.start_ch = S->start_ch;
adc_env.end_ch = S->end_ch;
adc_env.bufptr = buf;
adc_env.samples = samples;
adc_env.callback = callback;
// Busrt scan mode, need read all of the channel after once trigger
if (S->mode == SINGLE_SCAN_MOD) {
scan_ch_num = S->end_ch - S->start_ch + 1;
}
else {
scan_ch_num = 1;
}
#if (CONFIG_ADC_ENABLE_INTERRUPT==FALSE) && (ADC_DMA_EN==TRUE)
dma_init();
// samples*2 <= 0x7FF
dma_rx(DMA_TRANS_HALF_WORD, DMA_ADC, (uint32_t)buf, samples*2, callback);
#endif
mask = ADC_MASK_SCAN_CH_START
| ADC_MASK_SCAN_CH_END
| ADC_MASK_SCAN_INTV
| ADC_MASK_SCAN_EN
| ADC_MASK_SINGLE_EN
| ADC_MASK_START_SEL
| ADC_MASK_SFT_START
| ADC_MASK_POW_UP_DLY
| ADC_MASK_POW_DN_CTRL
| ADC_MASK_ADC_EN;
reg = (S->start_ch << ADC_POS_SCAN_CH_START) // set adc channel, or set scan start channel
| (S->end_ch << ADC_POS_SCAN_CH_END) // set scan end channel
| (0x03 << ADC_POS_SCAN_INTV) // should not be set to 0 at single mode
| (S->trig_src << ADC_POS_START_SEL) // select ADC trigger source
| (0x3F << ADC_POS_POW_UP_DLY) // power up delay
| ADC_MASK_POW_DN_CTRL // enable power down control by hardware, only work in single mode
| ADC_MASK_ADC_EN; // enable ADC
if ((S->mode == SINGLE_SCAN_MOD) || (S->mode == SINGLE_MOD)) { // default is continue
reg |= ADC_MASK_SINGLE_EN; // single mode enable
}
if ((S->mode == SINGLE_SCAN_MOD) || (S->mode == CONTINUE_SCAN_MOD)) { // default is not scan
reg |= ADC_MASK_SCAN_EN; // scan mode enable
}
adc_adc_SetADC0WithMask(QN_ADC, mask, reg);
if (adc_env.trig_src == ADC_TRIG_SOFT) {
// SFT_START 0->1 trigger ADC conversion
adc_adc_SetADC0WithMask(QN_ADC, ADC_MASK_SFT_START, MASK_ENABLE);
}
#if CONFIG_ADC_ENABLE_INTERRUPT==TRUE
dev_prevent_sleep(PM_MASK_ADC_ACTIVE_BIT);
#elif (CONFIG_ADC_ENABLE_INTERRUPT==FALSE) && (ADC_DMA_EN==FALSE)
// polling
while(samples > 0)
{
for (i = 0; ((i < scan_ch_num)&&(samples)); i++) {
while(!(adc_adc_GetSR(QN_ADC) & ADC_MASK_DAT_RDY_IF));
*buf++ = adc_adc_GetDATA(QN_ADC);
samples--;
}
// Single mode enable, software trigger
if ( (samples) && (adc_env.trig_src == ADC_TRIG_SOFT) && ((S->mode == SINGLE_SCAN_MOD)||(S->mode == SINGLE_MOD))) {
// SFT_START 0->1 trigger ADC conversion
adc_adc_SetADC0WithMask(QN_ADC, ADC_MASK_SFT_START, MASK_DISABLE);
adc_adc_SetADC0WithMask(QN_ADC, ADC_MASK_SFT_START, MASK_ENABLE);
}
}
// disable ADC
adc_enable(MASK_DISABLE);
adc_clean_fifo();
#if ADC_CALLBACK_EN==TRUE
if (callback != NULL)
{
callback();
}
#endif
#endif
}
test_mockable int main(void)
{
/*
* Pre-initialization (pre-verified boot) stage. Initialization at
* this level should do as little as possible, because verified boot
* may need to jump to another image, which will repeat this
* initialization. In particular, modules should NOT enable
* interrupts.
*/
#ifdef CONFIG_BOARD_PRE_INIT
board_config_pre_init();
#endif
#ifdef CONFIG_MPU
mpu_pre_init();
#endif
/* Configure the pin multiplexers and GPIOs */
jtag_pre_init();
gpio_pre_init();
#ifdef CONFIG_BOARD_POST_GPIO_INIT
board_config_post_gpio_init();
#endif
/*
* Initialize interrupts, but don't enable any of them. Note that
* task scheduling is not enabled until task_start() below.
*/
task_pre_init();
/*
* Initialize the system module. This enables the hibernate clock
* source we need to calibrate the internal oscillator.
*/
system_pre_init();
system_common_pre_init();
#ifdef CONFIG_FLASH
/*
* Initialize flash and apply write protect if necessary. Requires
* the reset flags calculated by system initialization.
*/
flash_pre_init();
#endif
/* Set the CPU clocks / PLLs. System is now running at full speed. */
clock_init();
/*
* Initialize timer. Everything after this can be benchmarked.
* get_time() and udelay() may now be used. usleep() requires task
* scheduling, so cannot be used yet. Note that interrupts declared
* via DECLARE_IRQ() call timer routines when profiling is enabled, so
* timer init() must be before uart_init().
*/
timer_init();
/* Main initialization stage. Modules may enable interrupts here. */
cpu_init();
#ifdef CONFIG_DMA
/* Initialize DMA. Must be before UART. */
dma_init();
#endif
/* Initialize UART. Console output functions may now be used. */
uart_init();
if (system_jumped_to_this_image()) {
CPRINTS("UART initialized after sysjump");
} else {
CPUTS("\n\n--- UART initialized after reboot ---\n");
CPUTS("[Reset cause: ");
system_print_reset_flags();
CPUTS("]\n");
}
CPRINTF("[Image: %s, %s]\n",
system_get_image_copy_string(), system_get_build_info());
#ifdef CONFIG_WATCHDOG
/*
* Intialize watchdog timer. All lengthy operations between now and
* task_start() must periodically call watchdog_reload() to avoid
* triggering a watchdog reboot. (This pretty much applies only to
* verified boot, because all *other* lengthy operations should be done
* by tasks.)
*/
watchdog_init();
#endif
/*
* Verified boot needs to read the initial keyboard state and EEPROM
* contents. EEPROM must be up first, so keyboard_scan can toggle
* debugging settings via keys held at boot.
*/
#ifdef CONFIG_EEPROM
eeprom_init();
#endif
#ifdef CONFIG_EOPTION
eoption_init();
#endif
#ifdef HAS_TASK_KEYSCAN
keyboard_scan_init();
#endif
/* Initialize the hook library. This calls HOOK_INIT hooks. */
hook_init();
/*
* Print the init time. Not completely accurate because it can't take
* into account the time before timer_init(), but it'll at least catch
* the majority of the time.
*/
CPRINTS("Inits done");
/* Launch task scheduling (never returns) */
return task_start();
}
int main (void)
{
u32 count = 0;
s32 i, j, k = 0;
u32 max, sum;
volatile u32 tmp;
u32 *p;
char *pstr;
p = (u32 *)(DRAM_PHYS_START + 0x6000);
u32 boot;
u32 load_start, load_end;
u32 boot_start, boot_end;
u32 bm_load_duration_ns, bm_load_duration_ms;
/* get the timestamp of the osc timer1 */
boot_end = readl((const volatile void *)SOCFPGA_OSC1TIMER1_ADDRESS + 0x4);
InitPeripheral();
cpu_local_irq_disable();
/* asp is cleared by the preloader , and preloader will save
* qspi probe, read function in it. Please don't clear
* we reuse the preloader qspi driver at here, so we save
* the probe and read function pointer into asp.
* it at here.
*/
//memset(asp, 0, sizeof(struct amp_share_param));
asp->bm_magic = ('b' << 8) | 'm';
/**** interrupt initialize*******/
gic_Int_init();
/**** hook ISR callback ******/
gic_sgi_init();
#ifdef NEED_SAVE_RESTORE_GIC_REGS_FROM_BM
gic_dist_save();
#endif
/**** interrupt ready *****/
cpu_local_irq_enable();
UART_DEBUG("start bm...... %x\r\n", p);
UART_DEBUG("++start bm...... 12345\r\n");
bmlog("start bm......%x\r\n", p);
UART_DEBUG("start bm...... %x\r\n", 0x55aa);
UART_DEBUG("--start bm...... 67890\r\n");
/* auto detect the boot mode */
boot = bm_get_boot_mode();
if((BOOTSEL_MODE_SD_1_8V == boot) || (BOOTSEL_MODE_SD_3_3V == boot))
{
if(!bm_sd_load_rbf())
bmlog("load fpga rbf is ok!\n");
}
else if((BOOTSET_MODE_QSPI_1_8V == boot) || (BOOTSET_MODE_QSPI_3_3V == boot))
{
if(!bm_qspi_load_rbf())
bmlog("load fpga rbf is ok!\n");
}
/* osc_timer1 is running at 25MHz, 40ns per cycle */
asp->boot_end_stamp = boot_end;
boot_start = asp->boot_start_stamp;
bm_load_duration_ns = (boot_start - boot_end) * 40;
bm_load_duration_ms = bm_load_duration_ns/1000/1000;
bmlog("start[0x%x],end[%x]\n, bm_load_ns = %u(ns), bm_load_ms= %u(ms)\n",
boot_start,
boot_end,
bm_load_duration_ns,
bm_load_duration_ms
);
load_start = asp->load_bm_start;
load_end = asp->load_bm_end;
bmlog("real loading bm time duration is %u(ms)(including qspi/sd init)\n", load_end - load_start);
if(fpgamgr_program_fpga((const unsigned long *)FPGA_RBF_BASE, FPGA_RBF_SIZE) < 0)
UART_DEBUG("config fpga failed!\r\n");
else
{
UART_DEBUG("config fpga OK!\r\n");
writel(('R'<<16)|('B'<<8)|('F'<<0),&(asp->preloader_wait_bm_load_rbf));
}
pstr = (char *)FPGA_SDRAM_PHYS_BASE;
sprintf(pstr, "%s\n", "i am from fpga ddr ram");
bmlog("%s", pstr);
pstr = (char *)FPGA_SRAM_PHYS_BASE;
sprintf(pstr, "%s\n", "i am from fpga sram");
bmlog("%s", pstr);
#ifdef LCD1602_DISP
IIC_InitIp();
LCD_SetCursor(0);
sprintf(cDispBuf[0], "fpga config done!");
IIC_EXfer(LCD_ADDR, cDispBuf[0], strlen(cDispBuf[0])>15?16:strlen(cDispBuf[0]));
#endif
while(!gCacheCoherence)
{
/** led blink for hand shake debug with linux **/
k++;
if((k&0x3FFFF) == 0)
LED27_BLINK();//*(volatile u32 *)HPS_GPIO1_BASE_ADDR ^= (0x1<<12);
}
/*
**************************************************************
**** cause Linux peer use 2GB user space/2GB kernel space split *******
**** so it is 2048 L1 entry here, if use 3GB user/1 GB space split ********
**** it woule be 1024 here, and p should adjust to 0x7000 yejc ********
**************************************************************
*/
for(j = 0; j < 2048-16; j++) //16MB for IO map space
PageTable[j+2048] = *p++;
/*
**************************************************************
**** time to bring bm core to smp cache coherence environmence *******
**************************************************************
*/
__asm__ __volatile__("dsb\n"
"isb\n"
"mrc p15, 0, r1, c1, c0, 0\n"
"ldr r2, =0x40180d\n"
"orr r1, r1, r2\n"
"mcr p15, 0, r1, c1, c0, 0\n"
"dsb\n"
"isb\n"
: : :"memory", "cc");
bmlog("L1 L2 cache enabled, SCU enabled~~~\n");
//asp = 0xFC700000;
/*
********************************************************************************
** from this point on, you can free to invoke the linux kernel space text function from BM, *****
** only if the function would not cause the shceduler to action, or the CPU of BM would trap *****
** in the cpu_idle(clone from linux cpu core) process if we can't not obtain the lock/mutex *****
** /semaphore ****
********************************************************************************
*/
//printk = (printk_fn)asp->sta.printk_fn;
_raw_spinlock = (raw_spinlock_fn)asp->sta.spinlock_lock_fn;
_raw_spinunlock = (raw_spinlock_fn)asp->sta.spinlock_unlock_fn;
/* semaphore */
down_trylock = (down_trylock_fn)asp->sta._down_trylock_fn;
while(1)
{
if(sgi15task_pending)
{
if(ACCESS_ONCE(asp->sra[SGI_LINUX_REQ_BM_CONSUME_BUF].linux_cmd_args) == 0)
{
/**************************************************************************************/
/**** place interrupt here test worse case interrupt latency would be more accuracy ***/
/**** casue we not only take care of 10000 interrupts/second from FPGA, but also ***/
/**** suffer more than 6000 extra interrupts/second from IPI and offen L1 data cahce miss **/
/**************************************************************************************/
#ifdef TEST_IL_MORE_ACCURACY
if(testIL)
{
bmlog("\n________________________________________________________________________________\n");
bmlog("Now the BM CPU would suffer more than 16000 interrupts/second(10000i/s from\n");
bmlog("FPGA_IRQ0 req(100us),more than 6000i/s from IPI(Inner Process Interrupt), and\n");
bmlog("process several Gbps data per second, they are all concurrently, very intensive\n");
bmlog("load for BM CPU core!\n");
bmlog("__________________________________________________________________________________\n");
testIL = 0;
gic_Int_dis (GIC_PFGA0); //72 FPGA_IRQ0
gic_Int_clr (GIC_PFGA0);
pvt_init(1);
fire_fpga_irq();
pvt_start();
gic_Int_en (GIC_PFGA0);
}
#endif
/************************************************************************/
//p = (unsigned int *)0x1E200000;
p = (unsigned int *)0xFC800000;
for(i = 0; i < (DRAM_BUF_SIZE/4); i++)
{
if(*p != CPU_DATA_PATERN0)
bmlog("check buf from linux failed! i=%d, *p=%x\n", i, *p);
p++;
}
//bmlog("check buf from linux finish!\n");
//p = (unsigned int *)0x1E200000;
p = (unsigned int *)0xFC800000;
memset_int(p, CPU_DATA_PATERN3, DRAM_BUF_SIZE);
//now u can mesure blink frequency on hps LED3 and multiply 2 to calculate the interrupte frequency
//and then you can evaulate how fast the cpu do 2 times DRAM_SIZE write and 2 times DRAM_SIZE read
//you sholud know that cpu spend must time to iter, compare in the read "for loop" and BM do interrupt
//handler&cpu mode switch Linux handle system tick&sgi intrrupt and sched task, so the actual memory system
//band width is greater than this evaluate value
//be aware 65536B is bigger than L1 Dcache but little than L2 Dcache
//evaluate data process speed in our case is:
//1842Hz * 2toggle * 2w * 2r&check * DRAM_SIZE(65536B) = 965738496B/s = 7.73Gbps
//toggle hps led
//*(volatile u32 *)HPS_GPIO1_BASE_ADDR ^= (0x1<<12);
LED27_BLINK();
sgi15task_pending = 0;
gic_raise_interrupt(CPU0, GIC_SGI13);
}
else if(ACCESS_ONCE(asp->sra[SGI_LINUX_REQ_BM_CONSUME_BUF].linux_cmd_args) == 1)
{
p = (unsigned int *)0xfe700000;
for(i = 0; i < (SRAM_BUF_SIZE/4); i++)
{
if(*p != CPU_DATA_PATERN0)
bmlog("check buf from linux failed! i=%d, *p=%x\n", i, *p);
p++;
}
//bmlog("check buf from linux finish!\n");
p = (unsigned int *)0xfe700000;
memset_int(p, CPU_DATA_PATERN3, SRAM_BUF_SIZE);
//now u can mesure blink frequency on hps LED2 and multiply 2 to calculate the interrupte frequency
//and then you can evaulate how fast the cpu do 2 times SRAM_SIZE write and 2 times SRAM_SIZE read
//you sholud know that cpu spend must time to iter, compare in the read "for loop" and BM do interrupt
//handler&cpu mode switch Linux handle system tick&sgi intrrupt and sched task, so the actual memory system
//band width is greater than this evaluate value
//be aware 32768B is bigger than L1 Dcache but little than L2 Dcache
//evaluate data process speed in our case is:
//3230Hz * 2toggle * 2w * 2r&check * SRAM_SIZE(32768B) = 846725120B/s = 6.77Gbps //little then DRAM cause much more interrupt overhead
//toggle hps led
//*(volatile u32 *)HPS_GPIO1_BASE_ADDR ^= (0x2<<12);
LED28_BLINK();
sgi15task_pending = 0;
gic_raise_interrupt(CPU0, GIC_SGI13);
}
//bmlog("CPU1#%04d:msg from cpu1 call~~~~~~~~~~~~~~~~\n", i);
}
if(asp->sra[SGI_LINUX_REQ_BM_CONSUME_BUF].linux_cmd_args == 2)
{
for(i = 0; i < SPINLOCK_TEST_COUNT; i++)
{
_raw_spinlock(&asp->rslocks[0]);
tmp = asp->sra[SGI_LINUX_REQ_BM_CONSUME_BUF].bm_cmd_status;
//dummy j++
j++;
asp->sra[SGI_LINUX_REQ_BM_CONSUME_BUF].bm_cmd_status += 2;
if((asp->sra[SGI_LINUX_REQ_BM_CONSUME_BUF].bm_cmd_status - tmp) != 2)
bmlog("BM:spinlock test failed!\n");
_raw_spinunlock(&asp->rslocks[0]);
//dummy operation on j++ simulate the actual scenario to give another cpu chance
//to take lock, reduce starvation situation
j++;
}
//bmlog("\nBM spinlock test:%d\n", tmp + 2);
bmlog("\n----------------------------\n");
bmlog("BM spinlock test:%d\n", tmp + 2);
bmlog("----------------------------\n");
/*************************************************************************************/
/**** place interrupt test here test cpu data process speed would be more accuracy ***/
/*************************************************************************************/
#ifdef TEST_DATA_PROCESS_SPEED_MORE_ACCURACY
gic_Int_dis (GIC_PFGA0); //72 FPGA_IRQ0
gic_Int_clr (GIC_PFGA0);
pvt_init(1);
fire_fpga_irq();
pvt_start();
gic_Int_en (GIC_PFGA0);
#endif
/************************************************************************/
while(!ACCESS_ONCE(gINTtestDone));
ACCESS_ONCE(gINTtestDone) = 0;
for(i = 0; i < IL_TEST_COUNT - 1; i++)
{
p_pvt[i] = p_pvt[i] - p_pvt[i + 1]; //delta t of pvt, be careful pvt counter overlap!
}
for(i = 0; i < IL_TEST_COUNT - 1; i++)
{
if(p_pvt[i] > PVT_100US_CYCLE)
p_pvt[i] -= PVT_100US_CYCLE; /* pvt 10ns resolution, 10000 * 10ns = 100us*/ //IL(interrupt latency jitter)
else
p_pvt[i] = PVT_100US_CYCLE - p_pvt[i];
}
max = p_pvt[0];
k = 0;
for(i = 0; i < IL_TEST_COUNT - 1; i++)
if(p_pvt[i] > max)
{
max = p_pvt[i];
k = i;
}
max *= 10;
bmlog("\n------------------------------------------------------------------------------------------\n");
//bmlog("\ninterrupt latency test method 1(use private timer)\n");
bmlog("interrupt latency test method 1(use private timer)\n");
//bmlog("max interrupt latency jitter: %d ns\n", max);
bmlog("max interrupt latency jitter: %d ns\n", max);
sum = 0;
for(i = 0; i < IL_TEST_COUNT - 1; i++)
{
sum += p_pvt[i]; //be carefule sum overflow
}
sum /= (IL_TEST_COUNT - 1);
sum *= 10;
//bmlog("average interrupt latency jitter: %d ns\n", sum);
bmlog("average interrupt latency jitter: %d ns\n", sum);
//90ns is measure from oscilloscope, see AMP Reference Design for detail
bmlog("max interrupt latency: %d ns(use private timer@CPU core cluster)\n", max + 90);
if(max>410)
bmlog("max interrupt latency: %d ns(use private timer@CPU core cluster),max_index=%d\n", max + 90, k);
bmlog("average interrupt latency: %d ns(use private timer@CPU core cluster)\n", sum + 90);
bmlog("-----------------------------------------------------------------------------------------------\n");
bmlog("\n-----------------------------------------------------------------------------------------------\n");
//bmlog("\nfpga send %d times irq req to arm, arm ack %d times, lost irq %d times\n", gFPGA_IRQ_req, gARM_IRQ_ack, gFPGA_IRQ_req - gARM_IRQ_ack);
bmlog("fpga send %d times irq req to arm, arm ack %d times, lost irq %d times\n",
ACCESS_ONCE(gFPGA_IRQ_req), ACCESS_ONCE(gARM_IRQ_ack), ACCESS_ONCE(gFPGA_IRQ_req) - ACCESS_ONCE(gARM_IRQ_ack));
bmlog("-------------------------------------------------------------------------------------------------\n");
testIL = 1;
#ifdef DMA_AND_ACP_TEST
dma_init();
//DMAC_regs_dump(0);
dma_mem2mem();//new for test
//DMAC_regs_dump(0);
while(!ACCESS_ONCE(gDMAtestDone));
ACCESS_ONCE(gDMAtestDone) = 0;
dma_mem2mem_done();
//DMAC_regs_dump(0);
bmlog("DMA test done\n");
bmlog("-----------------------------------------------\n\n");
dma_mem2mem_use_acp();
while(!ACCESS_ONCE(gDMAtestDone));
ACCESS_ONCE(gDMAtestDone) = 0;
dma_mem2mem_use_acp_done();
bmlog("DMA test acp done\n");
bmlog("-----------------------------------------------\n\n");
dma_ARMmem2FPGAmem();
while(!ACCESS_ONCE(gDMAtestDone));
ACCESS_ONCE(gDMAtestDone) = 0;
dma_mem2mem_done();
bmlog("dma_ARMmem2FPGAmem test done\n");
bmlog("-----------------------------------------------\n\n");
dma_FPGAmem2ARMmem_use_acp();
while(!ACCESS_ONCE(gDMAtestDone));
ACCESS_ONCE(gDMAtestDone) = 0;
dma_mem2mem_done();
bmlog("dma_FPGAmem2ARMmem_use_acp test done\n");
bmlog("-----------------------------------------------\n\n");
#endif
count++;
#ifdef LCD1602_DISP
LCD_SetCursor(1);
memset(cDispBuf[1], ' ', 16);
sprintf(cDispBuf[1], "test:%d", count);
IIC_EXfer(LCD_ADDR, cDispBuf[1], 16);
#endif
asp->sra[SGI_LINUX_REQ_BM_CONSUME_BUF].linux_cmd_args = -1; //tell linux interrupt latency and dma test done!
}
//dummy k++ and toggle hps led1, waste cpu time..
//indicate bm activity, u can measure the toggle freqency to evalute how much time spend per loop
//loop cycle = 1s /(toggle freqency * 2 * 1048576)
//in our case cpu = 800MHz, no interrupt to handle no work cmd,
// loop cycle = 1/(42.384*2*1048576) * 10^9 = 11.25ns
//if remov the K++, if((k&0xFFFFF) == 0){...} block, we can remove about 7 dissemable instrution~8 clock cycle
// 11.25 * (6 +6)(instrution)/(6+6+8) total instrution = 6.75ns
k++;
if((k&0x1FFFFF) == 0)
LED30_BLINK();
}
}
void play_sound(unsigned long addr,int size)
{
dma_init(addr,size);
AC_GLBCTRL |= (2<<12);
}
void board_init(void)
{
/* Configure the memory interface */
calypso_mem_cfg(CALYPSO_nCS0, 3, CALYPSO_MEM_16bit, 1);
calypso_mem_cfg(CALYPSO_nCS1, 3, CALYPSO_MEM_16bit, 1);
calypso_mem_cfg(CALYPSO_nCS2, 5, CALYPSO_MEM_16bit, 1);
calypso_mem_cfg(CALYPSO_nCS3, 5, CALYPSO_MEM_16bit, 1);
calypso_mem_cfg(CALYPSO_CS4, 0, CALYPSO_MEM_8bit, 1);
calypso_mem_cfg(CALYPSO_nCS6, 0, CALYPSO_MEM_32bit, 1);
calypso_mem_cfg(CALYPSO_nCS7, 0, CALYPSO_MEM_32bit, 0);
/* Set VTCXO_DIV2 = 1, configure PLL for 104 MHz and give ARM half of that */
calypso_clock_set(2, CALYPSO_PLL13_104_MHZ, ARM_MCLK_DIV_2);
/* Configure the RHEA bridge with some sane default values */
calypso_rhea_cfg(0, 0, 0xff, 0, 1, 0, 0);
/* Initialize board-specific GPIO */
board_io_init();
/* Enable bootrom mapping to route exception vectors to RAM */
calypso_bootrom(1);
calypso_exceptions_install();
/* Initialize interrupt controller */
irq_init();
/* initialize MODEM UART to be used for sercomm*/
uart_init(SERCOMM_UART_NR, 1);
uart_baudrate(SERCOMM_UART_NR, UART_115200);
/* Initialize IRDA UART to be used for old-school console code.
* note: IRDA uart only accessible on C115 and C117 PCB */
uart_init(CONS_UART_NR, 1);
uart_baudrate(CONS_UART_NR, UART_115200);
/* Initialize hardware timers */
hwtimer_init();
/* Initialize DMA controller */
dma_init();
/* Initialize real time clock */
rtc_init();
/* Initialize system timers (uses hwtimer 2) */
timer_init();
/* Initialize LCD driver (uses I2C) and backlight */
display = &st7558_display;
display_init();
bl_mode_pwl(1);
bl_level(0);
/* Initialize keypad driver */
keypad_init(1);
/* Initialize ABB driver (uses SPI) */
twl3025_init();
/* enable LEDB driver of Iota for keypad backlight */
twl3025_reg_write(AUXLED, 0x02);
}
/*---------------------------------------------------------------------------*/
int
main(void)
{
/* Hardware initialization */
clock_init();
soc_init();
rtimer_init();
/* Init LEDs here */
leds_init();
leds_off(LEDS_ALL);
fade(LEDS_GREEN);
/* initialize process manager. */
process_init();
/* Init UART */
uart0_init();
#if DMA_ON
dma_init();
#endif
#if SLIP_ARCH_CONF_ENABLE
slip_arch_init(0);
#else
uart0_set_input(serial_line_input_byte);
serial_line_init();
#endif
fade(LEDS_RED);
PUTSTRING("##########################################\n");
putstring(CONTIKI_VERSION_STRING "\n");
putstring("TI SmartRF05 EB\n");
switch(CHIPID) {
case 0xA5:
putstring("cc2530");
break;
case 0xB5:
putstring("cc2531");
break;
case 0x95:
putstring("cc2533");
break;
case 0x8D:
putstring("cc2540");
break;
}
putstring("-F");
switch(CHIPINFO0 & 0x70) {
case 0x40:
putstring("256, ");
break;
case 0x30:
putstring("128, ");
break;
case 0x20:
putstring("64, ");
break;
case 0x10:
putstring("32, ");
break;
}
puthex(CHIPINFO1 + 1);
putstring("KB SRAM\n");
PUTSTRING("\nSDCC Build:\n");
#if STARTUP_VERBOSE
#ifdef HAVE_SDCC_BANKING
PUTSTRING(" With Banking.\n");
#endif /* HAVE_SDCC_BANKING */
#ifdef SDCC_MODEL_LARGE
PUTSTRING(" --model-large\n");
#endif /* SDCC_MODEL_LARGE */
#ifdef SDCC_MODEL_HUGE
PUTSTRING(" --model-huge\n");
#endif /* SDCC_MODEL_HUGE */
#ifdef SDCC_STACK_AUTO
PUTSTRING(" --stack-auto\n");
#endif /* SDCC_STACK_AUTO */
PUTCHAR('\n');
PUTSTRING(" Net: ");
PUTSTRING(NETSTACK_NETWORK.name);
PUTCHAR('\n');
PUTSTRING(" MAC: ");
PUTSTRING(NETSTACK_MAC.name);
PUTCHAR('\n');
PUTSTRING(" RDC: ");
PUTSTRING(NETSTACK_RDC.name);
PUTCHAR('\n');
PUTSTRING("##########################################\n");
#endif
watchdog_init();
/* Initialise the H/W RNG engine. */
random_init(0);
/* start services */
process_start(&etimer_process, NULL);
ctimer_init();
/* initialize the netstack */
netstack_init();
set_rime_addr();
#if BUTTON_SENSOR_ON || ADC_SENSOR_ON
process_start(&sensors_process, NULL);
BUTTON_SENSOR_ACTIVATE();
ADC_SENSOR_ACTIVATE();
#endif
#if UIP_CONF_IPV6
memcpy(&uip_lladdr.addr, &rimeaddr_node_addr, sizeof(uip_lladdr.addr));
queuebuf_init();
process_start(&tcpip_process, NULL);
#endif /* UIP_CONF_IPV6 */
#if VIZTOOL_CONF_ON
process_start(&viztool_process, NULL);
#endif
energest_init();
ENERGEST_ON(ENERGEST_TYPE_CPU);
autostart_start(autostart_processes);
watchdog_start();
fade(LEDS_YELLOW);
while(1) {
do {
/* Reset watchdog and handle polls and events */
watchdog_periodic();
#if CLOCK_CONF_STACK_FRIENDLY
if(sleep_flag) {
if(etimer_pending() &&
(etimer_next_expiration_time() - clock_time() - 1) > MAX_TICKS) {
etimer_request_poll();
}
sleep_flag = 0;
}
#endif
r = process_run();
} while(r > 0);
len = NETSTACK_RADIO.pending_packet();
if(len) {
packetbuf_clear();
len = NETSTACK_RADIO.read(packetbuf_dataptr(), PACKETBUF_SIZE);
if(len > 0) {
packetbuf_set_datalen(len);
NETSTACK_RDC.input();
}
}
#if LPM_MODE
#if (LPM_MODE==LPM_MODE_PM2)
SLEEP &= ~OSC_PD; /* Make sure both HS OSCs are on */
while(!(SLEEP & HFRC_STB)); /* Wait for RCOSC to be stable */
CLKCON |= OSC; /* Switch to the RCOSC */
while(!(CLKCON & OSC)); /* Wait till it's happened */
SLEEP |= OSC_PD; /* Turn the other one off */
#endif /* LPM_MODE==LPM_MODE_PM2 */
/*
* Set MCU IDLE or Drop to PM1. Any interrupt will take us out of LPM
* Sleep Timer will wake us up in no more than 7.8ms (max idle interval)
*/
SLEEPCMD = (SLEEPCMD & 0xFC) | (LPM_MODE - 1);
#if (LPM_MODE==LPM_MODE_PM2)
/*
* Wait 3 NOPs. Either an interrupt occurred and SLEEP.MODE was cleared or
* no interrupt occurred and we can safely power down
*/
__asm
nop
nop
nop
__endasm;
if(SLEEPCMD & SLEEP_MODE0) {
#endif /* LPM_MODE==LPM_MODE_PM2 */
ENERGEST_OFF(ENERGEST_TYPE_CPU);
ENERGEST_ON(ENERGEST_TYPE_LPM);
/* We are only interested in IRQ energest while idle or in LPM */
ENERGEST_IRQ_RESTORE(irq_energest);
/* Go IDLE or Enter PM1 */
PCON |= PCON_IDLE;
/* First instruction upon exiting PM1 must be a NOP */
__asm
nop
__endasm;
/* Remember energest IRQ for next pass */
ENERGEST_IRQ_SAVE(irq_energest);
ENERGEST_ON(ENERGEST_TYPE_CPU);
ENERGEST_OFF(ENERGEST_TYPE_LPM);
#if (LPM_MODE==LPM_MODE_PM2)
SLEEPCMD &= ~SLEEP_OSC_PD; /* Make sure both HS OSCs are on */
while(!(SLEEPCMD & SLEEP_XOSC_STB)); /* Wait for XOSC to be stable */
CLKCONCMD &= ~CLKCONCMD_OSC; /* Switch to the XOSC */
/*
* On occasion the XOSC is reported stable when in reality it's not.
* We need to wait for a safeguard of 64us or more before selecting it
*/
clock_delay(10);
while(CLKCONCMD & CLKCONCMD_OSC); /* Wait till it's happened */
}
#endif /* LPM_MODE==LPM_MODE_PM2 */
#endif /* LPM_MODE */
}
}
int gmac_mac_init(struct eth_device *dev)
{
struct eth_info *eth = (struct eth_info *)(dev->priv);
struct eth_dma *dma = &(eth->dma);
uint32_t tmp;
uint32_t cmdcfg;
int chipid;
debug("%s enter\n", __func__);
/* Always use GMAC0 */
printf("Using GMAC%d\n", 0);
/* Reset AMAC0 core */
writel(0, AMAC0_IDM_RESET_ADDR);
tmp = readl(AMAC0_IO_CTRL_DIRECT_ADDR);
/* Set clock */
tmp &= ~(1 << AMAC0_IO_CTRL_CLK_250_SEL_SHIFT);
tmp |= (1 << AMAC0_IO_CTRL_GMII_MODE_SHIFT);
/* Set Tx clock */
tmp &= ~(1 << AMAC0_IO_CTRL_DEST_SYNC_MODE_EN_SHIFT);
writel(tmp, AMAC0_IO_CTRL_DIRECT_ADDR);
/* reset gmac */
/*
* As AMAC is just reset, NO need?
* set eth_data into loopback mode to ensure no rx traffic
* gmac_loopback(eth_data, TRUE);
* ET_TRACE(("%s gmac loopback\n", __func__));
* udelay(1);
*/
cmdcfg = readl(UNIMAC0_CMD_CFG_ADDR);
cmdcfg &= ~(CC_TE | CC_RE | CC_RPI | CC_TAI | CC_HD | CC_ML |
CC_CFE | CC_RL | CC_RED | CC_PE | CC_TPI |
CC_PAD_EN | CC_PF);
cmdcfg |= (CC_PROM | CC_NLC | CC_CFE);
/* put mac in reset */
gmac_init_reset();
writel(cmdcfg, UNIMAC0_CMD_CFG_ADDR);
gmac_clear_reset();
/* enable clear MIB on read */
reg32_set_bits(GMAC0_DEV_CTRL_ADDR, DC_MROR);
/* PHY: set smi_master to drive mdc_clk */
reg32_set_bits(GMAC0_PHY_CTRL_ADDR, PC_MTE);
/* clear persistent sw intstatus */
writel(0, GMAC0_INT_STATUS_ADDR);
if (dma_init(dma) < 0) {
pr_err("%s: GMAC dma_init failed\n", __func__);
goto err_exit;
}
chipid = CHIPID;
printf("%s: Chip ID: 0x%x\n", __func__, chipid);
/* set switch bypass mode */
tmp = readl(SWITCH_GLOBAL_CONFIG_ADDR);
tmp |= (1 << CDRU_SWITCH_BYPASS_SWITCH_SHIFT);
/* Switch mode */
/* tmp &= ~(1 << CDRU_SWITCH_BYPASS_SWITCH_SHIFT); */
writel(tmp, SWITCH_GLOBAL_CONFIG_ADDR);
tmp = readl(CRMU_CHIP_IO_PAD_CONTROL_ADDR);
tmp &= ~(1 << CDRU_IOMUX_FORCE_PAD_IN_SHIFT);
writel(tmp, CRMU_CHIP_IO_PAD_CONTROL_ADDR);
/* Set MDIO to internal GPHY */
tmp = readl(GMAC_MII_CTRL_ADDR);
/* Select internal MDC/MDIO bus*/
tmp &= ~(1 << GMAC_MII_CTRL_BYP_SHIFT);
/* select MDC/MDIO connecting to on-chip internal PHYs */
tmp &= ~(1 << GMAC_MII_CTRL_EXT_SHIFT);
/*
* give bit[6:0](MDCDIV) with required divisor to set
* the MDC clock frequency, 66MHZ/0x1A=2.5MHZ
*/
tmp |= 0x1A;
writel(tmp, GMAC_MII_CTRL_ADDR);
if (gmac_mii_busywait(1000)) {
pr_err("%s: Configure MDIO: MII/MDIO busy\n", __func__);
goto err_exit;
}
/* Configure GMAC0 */
/* enable one rx interrupt per received frame */
writel(1 << GMAC0_IRL_FRAMECOUNT_SHIFT, GMAC0_INTR_RECV_LAZY_ADDR);
/* read command config reg */
cmdcfg = readl(UNIMAC0_CMD_CFG_ADDR);
/* enable 802.3x tx flow control (honor received PAUSE frames) */
cmdcfg &= ~CC_RPI;
/* enable promiscuous mode */
cmdcfg |= CC_PROM;
/* Disable loopback mode */
cmdcfg &= ~CC_ML;
/* set the speed */
cmdcfg &= ~(CC_ES_MASK | CC_HD);
/* Set to 1Gbps and full duplex by default */
cmdcfg |= (2 << CC_ES_SHIFT);
/* put mac in reset */
gmac_init_reset();
/* write register */
writel(cmdcfg, UNIMAC0_CMD_CFG_ADDR);
/* bring mac out of reset */
gmac_clear_reset();
/* set max frame lengths; account for possible vlan tag */
writel(PKTSIZE + 32, UNIMAC0_FRM_LENGTH_ADDR);
return 0;
err_exit:
dma_deinit(dma);
return -1;
}
long int initdram (int board_type)
{
long dram_size = 0;
#if !defined(CONFIG_RAM_AS_FLASH)
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
sys_info_t sysinfo;
uint temp_lbcdll = 0;
#endif
#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
#endif
#if defined(CONFIG_DDR_DLL)
uint temp_ddrdll = 0;
/* Work around to stabilize DDR DLL */
temp_ddrdll = gur->ddrdllcr;
gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
asm("sync;isync;msync");
#endif
#if defined(CONFIG_SPD_EEPROM)
dram_size = spd_sdram ();
#else
dram_size = fixed_sdram ();
#endif
#if defined(CFG_RAMBOOT)
return dram_size;
#endif
#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */
get_sys_info(&sysinfo);
/* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000;
} else {
lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
udelay(200);
temp_lbcdll = gur->lbcdllcr;
gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
asm("sync;isync;msync");
}
lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */
lbc->br2 = CFG_BR2_PRELIM;
lbc->lbcr = CFG_LBC_LBCR;
lbc->lsdmr = CFG_LBC_LSDMR_1;
asm("sync");
* (ulong *)0 = 0x000000ff;
lbc->lsdmr = CFG_LBC_LSDMR_2;
asm("sync");
* (ulong *)0 = 0x000000ff;
lbc->lsdmr = CFG_LBC_LSDMR_3;
asm("sync");
* (ulong *)0 = 0x000000ff;
lbc->lsdmr = CFG_LBC_LSDMR_4;
asm("sync");
* (ulong *)0 = 0x000000ff;
lbc->lsdmr = CFG_LBC_LSDMR_5;
asm("sync");
lbc->lsrt = CFG_LBC_LSRT;
asm("sync");
lbc->mrtpr = CFG_LBC_MRTPR;
asm("sync");
#endif
#if defined(CONFIG_DDR_ECC)
{
/* Initialize all of memory for ECC, then
* enable errors */
uint *p = 0;
uint i = 0;
volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
dma_init();
for (*p = 0; p < (uint *)(8 * 1024); p++) {
if (((unsigned int)p & 0x1f) == 0) {
dcbz(p);
}
*p = (unsigned int)0xdeadbeef;
if (((unsigned int)p & 0x1c) == 0x1c) {
dcbf(p);
}
}
/* 8K */
dma_xfer((uint *)0x2000,0x2000,(uint *)0);
/* 16K */
dma_xfer((uint *)0x4000,0x4000,(uint *)0);
/* 32K */
dma_xfer((uint *)0x8000,0x8000,(uint *)0);
/* 64K */
dma_xfer((uint *)0x10000,0x10000,(uint *)0);
/* 128k */
dma_xfer((uint *)0x20000,0x20000,(uint *)0);
/* 256k */
dma_xfer((uint *)0x40000,0x40000,(uint *)0);
/* 512k */
dma_xfer((uint *)0x80000,0x80000,(uint *)0);
/* 1M */
dma_xfer((uint *)0x100000,0x100000,(uint *)0);
/* 2M */
dma_xfer((uint *)0x200000,0x200000,(uint *)0);
/* 4M */
dma_xfer((uint *)0x400000,0x400000,(uint *)0);
for (i = 1; i < dram_size / 0x800000; i++) {
dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
}
/* Enable errors for ECC */
ddr->err_disable = 0x00000000;
asm("sync;isync;msync");
}
#endif
return dram_size;
}
//
// syscall entry point
//
long int syscall(unsigned long int command,...){
int ret;
va_list ap;
ret = 0;
va_start(ap,command);
switch (command) {
// SYS
case SYS_INIT: {
tick_init(); // raw-handler
int_init(); // raw-handler
syscall(SYS_TIMER_INIT);
syscall(SYS_DMA_INIT);
syscall(SYS_VRAM_INIT);
syscall(SYS_SCREEN_INIT);
syscall(SYS_UART_INIT);
ret = 0;
} break;
// TIMER
case SYS_TIMER_INIT: {
timer_init(&timer);
ret = 0;
} break;
case SYS_TIMER_GET_COUNT: {
ret = timer_get_count(&timer);
} break;
// DMA
case SYS_DMA_INIT: {
unsigned long int base;
unsigned long int irq;
base = va_arg(ap,unsigned long int);
irq = va_arg(ap,unsigned long int);
dma.ch = dma_channel;
dma.ch_size = DMA_CH_SIZE;
dma.ch[0].buf = dma_buffer_ch0;
dma.ch[0].buf_size = DMA_BUF_SIZE;
dma_init(&dma,DMA_BASE,DMA_IRQ);
ret = 0;
} break;
case SYS_DMA_ADD: {
unsigned long int ch;
void *src;
void *dst;
unsigned long int size;
ch = va_arg(ap,unsigned long int);
src = va_arg(ap,void *);
dst = va_arg(ap,void *);
size = va_arg(ap,unsigned long int);
dma_add(&dma,ch,src,dst,size);
ret = 0;
} break;
case SYS_DMA_ADD_FULL: {
unsigned long int ch;
ch = va_arg(ap,unsigned long int);
ret = (long int)dma_add_full(&dma,ch);
} break;
case SYS_DMA_GET_HANDLE: {
ret = (long int)&dma;
} break;
case SYS_DMA_GET_CH: {
ret = 0;
} break;
// VRAM
case SYS_VRAM_INIT: {
vram_init(&vram,&dma,0);
ret = 0;
} break;
case SYS_VRAM_CLEAR: {
vram_clear(&vram);
ret = 0;
} break;
case SYS_VRAM_IMAGE_PASTE: {
IMAGE *img;
unsigned long int x;
unsigned long int y;
img = va_arg(ap,IMAGE *);
x = va_arg(ap,unsigned long int);
y = va_arg(ap,unsigned long int);
vram_image_paste(&vram,img,x,y);
ret = 0;
} break;
case SYS_VRAM_IMAGE_PASTE_FILTER: {
IMAGE *img;
unsigned long int x;
unsigned long int y;
img = va_arg(ap,IMAGE *);
x = va_arg(ap,unsigned long int);
y = va_arg(ap,unsigned long int);
vram_image_paste_filter(&vram,img,x,y);
ret = 0;
} break;
case SYS_VRAM_IMAGE_CLEAR: {
IMAGE *img;
unsigned long int x;
unsigned long int y;
img = va_arg(ap,IMAGE *);
x = va_arg(ap,unsigned long int);
y = va_arg(ap,unsigned long int);
vram_image_clear(&vram,img,x,y);
ret = 0;
} break;
// SCREEN
case SYS_SCREEN_INIT: {
screen_init(&scr,&vram);
ret = 0;
} break;
case SYS_SCREEN_CLEAR: {
screen_clear(&scr);
ret = 0;
} break;
case SYS_SCREEN_LOCATE: {
unsigned long int x;
unsigned long int y;
x = va_arg(ap,unsigned long int);
y = va_arg(ap,unsigned long int);
screen_locate(&scr,x,y);
ret = 0;
} break;
case SYS_SCREEN_SCROLL: {
unsigned long int height;
height = va_arg(ap,unsigned long int);
screen_scroll(&scr,height);
ret = 0;
} break;
case SYS_SCREEN_PUT_STRING: {
unsigned char *s;
s = va_arg(ap,unsigned char *);
screen_put_string(&scr,s);
ret = 0;
} break;
case SYS_SCREEN_PUT_CHAR: {
unsigned char c;
c = va_arg(ap,unsigned int); // usigned char
screen_put_char(&scr,c);
ret = 0;
} break;
case SYS_SCREEN_PRINT: {
unsigned char c;
c = va_arg(ap,unsigned int); // unsigned char
screen_print(&scr,c);
ret = 0;
} break;
//case SYS_SCREEN_IMAGE: {
// IMAGE *image;
// image = va_arg(ap,IMAGE *);
// screen_image(&scr,image);
// ret = 0;
//} break;
case SYS_SCREEN_SET_LOCATE_X: {
unsigned long int x;
x = va_arg(ap,unsigned long int);
screen_set_locate_x(&scr,x);
ret = 0;
} break;
case SYS_SCREEN_SET_LOCATE_Y: {
unsigned long int y;
y = va_arg(ap,unsigned long int);
screen_set_locate_y(&scr,y);
ret = 0;
} break;
case SYS_SCREEN_GET_LOCATE_X: {
ret = screen_get_locate_x(&scr);
} break;
case SYS_SCREEN_GET_LOCATE_Y: {
ret = screen_get_locate_y(&scr);
} break;
case SYS_SCREEN_SET_COLOR_FG: {
unsigned long int r,g,b;
r = va_arg(ap,unsigned long int);
g = va_arg(ap,unsigned long int);
b = va_arg(ap,unsigned long int);
screen_set_color_fg(&scr,r,g,b);
ret = 0;
} break;
case SYS_SCREEN_SET_COLOR_BG: {
unsigned long int r,g,b;
r = va_arg(ap,unsigned long int);
g = va_arg(ap,unsigned long int);
b = va_arg(ap,unsigned long int);
screen_set_color_bg(&scr,r,g,b);
ret = 0;
} break;
// UART
case SYS_UART_INIT: {
unsigned long int base;
unsigned long int irq;
base = va_arg(ap,unsigned long int);
irq = va_arg(ap,unsigned long int);
uart.tx.buf = uart_buffer_tx;
uart.tx.buf_size = UART_TX_BUF_SIZE;
uart.rx.buf = uart_buffer_rx;
uart.rx.buf_size = UART_RX_BUF_SIZE;
uart_init(&uart,UART_BASE,UART_IRQ);
ret = 0;
} break;
case SYS_UART_GET: {
ret = (long int)uart_get(&uart);
} break;
case SYS_UART_GET_EXIST: {
ret = (long int)uart_get_exist(&uart);
} break;
case SYS_UART_GET_CLEAR: {
uart_get_clear(&uart);
ret = 0;
} break;
case SYS_UART_PUT: {
unsigned int data;
data = va_arg(ap,unsigned int);
uart_put(&uart,(unsigned char)data);
ret = 0;
} break;
case SYS_UART_PUT_FULL: {
ret = uart_put_full(&uart);
} break;
case SYS_UART_PUT_CLEAR: {
uart_put_clear(&uart);
ret = 0;
} break;
case SYS_UART_PUT_STRING: {
unsigned char *string;
string = va_arg(ap,unsigned char *);
uart_put_string(&uart,string);
ret = 0;
} break;
case SYS_UART_IS_CTS: {
ret = uart_is_cts(&uart);
} break;
case SYS_UART_IS_DSR: {
ret = uart_is_dsr(&uart);
} break;
case SYS_UART_IS_RI: {
ret = uart_is_ri(&uart);
} break;
case SYS_UART_IS_DCD: {
ret = uart_is_dcd(&uart);
} break;
case SYS_UART_DTR: {
unsigned long int data;
data = va_arg(ap,unsigned long int);
uart_dtr(&uart,data);
ret = 0;
} break;
case SYS_UART_RTS: {
unsigned long int data;
data = va_arg(ap,unsigned long int);
uart_rts(&uart,data);
ret = 0;
} break;
}
va_end(ap);
return ret;
}
void cpu_init_f(void)
{
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile ccsr_lbc_t *memctl = &immap->im_lbc;
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
/* Clear initial global data */
memset ((void *) gd, 0, sizeof (gd_t));
#ifdef CONFIG_FSL_LAW
init_laws();
#endif
setup_bats();
/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
* addresses - these have to be modified later when FLASH size
* has been determined
*/
#if defined(CONFIG_SYS_OR0_REMAP)
memctl->or0 = CONFIG_SYS_OR0_REMAP;
#endif
#if defined(CONFIG_SYS_OR1_REMAP)
memctl->or1 = CONFIG_SYS_OR1_REMAP;
#endif
/* now restrict to preliminary range */
#if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM)
memctl->br0 = CONFIG_SYS_BR0_PRELIM;
memctl->or0 = CONFIG_SYS_OR0_PRELIM;
#endif
#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
memctl->or1 = CONFIG_SYS_OR1_PRELIM;
memctl->br1 = CONFIG_SYS_BR1_PRELIM;
#endif
#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
memctl->or2 = CONFIG_SYS_OR2_PRELIM;
memctl->br2 = CONFIG_SYS_BR2_PRELIM;
#endif
#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
memctl->or3 = CONFIG_SYS_OR3_PRELIM;
memctl->br3 = CONFIG_SYS_BR3_PRELIM;
#endif
#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
memctl->or4 = CONFIG_SYS_OR4_PRELIM;
memctl->br4 = CONFIG_SYS_BR4_PRELIM;
#endif
#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
memctl->or5 = CONFIG_SYS_OR5_PRELIM;
memctl->br5 = CONFIG_SYS_BR5_PRELIM;
#endif
#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
memctl->or6 = CONFIG_SYS_OR6_PRELIM;
memctl->br6 = CONFIG_SYS_BR6_PRELIM;
#endif
#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
memctl->or7 = CONFIG_SYS_OR7_PRELIM;
memctl->br7 = CONFIG_SYS_BR7_PRELIM;
#endif
#if defined(CONFIG_FSL_DMA)
dma_init();
#endif
/* enable the timebase bit in HID0 */
set_hid0(get_hid0() | 0x4000000);
/* enable EMCP, SYNCBE | ABE bits in HID1 */
set_hid1(get_hid1() | 0x80000C00);
}
void myinit(void)
{
#pragma message "myinit()"
#pragma message "HAL_Init()"
#pragma message "SystemClock_Config()"
HAL_Init();
SystemClock_Config();
#ifdef ENABLE_GPIO
#pragma message "led_init()"
led_init();
#ifdef btn_init
#pragma message "btn_init()"
btn_init();
#endif
#endif
#ifdef ENABLE_RNG
#pragma message "rng_init()"
rng_init();
#endif
#ifdef ENABLE_UART
#pragma message "uart_init()"
uart_init();
#endif
#ifdef ENABLE_I2C
#pragma message "i2c_init()"
i2c_init();
#endif
#ifdef ENABLE_SPI
#pragma message "spi_init()"
spi_init();
#endif
#ifdef ENABLE_TIM
#pragma message "tim_init()"
tim_init();
#endif
#ifdef ENABLE_ADC
#pragma message "adc_init()"
adc_init();
#endif
#ifdef ENABLE_CAN
#pragma message "can_init()"
can_init();
#endif
#ifdef ENABLE_DAC
#pragma message "dac_init()"
dac_init();
#endif
#ifdef ENABLE_DMA
#pragma message "dma_init()"
dma_init();
#endif
#ifdef ENABLE_FLASH
#pragma message "flash_erase_img1()"
flash_erase_img1();
#endif
#ifdef ENABLE_ETH
#pragma message "eth_init()"
eth_init();
#endif
#ifdef ENABLE_DSP
#pragma message "dsp_init()"
dsp_init();
#endif
#ifdef ENABLE_USB
#pragma message "usb_init()"
usb_init();
#endif
#ifdef ENABLE_PCL
#pragma message "pcl_init()"
pcl_init();
#endif
#ifdef ENABLE_SDIO
#pragma message "sdio_init()"
sdio_init();
#endif
#ifdef ENABLE_DISPLAY
#pragma message "display_init()"
display_init();
#endif
#ifdef ENABLE_BR
#pragma message "br_init()"
br_init();
#endif
}
int gboot_main()
{
int num;
//unsigned char buf[1024*4];
#ifdef MMU_ON
mmu_init();
#endif
uart_init();
led_init();
button_init();
init_irq();
led_off();
dma_init();
dma_start();
dm9000_init();
while(1)
{
printf("\n***************************************\n\r");
printf("\n****************MYBOOT*****************\n\r");
printf("1:Set Out a Arp Package to Get Host Ip and MAC!\n\r");
printf("2:Download Linux Kernel from TFTP Server!\n\r");
printf("3:Boot Linux from RAM!\n\r");
printf("\n Plese Select:");
scanf("%d",&num);
switch (num)
{
case 1:
arp_progress();
break;
case 2:
tftp_send_request("tftp.c");
while(FLAG_TFTP);
break;
case 3:
boot_linux();
//boot_linux_nand();
break;
default:
printf("Error: wrong selection!\n\r");
break;
}
}
return 0;
}
/*!
\brief main function
\param[in] none
\param[out] none
\retval none
*/
int main(void)
{
int i = 0;
dma_parameter_struct dma_init_struct;
/* enable DMA clock */
rcu_periph_clock_enable(RCU_DMA);
/* initialize LED */
led_config();
/* all LED off */
gd_eval_ledoff(LED1);
gd_eval_ledoff(LED3);
gd_eval_ledoff(LED2);
gd_eval_ledoff(LED4);
/* initialize DMA channel1 */
dma_deinit(DMA_CH1);
dma_init_struct.direction = DMA_PERIPHERA_TO_MEMORY;
dma_init_struct.memory_addr = (uint32_t)destination_address1;
dma_init_struct.memory_inc = DMA_MEMORY_INCREASE_ENABLE;
dma_init_struct.memory_width = DMA_MEMORY_WIDTH_8BIT;
dma_init_struct.number = DATANUM;
dma_init_struct.periph_addr = (uint32_t)source_address;
dma_init_struct.periph_inc = DMA_PERIPH_INCREASE_ENABLE;
dma_init_struct.periph_width = DMA_PERIPHERAL_WIDTH_8BIT;
dma_init_struct.priority = DMA_PRIORITY_ULTRA_HIGH;
dma_init(DMA_CH1,dma_init_struct);
/* configure DMA mode */
dma_circulation_disable(DMA_CH1);
dma_memory_to_memory_enable(DMA_CH1);
/* initialize DMA channel2 */
dma_deinit(DMA_CH2);
dma_init_struct.memory_addr = (uint32_t)destination_address2;
dma_init(DMA_CH2,dma_init_struct);
/* configure DMA mode */
dma_circulation_disable(DMA_CH2);
dma_memory_to_memory_enable(DMA_CH2);
/* initialize DMA channel3 */
dma_deinit(DMA_CH3);
dma_init_struct.memory_addr = (uint32_t)destination_address3;
dma_init(DMA_CH3,dma_init_struct);
/* configure DMA mode */
dma_circulation_disable(DMA_CH3);
dma_memory_to_memory_enable(DMA_CH3);
/* initialize DMA channel4 */
dma_deinit(DMA_CH4);
dma_init_struct.memory_addr = (uint32_t)destination_address4;
dma_init(DMA_CH4,dma_init_struct);
/* configure DMA mode */
dma_circulation_disable(DMA_CH4);
dma_memory_to_memory_enable(DMA_CH4);
/* enable DMA channel1~channel4 */
dma_channel_enable(DMA_CH1);
dma_channel_enable(DMA_CH2);
dma_channel_enable(DMA_CH3);
dma_channel_enable(DMA_CH4);
/* wait for DMA transfer complete */
for(i = 0; i < 200; i++);
/* compare the data of source_address with data of destination_address */
transferflag1 = memory_compare(source_address, destination_address1, DATANUM);
transferflag2 = memory_compare(source_address, destination_address2, DATANUM);
transferflag3 = memory_compare(source_address, destination_address3, DATANUM);
transferflag4 = memory_compare(source_address, destination_address4, DATANUM);
/* if DMA channel1 transfer success,light LED1 */
if(SUCCESS == transferflag1){
gd_eval_ledon(LED1);
}
/* if DMA channel2 transfer success,light LED2 */
if(SUCCESS == transferflag2){
gd_eval_ledon(LED2);
}
/* if DMA channel3 transfer success,light LED3 */
if(SUCCESS == transferflag3){
gd_eval_ledon(LED3);
}
/* if DMA channel4 transfer success,light LED4 */
if(SUCCESS == transferflag4){
gd_eval_ledon(LED4);
}
while (1);
}
/*---------------------------------------------------------------------------*/
int
main(void)
{
/* Hardware initialization */
bus_init();//ʱÖÓ³õʼ»¯
rtimer_init();//¼ÆʱÆ÷³õʼ»¯
/* model-specific h/w init. */
io_port_init();
/* Init LEDs here */
leds_init();//LED³õʼ»¯
/*LEDS_GREEN indicate LEDs Init finished*/
fade(LEDS_GREEN);
/* initialize process manager. */
process_init();//½ø³Ì¹ÜÀí³õʼ»¯
/* Init UART0
* Based on the EJOY MCU CC2430 Circuit Design
* */
uart0_init();//UART0´®¿Ú³õʼ»¯
#if DMA_ON
dma_init();//DMA³õʼ»¯
#endif
#if SLIP_ARCH_CONF_ENABLE
/* On cc2430, the argument is not used */
slip_arch_init(0);//SLIP³õʼ»¯
#else
uart1_set_input(serial_line_input_byte);
serial_line_init();
#endif
PUTSTRING("##########################################\n");
putstring(CONTIKI_VERSION_STRING "\n");
// putstring(SENSINODE_MODEL " (CC24");
puthex(((CHIPID >> 3) | 0x20));
putstring("-" FLASH_SIZE ")\n");
#if STARTUP_VERBOSE
#ifdef HAVE_SDCC_BANKING
PUTSTRING(" With Banking.\n");
#endif /* HAVE_SDCC_BANKING */
#ifdef SDCC_MODEL_LARGE
PUTSTRING(" --model-large\n");
#endif /* SDCC_MODEL_LARGE */
#ifdef SDCC_MODEL_HUGE
PUTSTRING(" --model-huge\n");
#endif /* SDCC_MODEL_HUGE */
#ifdef SDCC_STACK_AUTO
PUTSTRING(" --stack-auto\n");
#endif /* SDCC_STACK_AUTO */
PUTCHAR('\n');
PUTSTRING(" Net: ");
PUTSTRING(NETSTACK_NETWORK.name);
PUTCHAR('\n');
PUTSTRING(" MAC: ");
PUTSTRING(NETSTACK_MAC.name);
PUTCHAR('\n');
PUTSTRING(" RDC: ");
PUTSTRING(NETSTACK_RDC.name);
PUTCHAR('\n');
PUTSTRING("##########################################\n");
#endif
watchdog_init();//¿´ÃŹ·³õʼ»¯
/* Initialise the cc2430 RNG engine. */
random_init(0);//Ëæ»úÊýÉú³ÉÆ÷³õʼ»¯
/* start services */
process_start(&etimer_process, NULL);//
ctimer_init();//ctimer³õʼ»¯
/* initialize the netstack */
netstack_init();//ÍøÂçµ×²ãÕ»³õʼ»¯
set_rime_addr();//rimeµØÖ·ÉèÖÃ
//there is no sensor for us maintenance
#if BUTTON_SENSOR_ON || ADC_SENSOR_ON
process_start(&sensors_process, NULL);
sensinode_sensors_activate();
#endif
//IPV6,YES!
#if UIP_CONF_IPV6
memcpy(&uip_lladdr.addr, &rimeaddr_node_addr, sizeof(uip_lladdr.addr));
queuebuf_init();
process_start(&tcpip_process, NULL);
//DISCO
#if DISCO_ENABLED
process_start(&disco_process, NULL);
#endif /* DISCO_ENABLED */
//VIZTOOL
#if VIZTOOL_CONF_ON
process_start(&viztool_process, NULL);
#endif
#if (!UIP_CONF_IPV6_RPL)
{
uip_ipaddr_t ipaddr;
uip_ip6addr(&ipaddr, 0x2001, 0x630, 0x301, 0x6453, 0, 0, 0, 0);
uip_ds6_set_addr_iid(&ipaddr, &uip_lladdr);
uip_ds6_addr_add(&ipaddr, 0, ADDR_TENTATIVE);
}
#endif /* UIP_CONF_IPV6_RPL */
#endif /* UIP_CONF_IPV6 */
/*
* Acknowledge the UART1 RX interrupt
* now that we're sure we are ready to process it
*
* We don't need it. by MW
*/
// model_uart_intr_en();
energest_init();
ENERGEST_ON(ENERGEST_TYPE_CPU);
fade(LEDS_RED);
#if BATMON_CONF_ON
process_start(&batmon_process, NULL);
#endif
autostart_start(autostart_processes);
watchdog_start();
while(1) {
do {
/* Reset watchdog and handle polls and events */
watchdog_periodic();
/**/
#if !CLOCK_CONF_ACCURATE
if(sleep_flag) {
if(etimer_pending() &&
(etimer_next_expiration_time() - count - 1) > MAX_TICKS) { /*core/sys/etimer.c*/
etimer_request_poll();
}
sleep_flag = 0;
}
#endif
r = process_run();
} while(r > 0);
#if SHORTCUTS_CONF_NETSTACK
len = NETSTACK_RADIO.pending_packet();
if(len) {
packetbuf_clear();
len = NETSTACK_RADIO.read(packetbuf_dataptr(), PACKETBUF_SIZE);
if(len > 0) {
packetbuf_set_datalen(len);
NETSTACK_RDC.input();
}
}
#endif
#if LPM_MODE
#if (LPM_MODE==LPM_MODE_PM2)
SLEEP &= ~OSC_PD; /* Make sure both HS OSCs are on */
while(!(SLEEP & HFRC_STB)); /* Wait for RCOSC to be stable */
CLKCON |= OSC; /* Switch to the RCOSC */
while(!(CLKCON & OSC)); /* Wait till it's happened */
SLEEP |= OSC_PD; /* Turn the other one off */
#endif /* LPM_MODE==LPM_MODE_PM2 */
/*
* Set MCU IDLE or Drop to PM1. Any interrupt will take us out of LPM
* Sleep Timer will wake us up in no more than 7.8ms (max idle interval)
*/
SLEEP = (SLEEP & 0xFC) | (LPM_MODE - 1);
#if (LPM_MODE==LPM_MODE_PM2)
/*
* Wait 3 NOPs. Either an interrupt occurred and SLEEP.MODE was cleared or
* no interrupt occurred and we can safely power down
*/
__asm
nop
nop
nop
__endasm;
if (SLEEP & SLEEP_MODE0) {
#endif /* LPM_MODE==LPM_MODE_PM2 */
ENERGEST_OFF(ENERGEST_TYPE_CPU);
ENERGEST_ON(ENERGEST_TYPE_LPM);
/* We are only interested in IRQ energest while idle or in LPM */
ENERGEST_IRQ_RESTORE(irq_energest);
/* Go IDLE or Enter PM1 */
PCON |= IDLE;
/* First instruction upon exiting PM1 must be a NOP */
__asm
nop
__endasm;
/* Remember energest IRQ for next pass */
ENERGEST_IRQ_SAVE(irq_energest);
ENERGEST_ON(ENERGEST_TYPE_CPU);
ENERGEST_OFF(ENERGEST_TYPE_LPM);
#if (LPM_MODE==LPM_MODE_PM2)
SLEEP &= ~OSC_PD; /* Make sure both HS OSCs are on */
while(!(SLEEP & XOSC_STB)); /* Wait for XOSC to be stable */
CLKCON &= ~OSC; /* Switch to the XOSC */
/*
* On occasion the XOSC is reported stable when in reality it's not.
* We need to wait for a safeguard of 64us or more before selecting it
*/
clock_delay(10);
while(CLKCON & OSC); /* Wait till it's happened */
}
#endif /* LPM_MODE==LPM_MODE_PM2 */
#endif /* LPM_MODE */
}
}
uint8_t Sd2Card::init() {
// chipSelectPin_ = SS;
// SPI.begin();
errorCode_ = inBlock_ = partialBlockRead_ = type_ = 0;
#ifdef SPI_DMA
//init DMA
dma_init(DMA1);
//enable SPI over DMA
spi_rx_dma_enable(SPI1);
spi_tx_dma_enable(SPI1);
//DMA activity control
dmaActive = false;
//Acknowledgment array
for(int i=0; i<SPI_BUFF_SIZE; i++)
ack[i] = 0xFF;
#endif
//chipSelectPin_ = chipSelectPin;
// 16-bit init start time allows over a minute
uint16_t t0 = (uint16_t)millis();
uint32_t arg;
// SPIn = s;
// set pin modes
/* pinMode(chipSelectPin_, OUTPUT);
chipSelectHigh();
pinMode(SPI_MISO_PIN, INPUT);
pinMode(SPI_MOSI_PIN, OUTPUT);
pinMode(SPI_SCK_PIN, OUTPUT);
*/
// SS must be in output mode even it is not chip select
// pinMode(SS_PIN, OUTPUT);
// Enable SPI, Master, clock rate f_osc/128
// SPCR = (1 << SPE) | (1 << MSTR) | (1 << SPR1) | (1 << SPR0);
// clear double speed
// SPSR &= ~(1 << SPI2X);
// must supply min of 74 clock cycles with CS high.
chipSelectHigh();
for (uint8_t i = 0; i < 10; i++) spiSend(0XFF);
chipSelectLow();
// command to go idle in SPI mode
while ((status_ = cardCommand(CMD0, 0)) != R1_IDLE_STATE) {
if (((uint16_t)millis() - t0) > SD_INIT_TIMEOUT) {
Serial.println("Error: CMD0");
error(SD_CARD_ERROR_CMD0);
goto fail;
}
}
// check SD version
if ((cardCommand(CMD8, 0x1AA) & R1_ILLEGAL_COMMAND)) {
type(SD_CARD_TYPE_SD1);
} else {
// only need last byte of r7 response
for (uint8_t i = 0; i < 4; i++) status_ = spiRec();
if (status_ != 0XAA) {
error(SD_CARD_ERROR_CMD8);
Serial.println("Error: CMD8");
goto fail;
}
type(SD_CARD_TYPE_SD2);
}
// initialize card and send host supports SDHC if SD2
arg = (type() == SD_CARD_TYPE_SD2) ? 0X40000000 : 0;
while ((status_ = cardAcmd(ACMD41, arg)) != R1_READY_STATE) {
// check for timeout
if (((uint16_t)millis() - t0) > SD_INIT_TIMEOUT) {
Serial.println("Error: ACMD41");
error(SD_CARD_ERROR_ACMD41);
goto fail;
}
}
// if SD2 read OCR register to check for SDHC card
if (type() == SD_CARD_TYPE_SD2) {
if (cardCommand(CMD58, 0)) {
Serial.println("Error: CMD58");
error(SD_CARD_ERROR_CMD58);
goto fail;
}
if ((spiRec() & 0XC0) == 0XC0) type(SD_CARD_TYPE_SDHC);
// discard rest of ocr - contains allowed voltage range
for (uint8_t i = 0; i < 3; i++) spiRec();
}
chipSelectHigh();
// return setSckRate(sckRateID);
return true;
fail:
chipSelectHigh();
Serial.println("Error: Sd2Card::init()");
return false;
}
int main(void)
{
unsigned char* loadbuffer;
int buffer_size;
int rc;
int(*kernel_entry)(void);
led_init();
clear_leds(LED_ALL);
/* NB: something in system_init() prevents H-JTAG from downloading */
/* system_init(); */
kernel_init();
/* enable_interrupt(IRQ_FIQ_STATUS); */
backlight_init();
lcd_init();
lcd_setfont(FONT_SYSFIXED);
button_init();
dma_init();
uart_init();
uart_init_device(DEBUG_UART_PORT);
/* mini2440_test(); */
/* Show debug messages if button is pressed */
int touch_data;
if(button_read_device(&touch_data) & BUTTON_MENU)
verbose = true;
printf("Rockbox boot loader");
printf("Version " RBVERSION);
rc = storage_init();
if(rc)
{
reset_screen();
error(EATA, rc, true);
}
disk_init(IF_MD(0));
rc = disk_mount_all();
if (rc<=0)
{
error(EDISK,rc, true);
}
printf("Loading firmware");
/* Flush out anything pending first */
commit_discard_idcache();
loadbuffer = (unsigned char*) 0x31000000;
buffer_size = (unsigned char*)0x31400000 - loadbuffer;
rc = load_firmware(loadbuffer, BOOTFILE, buffer_size);
if(rc <= 0)
error(EBOOTFILE, rc, true);
printf("Loaded firmware %d\n", rc);
/* storage_close(); */
system_prepare_fw_start();
commit_discard_idcache();
kernel_entry = (void*) loadbuffer;
rc = kernel_entry();
/* end stop - should not get here */
led_flash(LED_ALL, LED_NONE);
while (1); /* avoid warning */
}
/*---------------------------------------------------------------------------*/
int
main(void)
{
clock_init(); // 初始化 睡眠定时器 必要
soc_init(); // 还函数中启动了全局中断 可修改
rtimer_init(); // rtimer为定时器1 必要
/* Init LEDs here */
leds_init(); // 初始化LED 可修改
leds_off(LEDS_ALL); // 关闭所有LED 非必要
fade(LEDS_GREEN); // 绿色闪烁一下 非必要
/* initialize process manager. */
process_init(); // 任务初始化 必要
/* Init UART */
uart0_init(); // 初始化串口0，先用于调试，可修改
#if DMA_ON
dma_init(); // 非必要
#endif
#if SLIP_ARCH_CONF_ENABLE
slip_arch_init(0);
#else
uart0_set_input(serial_line_input_byte);
serial_line_init();
#endif
fade(LEDS_RED); // 红色LED闪烁一下 非必要
// 打印若干提示信息 非必要 可修改
putstring("**************************************\r\n");
putstring(CONTIKI_VERSION_STRING "\r\n"); // 打印若干信息
putstring("Platform CC2530 NB\r\n");
switch(CHIPID) {
case 0xA5:
putstring("CC2530");
break;
case 0xB5:
putstring("CC2531");
break;
case 0x95:
putstring("CC2533");
break;
case 0x8D:
putstring("CC2540");
break;
}
putstring("-F");
switch(CHIPINFO0 & 0x70) {
case 0x40:
putstring("256,");
break;
case 0x30:
putstring("128,");
break;
case 0x20:
putstring("64,");
break;
case 0x10:
putstring("32,");
break;
}
puthex(CHIPINFO1 + 1);
putstring("KB SRAM\r\n");
#if STARTUP_VERBOSE
PUTSTRING("Net: "); // NETWORK名称
PUTSTRING(NETSTACK_NETWORK.name);
PUTCHAR('\r');PUTCHAR('\n');
PUTSTRING("MAC: "); // MAC名称
PUTSTRING(NETSTACK_MAC.name);
PUTCHAR('\r');PUTCHAR('\n');
PUTSTRING("RDC: "); // RDC名称
PUTSTRING(NETSTACK_RDC.name);
PUTCHAR('\r');PUTCHAR('\n');
PUTSTRING("**************************************\r\n");
#endif
watchdog_init(); // 初始化看门狗
/* Initialise the H/W RNG engine. */
random_init(0); //
/* start services */
process_start(&etimer_process, NULL); // 启动etimer任务
ctimer_init(); // ctimer初始化
/* initialize the netstack */
netstack_init(); // NET协议栈初始化
set_rime_addr(); // 设置RIME地址，相当于设置IP地址
#if BUTTON_SENSOR_ON || ADC_SENSOR_ON
process_start(&sensors_process, NULL);
BUTTON_SENSOR_ACTIVATE();
ADC_SENSOR_ACTIVATE();
#endif
#if UIP_CONF_IPV6 // 非常重要，启动TCPIP查询任务
memcpy(&uip_lladdr.addr, &rimeaddr_node_addr, sizeof(uip_lladdr.addr));
queuebuf_init();
process_start(&tcpip_process, NULL);
#endif /* UIP_CONF_IPV6 */
#if VIZTOOL_CONF_ON
process_start(&viztool_process, NULL);
#endif
energest_init(); // 能量估计初始化，但是该功能未被打开
ENERGEST_ON(ENERGEST_TYPE_CPU); // 该功能未被打开
autostart_start(autostart_processes); // 启动被定义为自动启动的任务
watchdog_start(); // 看门狗初始化
fade(LEDS_YELLOW); // 黄色LED闪烁，完成所有初始化工作
while(1) {
do {
/* Reset watchdog and handle polls and events */
watchdog_periodic(); // 喂狗操作
r = process_run();
} while(r > 0);
#if SHORTCUTS_CONF_NETSTACK // 循环查询无线输入数据包长度 tcpip_process
len = NETSTACK_RADIO.pending_packet();
if(len) {
packetbuf_clear();
len = NETSTACK_RADIO.read(packetbuf_dataptr(), PACKETBUF_SIZE);
if(len > 0) {
packetbuf_set_datalen(len);
NETSTACK_RDC.input();
}
}
#endif
#if LPM_MODE // 该宏被定义为0，没有休眠功能，以下代码均无效
#if (LPM_MODE==LPM_MODE_PM2)
SLEEP &= ~OSC_PD; /* Make sure both HS OSCs are on */
while(!(SLEEP & HFRC_STB)); /* Wait for RCOSC to be stable */
CLKCON |= OSC; /* Switch to the RCOSC */
while(!(CLKCON & OSC)); /* Wait till it's happened */
SLEEP |= OSC_PD; /* Turn the other one off */
#endif /* LPM_MODE==LPM_MODE_PM2 */
/*
* Set MCU IDLE or Drop to PM1. Any interrupt will take us out of LPM
* Sleep Timer will wake us up in no more than 7.8ms (max idle interval)
*/
SLEEPCMD = (SLEEPCMD & 0xFC) | (LPM_MODE - 1);
#if (LPM_MODE==LPM_MODE_PM2)
/*
* Wait 3 NOPs. Either an interrupt occurred and SLEEP.MODE was cleared or
* no interrupt occurred and we can safely power down
*/
__asm
nop
nop
nop
__endasm;
if(SLEEPCMD & SLEEP_MODE0) {
#endif /* LPM_MODE==LPM_MODE_PM2 */
ENERGEST_OFF(ENERGEST_TYPE_CPU);
ENERGEST_ON(ENERGEST_TYPE_LPM);
/* We are only interested in IRQ energest while idle or in LPM */
ENERGEST_IRQ_RESTORE(irq_energest);
/* Go IDLE or Enter PM1 */
PCON |= PCON_IDLE;
/* First instruction upon exiting PM1 must be a NOP */
__asm
nop
__endasm;
/* Remember energest IRQ for next pass */
ENERGEST_IRQ_SAVE(irq_energest);
ENERGEST_ON(ENERGEST_TYPE_CPU);
ENERGEST_OFF(ENERGEST_TYPE_LPM);
#if (LPM_MODE==LPM_MODE_PM2)
SLEEPCMD &= ~SLEEP_OSC_PD; /* Make sure both HS OSCs are on */
while(!(SLEEPCMD & SLEEP_XOSC_STB)); /* Wait for XOSC to be stable */
CLKCONCMD &= ~CLKCONCMD_OSC; /* Switch to the XOSC */
/*
* On occasion the XOSC is reported stable when in reality it's not.
* We need to wait for a safeguard of 64us or more before selecting it
*/
clock_delay(10);
while(CLKCONCMD & CLKCONCMD_OSC); /* Wait till it's happened */
}
#endif /* LPM_MODE==LPM_MODE_PM2 */
#endif /* LPM_MODE */
}
}
mp_uint_t sdcard_read_blocks(uint8_t *dest, uint32_t block_num, uint32_t num_blocks) {
// check that SD card is initialised
if (sd_handle.Instance == NULL) {
return HAL_ERROR;
}
HAL_StatusTypeDef err = HAL_OK;
// check that dest pointer is aligned on a 4-byte boundary
uint8_t *orig_dest = NULL;
uint32_t saved_word;
if (((uint32_t)dest & 3) != 0) {
// Pointer is not aligned so it needs fixing.
// We could allocate a temporary block of RAM (as sdcard_write_blocks
// does) but instead we are going to use the dest buffer inplace. We
// are going to align the pointer, save the initial word at the aligned
// location, read into the aligned memory, move the memory back to the
// unaligned location, then restore the initial bytes at the aligned
// location. We should have no trouble doing this as those initial
// bytes at the aligned location should be able to be changed for the
// duration of this function call.
orig_dest = dest;
dest = (uint8_t*)((uint32_t)dest & ~3);
saved_word = *(uint32_t*)dest;
}
if (query_irq() == IRQ_STATE_ENABLED) {
// we must disable USB irqs to prevent MSC contention with SD card
uint32_t basepri = raise_irq_pri(IRQ_PRI_OTG_FS);
#if SDIO_USE_GPDMA
dma_init(&sd_rx_dma, &SDMMC_RX_DMA, &sd_handle);
sd_handle.hdmarx = &sd_rx_dma;
#endif
// make sure cache is flushed and invalidated so when DMA updates the RAM
// from reading the peripheral the CPU then reads the new data
MP_HAL_CLEANINVALIDATE_DCACHE(dest, num_blocks * SDCARD_BLOCK_SIZE);
err = HAL_SD_ReadBlocks_DMA(&sd_handle, dest, block_num, num_blocks);
if (err == HAL_OK) {
err = sdcard_wait_finished(&sd_handle, 60000);
}
#if SDIO_USE_GPDMA
dma_deinit(&SDMMC_RX_DMA);
sd_handle.hdmarx = NULL;
#endif
restore_irq_pri(basepri);
} else {
err = HAL_SD_ReadBlocks(&sd_handle, dest, block_num, num_blocks, 60000);
if (err == HAL_OK) {
err = sdcard_wait_finished(&sd_handle, 60000);
}
}
if (orig_dest != NULL) {
// move the read data to the non-aligned position, and restore the initial bytes
memmove(orig_dest, dest, num_blocks * SDCARD_BLOCK_SIZE);
memcpy(dest, &saved_word, orig_dest - dest);
}
return err;
}
test_mockable __keep int main(void)
{
#ifdef CONFIG_REPLACE_LOADER_WITH_BSS_SLOW
/*
* Now that we have started execution, we no longer need the loader.
* Instead, variables placed in the .bss.slow section will use this
* space. Therefore, clear out this region now.
*/
memset((void *)(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_LOADER_MEM_OFF), 0,
CONFIG_LOADER_SIZE);
#endif /* defined(CONFIG_REPLACE_LOADER_WITH_BSS_SLOW) */
/*
* Pre-initialization (pre-verified boot) stage. Initialization at
* this level should do as little as possible, because verified boot
* may need to jump to another image, which will repeat this
* initialization. In particular, modules should NOT enable
* interrupts.
*/
#ifdef CONFIG_BOARD_PRE_INIT
board_config_pre_init();
#endif
#ifdef CONFIG_MPU
mpu_pre_init();
#endif
/* Configure the pin multiplexers and GPIOs */
jtag_pre_init();
gpio_pre_init();
#ifdef CONFIG_BOARD_POST_GPIO_INIT
board_config_post_gpio_init();
#endif
/*
* Initialize interrupts, but don't enable any of them. Note that
* task scheduling is not enabled until task_start() below.
*/
task_pre_init();
/*
* Initialize the system module. This enables the hibernate clock
* source we need to calibrate the internal oscillator.
*/
system_pre_init();
system_common_pre_init();
#ifdef CONFIG_FLASH
/*
* Initialize flash and apply write protect if necessary. Requires
* the reset flags calculated by system initialization.
*/
flash_pre_init();
#endif
#if defined(CONFIG_CASE_CLOSED_DEBUG)
/*
* If the device is locked we assert PD_NO_DEBUG, preventing the EC
* from interfering with the AP's access to the SPI flash.
* The PD_NO_DEBUG signal is latched in hardware, so changing this
* GPIO later has no effect.
*/
gpio_set_level(GPIO_PD_DISABLE_DEBUG, system_is_locked());
#endif
/* Set the CPU clocks / PLLs. System is now running at full speed. */
clock_init();
/*
* Initialize timer. Everything after this can be benchmarked.
* get_time() and udelay() may now be used. usleep() requires task
* scheduling, so cannot be used yet. Note that interrupts declared
* via DECLARE_IRQ() call timer routines when profiling is enabled, so
* timer init() must be before uart_init().
*/
timer_init();
/* Main initialization stage. Modules may enable interrupts here. */
cpu_init();
#ifdef CONFIG_DMA
/* Initialize DMA. Must be before UART. */
dma_init();
#endif
/* Initialize UART. Console output functions may now be used. */
uart_init();
if (system_jumped_to_this_image()) {
CPRINTS("UART initialized after sysjump");
} else {
CPUTS("\n\n--- UART initialized after reboot ---\n");
CPUTS("[Reset cause: ");
system_print_reset_flags();
CPUTS("]\n");
}
CPRINTF("[Image: %s, %s]\n",
system_get_image_copy_string(), system_get_build_info());
#ifdef CONFIG_BRINGUP
ccprintf("\n\nWARNING: BRINGUP BUILD\n\n\n");
#endif
#ifdef CONFIG_WATCHDOG
/*
* Intialize watchdog timer. All lengthy operations between now and
* task_start() must periodically call watchdog_reload() to avoid
* triggering a watchdog reboot. (This pretty much applies only to
* verified boot, because all *other* lengthy operations should be done
* by tasks.)
*/
watchdog_init();
#endif
/*
* Verified boot needs to read the initial keyboard state and EEPROM
* contents. EEPROM must be up first, so keyboard_scan can toggle
* debugging settings via keys held at boot.
*/
#ifdef CONFIG_EEPROM
eeprom_init();
#endif
#ifdef HAS_TASK_KEYSCAN
keyboard_scan_init();
#endif
#ifdef CONFIG_RWSIG
/*
* Check the RW firmware signature
* and eventually jump to it if it is good.
*/
check_rw_signature();
#endif
/*
* Print the init time. Not completely accurate because it can't take
* into account the time before timer_init(), but it'll at least catch
* the majority of the time.
*/
CPRINTS("Inits done");
/* Launch task scheduling (never returns) */
return task_start();
}
/**
****************************************************************************************
* @brief Initialize the UART to default values.
* @param[in] UART QN_UART0 or QN_UART1
* @param[in] uartclk USARTx_CLK(div)
* @param[in] baudrate baud rate
* @description
* This function is used to initialize UART, it consists of baud-rate, parity, data-bits, stop-bits,
* over sample rate and bit order. The function is also used to enable specified UART interrupt, and
* enable NVIC UART IRQ.
*****************************************************************************************
*/
void uart_init(QN_UART_TypeDef *UART, uint32_t uartclk, enum UART_BAUDRATE baudrate)
{
// UART0 and UART1 are arranged in cross over configuration
uint32_t reg;
struct uart_env_tag *uart_env = &uart0_env;
uart_clock_on(UART);
// Set UART baudrate
#if UART_BAUDRATE_TABLE_EN==TRUE
reg = (uart_divider[baudrate].integer_h << (UART_POS_DIVIDER_INT + 8))
| (uart_divider[baudrate].integer_l << UART_POS_DIVIDER_INT)
| uart_divider[baudrate].fractional;
uart_uart_SetBaudDivider(UART, reg);
#else
uart_baudrate_set(UART, uartclk, UART_OVS16, baudrate);
#endif
#if CONFIG_ENABLE_DRIVER_UART0==TRUE
if (UART == QN_UART0) {
/*
* Set UART config:
*
* - oversample rate is 16
* - HW flow control disable
* - 1 stop bit
* - parity type unused
* - no parity
* - bitorder = LSB
*/
reg = UART_MASK_UART_EN // uart enable
| UART_MASK_UART_IE // uart int enable
//| UART_MASK_CTS_EN
//| UART_MASK_RTS_EN
| UART_OVS16
| UART_MASK_LEVEL_INV
| UART_MASK_BIT_ORDER;
uart_env = &uart0_env;
#if CONFIG_UART0_TX_ENABLE_INTERRUPT==TRUE && UART_TX_DMA_EN==FALSE
// Enable the UART0 TX Interrupt
NVIC_EnableIRQ(UART0_TX_IRQn);
#endif
#if CONFIG_UART0_RX_ENABLE_INTERRUPT==TRUE && UART_RX_DMA_EN==FALSE
// Enable the UART0 RX Interrupt
NVIC_EnableIRQ(UART0_RX_IRQn);
#endif
}
#endif
#if CONFIG_ENABLE_DRIVER_UART1==TRUE
if (UART == QN_UART1) {
/*
* Set UART config:
*
* - oversample rate is 16
* - HW flow control disable
* - 1 stop bit
* - parity type unused
* - no parity
* - bitorder = LSB
*/
reg = UART_MASK_UART_EN // uart enable
| UART_MASK_UART_IE // uart int enable
| UART_OVS16
| UART_MASK_LEVEL_INV
| UART_MASK_BIT_ORDER;
uart_env = &uart1_env;
#if CONFIG_UART1_TX_ENABLE_INTERRUPT==TRUE && UART_TX_DMA_EN==FALSE
// Enable the UART1 TX Interrupt
NVIC_EnableIRQ(UART1_TX_IRQn);
#endif
#if CONFIG_UART1_RX_ENABLE_INTERRUPT==TRUE && UART_RX_DMA_EN==FALSE
// Enable the UART1 RX Interrupt
NVIC_EnableIRQ(UART1_RX_IRQn);
#endif
}
#endif
// Set UART config
uart_uart_SetCR(UART, reg);
#if UART_DMA_EN==TRUE
dma_init();
#endif
//Configure UART environment
uart_env->rx.size = 0;
uart_env->tx.size = 0;
uart_env->rx.bufptr = NULL;
uart_env->tx.bufptr = NULL;
#if UART_CALLBACK_EN==TRUE
uart_env->rx.callback = NULL;
uart_env->tx.callback = NULL;
#endif
}
int gboot_main()
{
int num;
//unsigned char buf[1024*4];
#ifdef MMU_ON
mmu_init();
#endif
uart_init();
led_init();
button_init();
//init_irq();
led_on();
dma_init();
dma_start();
/*
NF_Erase(128*1+1);
buf[0] = 100;
NF_WritePage(128*1+1,buf);
buf[0] = 10;
NF_PageRead(128*1+1,buf);
if( buf[0] == 100 )
led_on();
*/
//putc(0x0d);
//putc(0x0a);
//putc('H');
//uart_send_string(buff);
//printf("Hello GBOOT!\n");
while(1)
{
//getc();
printf("\n\r***************************************\n\r");
printf("\n\r*****************GBOOT*****************\n\r");
printf("1:Download Linux Kernel from TFTP Server!\n\r");
printf("2:Boot Linux from RAM!\n\r");
printf("3:Boor Linux from Nand Flash!\n\r");
printf("\n Plese Select:");
scanf("%d",&num);
switch (num)
{
case 1:
//tftp_load();
break;
case 2:
//boot_linux_ram();
break;
case 3:
//boot_linux_nand();
break;
default:
printf("Error: wrong selection!\n\r");
break;
}
}
return 0;
}
void board_init(int with_irq)
{
/* Disable watchdog (compal loader leaves it enabled) */
wdog_enable(0);
/* Configure memory interface */
calypso_mem_cfg(CALYPSO_nCS0, 3, CALYPSO_MEM_16bit, 1);
calypso_mem_cfg(CALYPSO_nCS1, 3, CALYPSO_MEM_16bit, 1);
calypso_mem_cfg(CALYPSO_nCS2, 5, CALYPSO_MEM_16bit, 1);
calypso_mem_cfg(CALYPSO_nCS3, 5, CALYPSO_MEM_16bit, 1);
calypso_mem_cfg(CALYPSO_CS4, 0, CALYPSO_MEM_8bit, 1);
calypso_mem_cfg(CALYPSO_nCS6, 0, CALYPSO_MEM_32bit, 1);
calypso_mem_cfg(CALYPSO_nCS7, 0, CALYPSO_MEM_32bit, 0);
/* Set VTCXO_DIV2 = 1, configure PLL for 104 MHz and give ARM half of that */
calypso_clock_set(2, CALYPSO_PLL13_104_MHZ, ARM_MCLK_DIV_2);
/* Configure the RHEA bridge with some sane default values */
calypso_rhea_cfg(0, 0, 0xff, 0, 1, 0, 0);
/* Initialize board-specific GPIO */
board_io_init();
/* Enable bootrom mapping to route exception vectors to RAM */
calypso_bootrom(with_irq);
calypso_exceptions_install();
/* Initialize interrupt controller */
if (with_irq)
irq_init();
sercomm_bind_uart(UART_MODEM);
cons_bind_uart(UART_IRDA);
/* initialize MODEM UART to be used for sercomm */
uart_init(UART_MODEM, with_irq);
uart_baudrate(UART_MODEM, UART_115200);
/* initialize IRDA UART to be used for old-school console code.
* note: IRDA uart only accessible on C115 and C117 PCB */
uart_init(UART_IRDA, with_irq);
uart_baudrate(UART_IRDA, UART_115200);
/* Initialize hardware timers */
hwtimer_init();
/* Initialize DMA controller */
dma_init();
/* Initialize real time clock */
rtc_init();
/* Initialize system timers (uses hwtimer 2) */
timer_init();
/* Initialize LCD driver (uses UWire) */
fb_init();
bl_mode_pwl(1);
bl_level(0);
/* Initialize keypad driver */
keypad_init(keymap, with_irq);
/* Initialize ABB driver (uses SPI) */
twl3025_init();
/* enable LEDB driver of Iota for keypad backlight */
twl3025_reg_write(AUXLED, 0x02);
}
int gboot_main()
{
int num;
#ifdef MMU_ON
mmu_init();
#endif
led_init();
button_init();
init_irq();
led_on();
uart_init();
dma_init();
dma_start();
/*
putc(0x0d);
putc(0x0a);
putc('H');
*/
//uart_send_string(buf);
//putc('A');
while(1)
{
//getc();
printf("\n\r***************************************\n\r");
printf("\n\r*****************GBOOT*****************\n\r");
printf("1:Download Linux Kernel from TFTP Server!\n\r");
printf("2:Boot Linux from RAM!\n\r");
printf("3:Boor Linux from Nand Flash!\n\r");
printf("\n Plese Select:");
scanf("%d",&num);
switch (num)
{
case 1:
//tftp_load();
break;
case 2:
//boot_linux_ram();
break;
case 3:
//boot_linux_nand();
break;
default:
printf("Error: wrong selection!\n\r");
break;
}
}
return 0;
}
