int main(void)
{
INTR_DISABLE; /* 割込み無効にする */
#ifdef SIMULATOR
extern int bss_start, ebss;
memset(&bss_start, 0, (long)&ebss - (long)&bss_start);
/* ソフトウエア・割り込みベクタを初期化する */
softvec_init();
/* シリアルの初期化 */
serial_init(SERIAL_DEFAULT_DEVICE);
#if 0
/* DRAMの初期化 */
dram_init();
#endif
#endif
puts("kozos boot succeed!\n");
/* OSの動作開始 */
kz_start(start_threads, "idle", 0, 0x100, 0, NULL);
/* ここには戻ってこない */
return 0;
}
static int init_func_ram(void)
{
if ((gd->ram_size = dram_init()) > 0)
return 0;
return 1;
}
int board_early_init_f(void)
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_TSEC_ENET
/* clear BD & FR bits for BE BD's and frame data */
clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
#endif
#ifdef CONFIG_FSL_IFC
init_early_memctl_regs();
#endif
arch_soc_init();
#if defined(CONFIG_DEEP_SLEEP)
if (is_warm_boot()) {
timer_init();
dram_init();
}
#endif
return 0;
}
void board_init_f(ulong dummy)
{
/* Set global data pointer */
gd = &gdata;
/* Clear global data */
memset((void *)gd, 0, sizeof(gd_t));
#ifdef CONFIG_LS2085A
arch_cpu_init();
#endif
#ifdef CONFIG_FSL_IFC
init_early_memctl_regs();
#endif
board_early_init_f();
timer_init();
#ifdef CONFIG_LS2085A
env_init();
#endif
get_clocks();
preloader_console_init();
#ifdef CONFIG_SPL_I2C_SUPPORT
i2c_init_all();
#endif
dram_init();
/* Clear the BSS */
memset(__bss_start, 0, __bss_end - __bss_start);
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();
#endif
board_init_r(NULL, 0);
}
/*
* Description: dram init main entry
* Parameters :
* Return :
* Note :
*/
unsigned int dram_main(void)
{
unsigned int ch;
unsigned int freq;
unsigned int bSRX = 0;
/* used for DDR Test Tool */
if (0xEF08A53C == pPMU_Reg->PMU_PMU_SYS_REG[0])
goto error;
/*
* increase emmc speed
* emmc sel GPLL, div 12
*/
g_cruReg->CRU_CLKSEL_CON[12] = ((((0x3F<<8)|(3<<14))<<16)
| (11<<8)|(1<<14));
printk(BIOS_DEBUG, "DDR Version 1.00 20140512\n");
printk(BIOS_DEBUG, "In\n");
if (-1 != dram_is_SelfRefresh()) {
printk(BIOS_DEBUG, "SRX\n");
bSRX = 1;
}
freq = 300;
rkclk_set_ddr_freq(freq);
ddr_timing_init(freq);
for (ch = 0; ch < CHANNEL_CNT; ch++) {
pChInfo = &g_ChInfo[ch];
/* printk(BIOS_DEBUG, "Channel ");
* printk(BIOS_DEBUG, ch ? "b: " : "a: ");
* print_ddr_type(pChInfo->dramType);
*/
if (-1 == dram_init(freq)) {
printk(BIOS_DEBUG, "init failed\n");
goto error;
}
get_ch_cap_info(ch);
/* print_ddr_info(); */
}
dram_all_config();
if (!bSRX) {
if (-1 == test())
goto error;
}
printk(BIOS_DEBUG, "OUT\n");
return 0;
error:
printk(BIOS_DEBUG, "ERR\n");
return 1;
}
void test_dram_init(u8 expect_id)
{
int ret;
if ((ret = dram_init(expect_id, -1)) != IAPETUS_ERR_OK)
{
do_tests_error(ret, "dram init failed");
return;
}
stage_status = STAGESTAT_DONE;
}
/*
* Miscellaneous late-boot configurations
*
* If a VSC7385 microcode image is present, then upload it.
*/
int misc_init_r(void)
{
int rc = 0;
#ifdef CONFIG_VSC7385_IMAGE
if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
CONFIG_VSC7385_IMAGE_SIZE)) {
puts("Failure uploading VSC7385 microcode.\n");
rc = 1;
}
#endif
return rc;
}
#if defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
return 0;
}
#endif
#else /* CONFIG_SPL_BUILD */
void board_init_f(ulong bootflag)
{
board_early_init_f();
NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
puts("NAND boot... ");
timer_init();
dram_init();
relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd,
CONFIG_SYS_NAND_U_BOOT_RELOC);
}
void plat_rockchip_soc_init(void)
{
secure_timer_init();
secure_sgrf_init();
secure_sgrf_ddr_rgn_init();
soc_global_soft_reset_init();
plat_rockchip_gpio_init();
m0_init();
dram_init();
dram_dfs_init();
}
void board_init_f(ulong dummy)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
unsigned int major;
#ifdef CONFIG_NAND_BOOT
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
u32 porsr1, pinctl;
/*
* There is LS1 SoC issue where NOR, FPGA are inaccessible during
* NAND boot because IFC signals > IFC_AD7 are not enabled.
* This workaround changes RCW source to make all signals enabled.
*/
porsr1 = in_be32(&gur->porsr1);
pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
DCFG_CCSR_PORSR1_RCW_SRC_I2C);
out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
pinctl);
#endif
/* Clear the BSS */
memset(__bss_start, 0, __bss_end - __bss_start);
#ifdef CONFIG_FSL_IFC
init_early_memctl_regs();
#endif
get_clocks();
#if defined(CONFIG_DEEP_SLEEP)
if (is_warm_boot())
fsl_dp_disable_console();
#endif
preloader_console_init();
#ifdef CONFIG_SPL_I2C_SUPPORT
i2c_init_all();
#endif
major = get_soc_major_rev();
if (major == SOC_MAJOR_VER_1_0)
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
dram_init();
/* Allow OCRAM access permission as R/W */
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();
#endif
board_init_r(NULL, 0);
}
void board_init_r(gd_t *gd, ulong dest_addr)
{
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *)CONFIG_SPL_GD_ADDR;
bd_t *bd;
memset(gd, 0, sizeof(gd_t));
bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
memset(bd, 0, sizeof(bd_t));
gd->bd = bd;
bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
bd->bi_memsize = CONFIG_SYS_L2_SIZE;
arch_cpu_init();
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
gd->flags |= GD_FLG_FULL_MALLOC_INIT;
#ifndef CONFIG_SPL_NAND_BOOT
env_init();
#endif
#ifdef CONFIG_SPL_MMC_BOOT
mmc_initialize(bd);
#endif
/* relocate environment function pointers etc. */
#ifdef CONFIG_SPL_NAND_BOOT
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
(uchar *)CONFIG_ENV_ADDR);
gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
gd->env_valid = ENV_VALID;
#else
env_relocate();
#endif
i2c_init_all();
dram_init();
#ifdef CONFIG_SPL_NAND_BOOT
puts("\nTertiary program loader running in sram...");
#else
puts("\nSecond program loader running in sram...");
#endif
#ifdef CONFIG_SPL_MMC_BOOT
mmc_boot();
#elif defined(CONFIG_SPL_SPI_BOOT)
fsl_spi_boot();
#elif defined(CONFIG_SPL_NAND_BOOT)
nand_boot();
#endif
}
int board_early_init_f(void)
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
unsigned int major;
#ifdef CONFIG_TSEC_ENET
/* clear BD & FR bits for BE BD's and frame data */
clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
#endif
#ifdef CONFIG_FSL_IFC
init_early_memctl_regs();
#endif
#ifdef CONFIG_FSL_DCU_FB
out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
#endif
#ifdef CONFIG_FSL_QSPI
out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
#endif
/* Configure Little endian for SAI, ASRC and SPDIF */
out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE);
/*
* Enable snoop requests and DVM message requests for
* Slave insterface S4 (A7 core cluster)
*/
out_le32(&cci->slave[4].snoop_ctrl,
CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
major = get_soc_major_rev();
if (major == SOC_MAJOR_VER_1_0) {
/*
* Set CCI-400 Slave interface S1, S2 Shareable Override
* Register All transactions are treated as non-shareable
*/
out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
}
#if defined(CONFIG_DEEP_SLEEP)
if (is_warm_boot()) {
timer_init();
dram_init();
}
#endif
return 0;
}
s32 os_main(u32 sp)
{
struct __os_task__ *ptask;
int_init();
uart_init();
dram_init();
timer_init();
mmc_init();
PRINT_INFO("%s\n", sys_banner);
coretimer_init();
task_init();
semaphore_init();
PRINT_INFO("cpu_mode: %s; lr: 0x%x; sp: 0x%x; cpsr: 0x%x\n",
get_cpu_mode(NULL), __get_lr(), sp, __get_cpsr());
gpio_set_function(GPIO_16, OUTPUT);
gpio_set_output(GPIO_16, 0);
/* set_log_level(LOG_DEBUG); */
/* create idle task */
if ((ptask = tcb_alloc()) == NULL) {
panic();
}
tcb_init(ptask, idle_task, 0, 256);
/*os_ready_insert(ptask);*/
current_task = &tcb[IDLE_TASK_ID]; /* assume that this is idle_task */
/* create main task */
if ((ptask = tcb_alloc()) == NULL) {
panic();
}
tcb_init(ptask, main_task, 0, 100);
os_ready_insert(ptask);
/* 'slip into idle task', cause the os_main() is not a task (it's the god code of system) */
__set_sp(&(task_stack[0][TASK_STK_SIZE]));
current_task->state = TASK_RUNNING;
idle_task(0);
kassert(0);
return 0;
}
void board_init_f(ulong dummy)
{
/* Clear global data */
memset((void *)gd, 0, sizeof(gd_t));
board_early_init_f();
timer_init();
#ifdef CONFIG_ARCH_LS2080A
env_init();
#endif
get_clocks();
preloader_console_init();
spl_set_bd();
#ifdef CONFIG_SPL_I2C_SUPPORT
i2c_init_all();
#endif
dram_init();
#ifdef CONFIG_SPL_FSL_LS_PPA
#ifndef CONFIG_SYS_MEM_RESERVE_SECURE
#error Need secure RAM for PPA
#endif
/*
* Secure memory location is determined in dram_init_banksize().
* gd->ram_size is deducted by the size of secure ram.
*/
dram_init_banksize();
/*
* After dram_init_bank_size(), we know U-Boot only uses the first
* memory bank regardless how big the memory is.
*/
gd->ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
/*
* If PPA is loaded, U-Boot will resume running at EL2.
* Cache and MMU will be enabled. Need a place for TLB.
* U-Boot will be relocated to the end of available memory
* in first bank. At this point, we cannot know how much
* memory U-Boot uses. Put TLB table lower by SPL_TLB_SETBACK
* to avoid overlapping. As soon as the RAM version U-Boot sets
* up new MMU, this space is no longer needed.
*/
gd->ram_top -= SPL_TLB_SETBACK;
gd->arch.tlb_size = PGTABLE_SIZE;
gd->arch.tlb_addr = (gd->ram_top - gd->arch.tlb_size) & ~(0x10000 - 1);
gd->arch.tlb_allocated = gd->arch.tlb_addr;
#endif /* CONFIG_SPL_FSL_LS_PPA */
}
/*
* SPL version of board_init_f()
*/
void board_init_f(ulong bootflag)
{
end_align = (u32)__spl_flash_end;
/*
* On MPC5200, the initial RAM (and gd) is located in the internal
* SRAM. So we can actually call the preloader console init code
* before calling dram_init(). This makes serial output (printf)
* available very early, even before SDRAM init, which has been
* an U-Boot priciple from day 1.
*/
/*
* Init global_data pointer. Has to be done before calling
* get_clocks(), as it stores some clock values into gd needed
* later on in the serial driver.
*/
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
/* Clear initial global data */
memset((void *)gd, 0, sizeof(gd_t));
/*
* get_clocks() needs to be called so that the serial driver
* works correctly
*/
get_clocks();
/*
* Do rudimental console / serial setup
*/
preloader_console_init();
/*
* First we need to initialize the SDRAM, so that the real
* U-Boot or the OS (Linux) can be loaded
*/
dram_init();
/* Clear bss */
memset(__bss_start, '\0', __bss_end - __bss_start);
/*
* Call board_init_r() (SPL framework version) to load and boot
* real U-Boot or OS
*/
board_init_r(NULL, 0);
/* Does not return!!! */
}
/*
* Early hardware init.
*/
int board_init(void)
{
int rv;
#if defined(CONFIG_SYS_BOARD_UCL_BSB)
rv = pwr_setup_gpio();
if (rv)
printf("WARN: pwr_setup_gpio() error %d\n", rv);
#endif
rv = fmc_fsmc_setup_gpio();
if (rv)
return rv;
#if !defined(CONFIG_SYS_NO_FLASH)
# if defined(CONFIG_ENV_IS_IN_FLASH)
/*
* We may sometimes got fixed garbage from NOR flash if access it after
* a sw reset and before external SDRAM initializion complete.
* Erratas say nothing about this, so we just initialize SDRAM earlier
* if want to access NOR to get environment.
*/
dram_init();
# endif /* CONFIG_ENV_IS_IN_FLASH */
if ((rv = fsmc_nor_psram_init(CONFIG_SYS_FLASH_CS,
CONFIG_SYS_FSMC_FLASH_BCR,
CONFIG_SYS_FSMC_FLASH_BTR,
CONFIG_SYS_FSMC_FLASH_BWTR))) {
goto Done;
}
#endif
#if defined(CONFIG_VIDEO_STM32F4_LTDC) && !defined(CONFIG_SYS_STM32F769I_DISCO)
rv = ltdc_setup_iomux();
if (rv)
return rv;
#endif /* CONFIG_VIDEO_STM32F4_LTDC */
rv = qspi_setup_iomux();
if (rv)
return rv;
Done:
return 0;
}
void platform_init_mmu_mappings(void)
{
/* configure available RAM banks */
dram_init();
/* Enable D-cache */
#if 1
unsigned int addr;
//unsigned int i = 0;
unsigned int dram_size = 0;
dram_size = memory_size();
for (addr = 0; addr < dram_size; addr += (1024*1024))
{
/*virtual to physical 1-1 mapping*/
arm_mmu_map_section(bi_dram[0].start+addr,bi_dram[0].start+addr, MMU_MEMORY_TYPE_NORMAL_WRITE_BACK_ALLOCATE | MMU_MEMORY_AP_READ_WRITE);
}
#endif
}
void spl_board_init(void)
{
#if 0
int i;
u32 const *regs ;
int num_regs;
unsigned char mac_address[6];
imx_get_mac_from_fuse(0,mac_address);
printf("ethaddr: %pM\n", mac_address);
if (is_cpu_type(MXC_CPU_MX6Q)) {
#if 1
regs = mx6q_1g;
num_regs = ARRAY_SIZE(mx6q_1g);
#else
regs = mx6q_2g;
num_regs = ARRAY_SIZE(mx6q_2g);
#endif
} else {
#if CONFIG_DDR_MB == 512
regs = mx6dl_512m;
num_regs = ARRAY_SIZE(mx6dl_512m);
printf("Configuring for 512MiB narrow memory bus\n");
#elif CONFIG_DDR_MB == 1024
regs = mx6dl_1gn;
num_regs = ARRAY_SIZE(mx6dl_1gn);
printf("Configuring for 1GiB narrow memory bus\n");
#elif CONFIG_DDR_MB == 2048
regs = mx6dl_2g;
num_regs = ARRAY_SIZE(mx6dl_2g);
printf("Configuring for 2GiB wide memory bus\n");
#endif
}
for (i=0; i < num_regs; i+=2) {
writel(regs[i+1],regs[i]);
}
dram_init();
#endif
printf("%s\n", __func__);
}
static int init(void)
{
/* 以下はリンカ・スクリプトで定義してあるシンボル */
extern int erodata, data_start, edata, bss_start, ebss;
/*
* データ領域とBSS領域を初期化する．この処理以降でないと，
* グローバル変数が初期化されていないので注意．
*/
memcpy(&data_start, &erodata, (long)&edata - (long)&data_start);
memset(&bss_start, 0, (long)&ebss - (long)&bss_start);
/* ソフトウエア・割り込みベクタを初期化する */
softvec_init();
/* シリアルの初期化 */
serial_init(SERIAL_DEFAULT_DEVICE);
/* DRAMの初期化 */
dram_init();
return 0;
}
void board_init_r(gd_t *gd, ulong dest_addr)
{
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *)CONFIG_SPL_GD_ADDR;
bd_t *bd;
memset(gd, 0, sizeof(gd_t));
bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
memset(bd, 0, sizeof(bd_t));
gd->bd = bd;
bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
bd->bi_memsize = CONFIG_SYS_L2_SIZE;
arch_cpu_init();
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
gd->flags |= GD_FLG_FULL_MALLOC_INIT;
/* relocate environment function pointers etc. */
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
(uchar *)CONFIG_ENV_ADDR);
gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
gd->env_valid = ENV_VALID;
i2c_init_all();
dram_init();
#ifdef CONFIG_SPL_NAND_BOOT
puts("TPL\n");
#else
puts("SPL\n");
#endif
nand_boot();
}
void board_init_f(ulong dummy)
{
void (*second_uboot)(void);
/* Clear the BSS */
memset(__bss_start, 0, __bss_end - __bss_start);
get_clocks();
#if defined(CONFIG_DEEP_SLEEP)
if (is_warm_boot())
fsl_dp_disable_console();
#endif
preloader_console_init();
dram_init();
/* Allow OCRAM access permission as R/W */
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();
enable_layerscape_ns_access();
#endif
/*
* if it is woken up from deep sleep, then jump to second
* stage uboot and continue executing without recopying
* it from SD since it has already been reserved in memeory
* in last boot.
*/
if (is_warm_boot()) {
second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
second_uboot();
}
board_init_r(NULL, 0);
}
void board_init_f(ulong dummy)
{
/* Clear the BSS */
memset(__bss_start, 0, __bss_end - __bss_start);
get_clocks();
#if defined(CONFIG_DEEP_SLEEP)
if (is_warm_boot())
fsl_dp_disable_console();
#endif
preloader_console_init();
dram_init();
/* Allow OCRAM access permission as R/W */
#ifdef CONFIG_LS102XA_NS_ACCESS
enable_devices_ns_access(&ns_dev[4], 1);
enable_devices_ns_access(&ns_dev[7], 1);
#endif
board_init_r(NULL, 0);
}
void board_init_f(ulong board_type)
{
gd_t gd_data;
gd_t *new_gd;
bd_t *bd;
unsigned long *new_sp;
unsigned long monitor_len;
unsigned long monitor_addr;
unsigned long addr;
/* Initialize the global data pointer */
memset(&gd_data, 0, sizeof(gd_data));
gd = &gd_data;
/* Perform initialization sequence */
board_early_init_f();
arch_cpu_init();
board_postclk_init();
env_init();
init_baudrate();
serial_init();
console_init_f();
display_banner();
dram_init();
/* If we have no SDRAM, we can't go on */
if (gd->ram_size <= 0)
panic("No working SDRAM available\n");
/*
* Now that we have DRAM mapped and working, we can
* relocate the code and continue running from DRAM.
*
* Reserve memory at end of RAM for (top down in that order):
* - u-boot image
* - heap for malloc()
* - board info struct
* - global data struct
* - stack
*/
addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size;
monitor_len = (char *)(&__bss_end) - _text;
/*
* Reserve memory for u-boot code, data and bss.
* Round down to next 4 kB limit.
*/
addr -= monitor_len;
addr &= ~(4096UL - 1);
monitor_addr = addr;
/* Reserve memory for malloc() */
addr -= CONFIG_SYS_MALLOC_LEN;
#ifdef CONFIG_LCD
#ifdef CONFIG_FB_ADDR
printf("LCD: Frame buffer allocated at preset 0x%08x\n",
CONFIG_FB_ADDR);
gd->fb_base = CONFIG_FB_ADDR;
#else
addr = lcd_setmem(addr);
printf("LCD: Frame buffer allocated at 0x%08lx\n", addr);
gd->fb_base = addr;
#endif /* CONFIG_FB_ADDR */
#endif /* CONFIG_LCD */
/* Allocate a Board Info struct on a word boundary */
addr -= sizeof(bd_t);
addr &= ~3UL;
gd->bd = bd = (bd_t *)addr;
/* Allocate a new global data copy on a 8-byte boundary. */
addr -= sizeof(gd_t);
addr &= ~7UL;
new_gd = (gd_t *)addr;
/* And finally, a new, bigger stack. */
new_sp = (unsigned long *)addr;
gd->start_addr_sp = addr;
*(--new_sp) = 0;
*(--new_sp) = 0;
dram_init_banksize();
memcpy(new_gd, gd, sizeof(gd_t));
relocate_code((unsigned long)new_sp, new_gd, monitor_addr);
}
/*
* If this function is not defined here,
* board.c alters dram bank zero configuration defined above.
*/
void dram_init_banksize(void)
{
dram_init();
}
