/**
* Process driconf (drirc) options, setting appropriate context flags.
*
* intelInitExtensions still pokes at optionCache directly, in order to
* avoid advertising various extensions. No flags are set, so it makes
* sense to continue doing that there.
*/
static void
brw_process_driconf_options(struct brw_context *brw)
{
struct gl_context *ctx = &brw->ctx;
driOptionCache *options = &brw->optionCache;
driParseConfigFiles(options, &brw->intelScreen->optionCache,
brw->driContext->driScreenPriv->myNum, "i965");
int bo_reuse_mode = driQueryOptioni(options, "bo_reuse");
switch (bo_reuse_mode) {
case DRI_CONF_BO_REUSE_DISABLED:
break;
case DRI_CONF_BO_REUSE_ALL:
intel_bufmgr_gem_enable_reuse(brw->bufmgr);
break;
}
if (!driQueryOptionb(options, "hiz")) {
brw->has_hiz = false;
/* On gen6, you can only do separate stencil with HIZ. */
if (brw->gen == 6)
brw->has_separate_stencil = false;
}
if (driQueryOptionb(options, "always_flush_batch")) {
fprintf(stderr, "flushing batchbuffer before/after each draw call\n");
brw->always_flush_batch = true;
}
if (driQueryOptionb(options, "always_flush_cache")) {
fprintf(stderr, "flushing GPU caches before/after each draw call\n");
brw->always_flush_cache = true;
}
if (driQueryOptionb(options, "disable_throttling")) {
fprintf(stderr, "disabling flush throttling\n");
brw->disable_throttling = true;
}
brw->disable_derivative_optimization =
driQueryOptionb(&brw->optionCache, "disable_derivative_optimization");
brw->precompile = driQueryOptionb(&brw->optionCache, "shader_precompile");
ctx->Const.ForceGLSLExtensionsWarn =
driQueryOptionb(options, "force_glsl_extensions_warn");
ctx->Const.DisableGLSLLineContinuations =
driQueryOptionb(options, "disable_glsl_line_continuations");
}
/**
* DRI2
*/
static __DRIscreen *
dri2CreateNewScreen(int scrn, int fd,
const __DRIextension **extensions,
const __DRIconfig ***driver_configs, void *data)
{
static const __DRIextension *emptyExtensionList[] = { NULL };
__DRIscreen *psp;
drmVersionPtr version;
if (driDriverAPI.InitScreen2 == NULL)
return NULL;
psp = calloc(1, sizeof(*psp));
if (!psp)
return NULL;
setupLoaderExtensions(psp, extensions);
version = drmGetVersion(fd);
if (version) {
psp->drm_version.major = version->version_major;
psp->drm_version.minor = version->version_minor;
psp->drm_version.patch = version->version_patchlevel;
drmFreeVersion(version);
}
psp->extensions = emptyExtensionList;
psp->fd = fd;
psp->myNum = scrn;
psp->dri2.enabled = GL_TRUE;
psp->DriverAPI = driDriverAPI;
psp->api_mask = (1 << __DRI_API_OPENGL);
*driver_configs = driDriverAPI.InitScreen2(psp);
if (*driver_configs == NULL) {
free(psp);
return NULL;
}
psp->DriverAPI = driDriverAPI;
psp->loaderPrivate = data;
driParseOptionInfo(&psp->optionInfo, __dri2ConfigOptions,
__dri2NConfigOptions);
driParseConfigFiles(&psp->optionCache, &psp->optionInfo, psp->myNum,
"dri2");
return psp;
}
static char *loader_get_dri_config_device_id(void)
{
driOptionCache defaultInitOptions;
driOptionCache userInitOptions;
char *prime = NULL;
driParseOptionInfo(&defaultInitOptions, __driConfigOptionsLoader);
driParseConfigFiles(&userInitOptions, &defaultInitOptions, 0, "loader");
if (driCheckOption(&userInitOptions, "device_id", DRI_STRING))
prime = strdup(driQueryOptionstr(&userInitOptions, "device_id"));
driDestroyOptionCache(&userInitOptions);
driDestroyOptionInfo(&defaultInitOptions);
return prime;
}
GLboolean
nouveau_context_create(const __GLcontextModes *glVis,
__DRIcontextPrivate *driContextPriv,
void *sharedContextPrivate)
{
__DRIscreenPrivate *driScrnPriv = driContextPriv->driScreenPriv;
struct nouveau_screen *nv_screen = driScrnPriv->private;
struct nouveau_context *nv;
struct pipe_context *pipe;
struct st_context *st_share = NULL;
if (sharedContextPrivate)
st_share = ((struct nouveau_context *)sharedContextPrivate)->st;
nv = CALLOC_STRUCT(nouveau_context);
if (!nv)
return GL_FALSE;
{
struct nouveau_device_priv *nvdev =
nouveau_device(nv_screen->device);
nvdev->ctx = driContextPriv->hHWContext;
nvdev->lock = (drmLock *)&driScrnPriv->pSAREA->lock;
}
pipe = drm_api_hooks.create_context(nv_screen->pscreen);
if (!pipe) {
FREE(nv);
return GL_FALSE;
}
pipe->priv = nv;
driContextPriv->driverPrivate = nv;
nv->dri_screen = driScrnPriv;
driParseConfigFiles(&nv->dri_option_cache, &nv_screen->option_cache,
nv->dri_screen->myNum, "nouveau");
nv->st = st_create_context(pipe, glVis, st_share);
return GL_TRUE;
}
bool
intelInitContext(struct intel_context *intel,
int api,
unsigned major_version,
unsigned minor_version,
uint32_t flags,
const struct gl_config * mesaVis,
__DRIcontext * driContextPriv,
void *sharedContextPrivate,
struct dd_function_table *functions,
unsigned *dri_ctx_error)
{
struct gl_context *ctx = &intel->ctx;
struct gl_context *shareCtx = (struct gl_context *) sharedContextPrivate;
__DRIscreen *sPriv = driContextPriv->driScreenPriv;
struct intel_screen *intelScreen = sPriv->driverPrivate;
int bo_reuse_mode;
/* Can't rely on invalidate events, fall back to glViewport hack */
if (!driContextPriv->driScreenPriv->dri2.useInvalidate)
functions->Viewport = intel_noninvalidate_viewport;
else
functions->Viewport = intel_viewport;
intel->intelScreen = intelScreen;
if (!_mesa_initialize_context(&intel->ctx, api, mesaVis, shareCtx,
functions)) {
*dri_ctx_error = __DRI_CTX_ERROR_NO_MEMORY;
printf("%s: failed to init mesa context\n", __func__);
return false;
}
driContextSetFlags(&intel->ctx, flags);
driContextPriv->driverPrivate = intel;
intel->driContext = driContextPriv;
intel->gen = intelScreen->gen;
const int devID = intelScreen->deviceID;
intel->is_945 = IS_945(devID);
intel->has_swizzling = intel->intelScreen->hw_has_swizzling;
memset(&ctx->TextureFormatSupported,
0, sizeof(ctx->TextureFormatSupported));
driParseConfigFiles(&intel->optionCache, &intelScreen->optionCache,
sPriv->myNum, "i915");
intel->maxBatchSize = 4096;
/* Estimate the size of the mappable aperture into the GTT. There's an
* ioctl to get the whole GTT size, but not one to get the mappable subset.
* It turns out it's basically always 256MB, though some ancient hardware
* was smaller.
*/
uint32_t gtt_size = 256 * 1024 * 1024;
if (intel->gen == 2)
gtt_size = 128 * 1024 * 1024;
/* We don't want to map two objects such that a memcpy between them would
* just fault one mapping in and then the other over and over forever. So
* we would need to divide the GTT size by 2. Additionally, some GTT is
* taken up by things like the framebuffer and the ringbuffer and such, so
* be more conservative.
*/
intel->max_gtt_map_object_size = gtt_size / 4;
intel->bufmgr = intelScreen->bufmgr;
bo_reuse_mode = driQueryOptioni(&intel->optionCache, "bo_reuse");
switch (bo_reuse_mode) {
case DRI_CONF_BO_REUSE_DISABLED:
break;
case DRI_CONF_BO_REUSE_ALL:
intel_bufmgr_gem_enable_reuse(intel->bufmgr);
break;
}
ctx->Const.MinLineWidth = 1.0;
ctx->Const.MinLineWidthAA = 1.0;
ctx->Const.MaxLineWidth = 7.0;
ctx->Const.MaxLineWidthAA = 7.0;
ctx->Const.LineWidthGranularity = 0.5;
ctx->Const.MinPointSize = 1.0;
ctx->Const.MinPointSizeAA = 1.0;
ctx->Const.MaxPointSize = 255.0;
ctx->Const.MaxPointSizeAA = 3.0;
ctx->Const.PointSizeGranularity = 1.0;
ctx->Const.StripTextureBorder = GL_TRUE;
/* reinitialize the context point state.
* It depend on constants in __struct gl_contextRec::Const
*/
_mesa_init_point(ctx);
ctx->Const.MaxRenderbufferSize = 2048;
_swrast_CreateContext(ctx);
_vbo_CreateContext(ctx);
if (ctx->swrast_context) {
_tnl_CreateContext(ctx);
_swsetup_CreateContext(ctx);
/* Configure swrast to match hardware characteristics: */
_swrast_allow_pixel_fog(ctx, false);
_swrast_allow_vertex_fog(ctx, true);
}
_mesa_meta_init(ctx);
intel->hw_stipple = 1;
intel->RenderIndex = ~0;
intelInitExtensions(ctx);
INTEL_DEBUG = parse_debug_string(getenv("INTEL_DEBUG"), debug_control);
if (INTEL_DEBUG & DEBUG_BUFMGR)
dri_bufmgr_set_debug(intel->bufmgr, true);
if (INTEL_DEBUG & DEBUG_PERF)
intel->perf_debug = true;
if (INTEL_DEBUG & DEBUG_AUB)
drm_intel_bufmgr_gem_set_aub_dump(intel->bufmgr, true);
intel_batchbuffer_init(intel);
intel_fbo_init(intel);
intel->use_early_z = driQueryOptionb(&intel->optionCache, "early_z");
intel->prim.primitive = ~0;
/* Force all software fallbacks */
if (driQueryOptionb(&intel->optionCache, "no_rast")) {
fprintf(stderr, "disabling 3D rasterization\n");
intel->no_rast = 1;
}
if (driQueryOptionb(&intel->optionCache, "always_flush_batch")) {
fprintf(stderr, "flushing batchbuffer before/after each draw call\n");
intel->always_flush_batch = 1;
}
if (driQueryOptionb(&intel->optionCache, "always_flush_cache")) {
fprintf(stderr, "flushing GPU caches before/after each draw call\n");
intel->always_flush_cache = 1;
}
if (driQueryOptionb(&intel->optionCache, "disable_throttling")) {
fprintf(stderr, "disabling flush throttling\n");
intel->disable_throttling = 1;
}
return true;
}
/* Create the device specific rendering context.
*/
GLboolean r200CreateContext( const __GLcontextModes *glVisual,
__DRIcontextPrivate *driContextPriv,
void *sharedContextPrivate)
{
__DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
radeonScreenPtr screen = (radeonScreenPtr)(sPriv->private);
struct dd_function_table functions;
r200ContextPtr rmesa;
GLcontext *ctx;
int i;
int tcl_mode;
assert(glVisual);
assert(driContextPriv);
assert(screen);
/* Allocate the R200 context */
rmesa = (r200ContextPtr) CALLOC( sizeof(*rmesa) );
if ( !rmesa )
return GL_FALSE;
r200_init_vtbl(&rmesa->radeon);
/* init exp fog table data */
r200InitStaticFogData();
/* Parse configuration files.
* Do this here so that initialMaxAnisotropy is set before we create
* the default textures.
*/
driParseConfigFiles (&rmesa->radeon.optionCache, &screen->optionCache,
screen->driScreen->myNum, "r200");
rmesa->radeon.initialMaxAnisotropy = driQueryOptionf(&rmesa->radeon.optionCache,
"def_max_anisotropy");
if ( sPriv->drm_version.major == 1
&& driQueryOptionb( &rmesa->radeon.optionCache, "hyperz" ) ) {
if ( sPriv->drm_version.minor < 13 )
fprintf( stderr, "DRM version 1.%d too old to support HyperZ, "
"disabling.\n", sPriv->drm_version.minor );
else
rmesa->using_hyperz = GL_TRUE;
}
if ( sPriv->drm_version.minor >= 15 )
rmesa->texmicrotile = GL_TRUE;
/* Init default driver functions then plug in our R200-specific functions
* (the texture functions are especially important)
*/
_mesa_init_driver_functions(&functions);
r200InitDriverFuncs(&functions);
r200InitIoctlFuncs(&functions);
r200InitStateFuncs(&functions);
r200InitTextureFuncs(&functions);
r200InitShaderFuncs(&functions);
radeonInitQueryObjFunctions(&functions);
if (!radeonInitContext(&rmesa->radeon, &functions,
glVisual, driContextPriv,
sharedContextPrivate)) {
FREE(rmesa);
return GL_FALSE;
}
rmesa->radeon.swtcl.RenderIndex = ~0;
rmesa->radeon.hw.all_dirty = 1;
/* Set the maximum texture size small enough that we can guarentee that
* all texture units can bind a maximal texture and have all of them in
* texturable memory at once. Depending on the allow_large_textures driconf
* setting allow larger textures.
*/
ctx = rmesa->radeon.glCtx;
ctx->Const.MaxTextureUnits = driQueryOptioni (&rmesa->radeon.optionCache,
"texture_units");
ctx->Const.MaxTextureImageUnits = ctx->Const.MaxTextureUnits;
ctx->Const.MaxTextureCoordUnits = ctx->Const.MaxTextureUnits;
i = driQueryOptioni( &rmesa->radeon.optionCache, "allow_large_textures");
/* FIXME: When no memory manager is available we should set this
* to some reasonable value based on texture memory pool size */
ctx->Const.MaxTextureLevels = 12;
ctx->Const.Max3DTextureLevels = 9;
ctx->Const.MaxCubeTextureLevels = 12;
ctx->Const.MaxTextureRectSize = 2048;
ctx->Const.MaxTextureMaxAnisotropy = 16.0;
/* No wide AA points.
*/
ctx->Const.MinPointSize = 1.0;
ctx->Const.MinPointSizeAA = 1.0;
ctx->Const.MaxPointSizeAA = 1.0;
ctx->Const.PointSizeGranularity = 0.0625;
if (rmesa->radeon.radeonScreen->drmSupportsPointSprites)
ctx->Const.MaxPointSize = 2047.0;
else
ctx->Const.MaxPointSize = 1.0;
/* mesa initialization problem - _mesa_init_point was already called */
ctx->Point.MaxSize = ctx->Const.MaxPointSize;
ctx->Const.MinLineWidth = 1.0;
ctx->Const.MinLineWidthAA = 1.0;
ctx->Const.MaxLineWidth = 10.0;
ctx->Const.MaxLineWidthAA = 10.0;
ctx->Const.LineWidthGranularity = 0.0625;
ctx->Const.VertexProgram.MaxNativeInstructions = R200_VSF_MAX_INST;
ctx->Const.VertexProgram.MaxNativeAttribs = 12;
ctx->Const.VertexProgram.MaxNativeTemps = R200_VSF_MAX_TEMPS;
ctx->Const.VertexProgram.MaxNativeParameters = R200_VSF_MAX_PARAM;
ctx->Const.VertexProgram.MaxNativeAddressRegs = 1;
ctx->Const.MaxDrawBuffers = 1;
_mesa_set_mvp_with_dp4( ctx, GL_TRUE );
/* Initialize the software rasterizer and helper modules.
*/
_swrast_CreateContext( ctx );
_vbo_CreateContext( ctx );
_tnl_CreateContext( ctx );
_swsetup_CreateContext( ctx );
_ae_create_context( ctx );
/* Install the customized pipeline:
*/
_tnl_destroy_pipeline( ctx );
_tnl_install_pipeline( ctx, r200_pipeline );
/* Try and keep materials and vertices separate:
*/
/* _tnl_isolate_materials( ctx, GL_TRUE ); */
/* Configure swrast and TNL to match hardware characteristics:
*/
_swrast_allow_pixel_fog( ctx, GL_FALSE );
_swrast_allow_vertex_fog( ctx, GL_TRUE );
_tnl_allow_pixel_fog( ctx, GL_FALSE );
_tnl_allow_vertex_fog( ctx, GL_TRUE );
for ( i = 0 ; i < R200_MAX_TEXTURE_UNITS ; i++ ) {
_math_matrix_ctr( &rmesa->TexGenMatrix[i] );
_math_matrix_set_identity( &rmesa->TexGenMatrix[i] );
}
_math_matrix_ctr( &rmesa->tmpmat );
_math_matrix_set_identity( &rmesa->tmpmat );
driInitExtensions( ctx, card_extensions, GL_TRUE );
if (rmesa->radeon.radeonScreen->kernel_mm)
driInitExtensions(ctx, mm_extensions, GL_FALSE);
if (!(rmesa->radeon.radeonScreen->chip_flags & R200_CHIPSET_YCBCR_BROKEN)) {
/* yuv textures don't work with some chips - R200 / rv280 okay so far
others get the bit ordering right but don't actually do YUV-RGB conversion */
_mesa_enable_extension( ctx, "GL_MESA_ycbcr_texture" );
}
if (rmesa->radeon.glCtx->Mesa_DXTn) {
_mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" );
_mesa_enable_extension( ctx, "GL_S3_s3tc" );
}
else if (driQueryOptionb (&rmesa->radeon.optionCache, "force_s3tc_enable")) {
_mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" );
}
if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR200)
_mesa_enable_extension( ctx, "GL_ARB_texture_cube_map" );
if (rmesa->radeon.radeonScreen->drmSupportsBlendColor) {
driInitExtensions( ctx, blend_extensions, GL_FALSE );
}
if(rmesa->radeon.radeonScreen->drmSupportsVertexProgram)
driInitSingleExtension( ctx, ARB_vp_extension );
if(driQueryOptionb(&rmesa->radeon.optionCache, "nv_vertex_program"))
driInitSingleExtension( ctx, NV_vp_extension );
if ((ctx->Const.MaxTextureUnits == 6) && rmesa->radeon.radeonScreen->drmSupportsFragShader)
driInitSingleExtension( ctx, ATI_fs_extension );
if (rmesa->radeon.radeonScreen->drmSupportsPointSprites)
driInitExtensions( ctx, point_extensions, GL_FALSE );
if (!rmesa->radeon.radeonScreen->kernel_mm)
_mesa_disable_extension(ctx, "GL_ARB_occlusion_query");
#if 0
r200InitDriverFuncs( ctx );
r200InitIoctlFuncs( ctx );
r200InitStateFuncs( ctx );
r200InitTextureFuncs( ctx );
#endif
/* plug in a few more device driver functions */
/* XXX these should really go right after _mesa_init_driver_functions() */
radeon_fbo_init(&rmesa->radeon);
radeonInitSpanFuncs( ctx );
r200InitPixelFuncs( ctx );
r200InitTnlFuncs( ctx );
r200InitState( rmesa );
r200InitSwtcl( ctx );
rmesa->prefer_gart_client_texturing =
(getenv("R200_GART_CLIENT_TEXTURES") != 0);
tcl_mode = driQueryOptioni(&rmesa->radeon.optionCache, "tcl_mode");
if (driQueryOptionb(&rmesa->radeon.optionCache, "no_rast")) {
fprintf(stderr, "disabling 3D acceleration\n");
FALLBACK(rmesa, R200_FALLBACK_DISABLE, 1);
}
else if (tcl_mode == DRI_CONF_TCL_SW || getenv("R200_NO_TCL") ||
!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
rmesa->radeon.radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL;
fprintf(stderr, "Disabling HW TCL support\n");
}
TCL_FALLBACK(rmesa->radeon.glCtx, R200_TCL_FALLBACK_TCL_DISABLE, 1);
}
return GL_TRUE;
}
GLboolean
intelInitContext(struct intel_context *intel,
const __GLcontextModes * mesaVis,
__DRIcontext * driContextPriv,
void *sharedContextPrivate,
struct dd_function_table *functions)
{
GLcontext *ctx = &intel->ctx;
GLcontext *shareCtx = (GLcontext *) sharedContextPrivate;
__DRIscreen *sPriv = driContextPriv->driScreenPriv;
struct intel_screen *intelScreen = sPriv->private;
int bo_reuse_mode;
/* we can't do anything without a connection to the device */
if (intelScreen->bufmgr == NULL)
return GL_FALSE;
if (!_mesa_initialize_context(&intel->ctx, mesaVis, shareCtx,
functions, (void *) intel)) {
printf("%s: failed to init mesa context\n", __FUNCTION__);
return GL_FALSE;
}
driContextPriv->driverPrivate = intel;
intel->intelScreen = intelScreen;
intel->driScreen = sPriv;
intel->driContext = driContextPriv;
intel->driFd = sPriv->fd;
intel->has_xrgb_textures = GL_TRUE;
if (IS_GEN6(intel->intelScreen->deviceID)) {
intel->gen = 6;
intel->needs_ff_sync = GL_TRUE;
intel->has_luminance_srgb = GL_TRUE;
} else if (IS_GEN5(intel->intelScreen->deviceID)) {
intel->gen = 5;
intel->needs_ff_sync = GL_TRUE;
intel->has_luminance_srgb = GL_TRUE;
} else if (IS_965(intel->intelScreen->deviceID)) {
intel->gen = 4;
if (IS_G4X(intel->intelScreen->deviceID)) {
intel->has_luminance_srgb = GL_TRUE;
intel->is_g4x = GL_TRUE;
}
} else if (IS_9XX(intel->intelScreen->deviceID)) {
intel->gen = 3;
if (IS_945(intel->intelScreen->deviceID)) {
intel->is_945 = GL_TRUE;
}
} else {
intel->gen = 2;
if (intel->intelScreen->deviceID == PCI_CHIP_I830_M ||
intel->intelScreen->deviceID == PCI_CHIP_845_G) {
intel->has_xrgb_textures = GL_FALSE;
}
}
driParseConfigFiles(&intel->optionCache, &intelScreen->optionCache,
intel->driScreen->myNum,
(intel->gen >= 4) ? "i965" : "i915");
if (intelScreen->deviceID == PCI_CHIP_I865_G)
intel->maxBatchSize = 4096;
else
intel->maxBatchSize = BATCH_SZ;
intel->bufmgr = intelScreen->bufmgr;
bo_reuse_mode = driQueryOptioni(&intel->optionCache, "bo_reuse");
switch (bo_reuse_mode) {
case DRI_CONF_BO_REUSE_DISABLED:
break;
case DRI_CONF_BO_REUSE_ALL:
intel_bufmgr_gem_enable_reuse(intel->bufmgr);
break;
}
/* This doesn't yet catch all non-conformant rendering, but it's a
* start.
*/
if (getenv("INTEL_STRICT_CONFORMANCE")) {
unsigned int value = atoi(getenv("INTEL_STRICT_CONFORMANCE"));
if (value > 0) {
intel->conformance_mode = value;
}
else {
intel->conformance_mode = 1;
}
}
if (intel->conformance_mode > 0) {
ctx->Const.MinLineWidth = 1.0;
ctx->Const.MinLineWidthAA = 1.0;
ctx->Const.MaxLineWidth = 1.0;
ctx->Const.MaxLineWidthAA = 1.0;
ctx->Const.LineWidthGranularity = 1.0;
}
else {
ctx->Const.MinLineWidth = 1.0;
ctx->Const.MinLineWidthAA = 1.0;
ctx->Const.MaxLineWidth = 5.0;
ctx->Const.MaxLineWidthAA = 5.0;
ctx->Const.LineWidthGranularity = 0.5;
}
ctx->Const.MinPointSize = 1.0;
ctx->Const.MinPointSizeAA = 1.0;
ctx->Const.MaxPointSize = 255.0;
ctx->Const.MaxPointSizeAA = 3.0;
ctx->Const.PointSizeGranularity = 1.0;
/* reinitialize the context point state.
* It depend on constants in __GLcontextRec::Const
*/
_mesa_init_point(ctx);
meta_init_metaops(ctx, &intel->meta);
ctx->Const.MaxColorAttachments = 4; /* XXX FBO: review this */
if (intel->gen >= 4) {
if (MAX_WIDTH > 8192)
ctx->Const.MaxRenderbufferSize = 8192;
} else {
if (MAX_WIDTH > 2048)
ctx->Const.MaxRenderbufferSize = 2048;
}
/* Initialize the software rasterizer and helper modules. */
_swrast_CreateContext(ctx);
_vbo_CreateContext(ctx);
_tnl_CreateContext(ctx);
_swsetup_CreateContext(ctx);
/* Configure swrast to match hardware characteristics: */
_swrast_allow_pixel_fog(ctx, GL_FALSE);
_swrast_allow_vertex_fog(ctx, GL_TRUE);
_mesa_meta_init(ctx);
intel->hw_stencil = mesaVis->stencilBits && mesaVis->depthBits == 24;
intel->hw_stipple = 1;
/* XXX FBO: this doesn't seem to be used anywhere */
switch (mesaVis->depthBits) {
case 0: /* what to do in this case? */
case 16:
intel->polygon_offset_scale = 1.0;
break;
case 24:
intel->polygon_offset_scale = 2.0; /* req'd to pass glean */
break;
default:
assert(0);
break;
}
if (intel->gen >= 4)
intel->polygon_offset_scale /= 0xffff;
intel->RenderIndex = ~0;
intelInitExtensions(ctx);
INTEL_DEBUG = driParseDebugString(getenv("INTEL_DEBUG"), debug_control);
if (INTEL_DEBUG & DEBUG_BUFMGR)
dri_bufmgr_set_debug(intel->bufmgr, GL_TRUE);
intel->batch = intel_batchbuffer_alloc(intel);
intel_fbo_init(intel);
if (intel->ctx.Mesa_DXTn) {
_mesa_enable_extension(ctx, "GL_EXT_texture_compression_s3tc");
_mesa_enable_extension(ctx, "GL_S3_s3tc");
}
else if (driQueryOptionb(&intel->optionCache, "force_s3tc_enable")) {
_mesa_enable_extension(ctx, "GL_EXT_texture_compression_s3tc");
}
intel->use_texture_tiling = driQueryOptionb(&intel->optionCache,
"texture_tiling");
intel->use_early_z = driQueryOptionb(&intel->optionCache, "early_z");
intel->prim.primitive = ~0;
/* Force all software fallbacks */
if (driQueryOptionb(&intel->optionCache, "no_rast")) {
fprintf(stderr, "disabling 3D rasterization\n");
intel->no_rast = 1;
}
if (driQueryOptionb(&intel->optionCache, "always_flush_batch")) {
fprintf(stderr, "flushing batchbuffer before/after each draw call\n");
intel->always_flush_batch = 1;
}
if (driQueryOptionb(&intel->optionCache, "always_flush_cache")) {
fprintf(stderr, "flushing GPU caches before/after each draw call\n");
intel->always_flush_cache = 1;
}
/* Disable all hardware rendering (skip emitting batches and fences/waits
* to the kernel)
*/
intel->no_hw = getenv("INTEL_NO_HW") != NULL;
return GL_TRUE;
}
/**
* This is the first entrypoint in the driver called by the DRI driver loader
* after dlopen()ing it.
*
* It's used to create global state for the driver across contexts on the same
* Display.
*/
static __DRIscreen *
driCreateNewScreen2(int scrn, int fd,
const __DRIextension **extensions,
const __DRIextension **driver_extensions,
const __DRIconfig ***driver_configs, void *data)
{
static const __DRIextension *emptyExtensionList[] = { NULL };
__DRIscreen *psp;
psp = calloc(1, sizeof(*psp));
if (!psp)
return NULL;
/* By default, use the global driDriverAPI symbol (non-megadrivers). */
psp->driver = globalDriverAPI;
/* If the driver exposes its vtable through its extensions list
* (megadrivers), use that instead.
*/
if (driver_extensions) {
for (int i = 0; driver_extensions[i]; i++) {
if (strcmp(driver_extensions[i]->name, __DRI_DRIVER_VTABLE) == 0) {
psp->driver =
((__DRIDriverVtableExtension *)driver_extensions[i])->vtable;
}
}
}
setupLoaderExtensions(psp, extensions);
psp->loaderPrivate = data;
psp->extensions = emptyExtensionList;
psp->fd = fd;
psp->myNum = scrn;
*driver_configs = psp->driver->InitScreen(psp);
if (*driver_configs == NULL) {
free(psp);
return NULL;
}
struct gl_constants consts = { 0 };
gl_api api;
unsigned version;
api = API_OPENGLES2;
if (_mesa_override_gl_version_contextless(&consts, &api, &version))
psp->max_gl_es2_version = version;
api = API_OPENGL_COMPAT;
if (_mesa_override_gl_version_contextless(&consts, &api, &version)) {
if (api == API_OPENGL_CORE) {
psp->max_gl_core_version = version;
} else {
psp->max_gl_compat_version = version;
}
}
psp->api_mask = 0;
if (psp->max_gl_compat_version > 0)
psp->api_mask |= (1 << __DRI_API_OPENGL);
if (psp->max_gl_core_version > 0)
psp->api_mask |= (1 << __DRI_API_OPENGL_CORE);
if (psp->max_gl_es1_version > 0)
psp->api_mask |= (1 << __DRI_API_GLES);
if (psp->max_gl_es2_version > 0)
psp->api_mask |= (1 << __DRI_API_GLES2);
if (psp->max_gl_es2_version >= 30)
psp->api_mask |= (1 << __DRI_API_GLES3);
driParseOptionInfo(&psp->optionInfo, __dri2ConfigOptions);
driParseConfigFiles(&psp->optionCache, &psp->optionInfo, psp->myNum, "dri2");
return psp;
}
GLboolean
dri_create_context(gl_api api, const struct gl_config * visual,
__DRIcontext * cPriv,
unsigned major_version,
unsigned minor_version,
uint32_t flags,
unsigned *error,
void *sharedContextPrivate)
{
__DRIscreen *sPriv = cPriv->driScreenPriv;
struct dri_screen *screen = dri_screen(sPriv);
struct st_api *stapi = screen->st_api;
struct dri_context *ctx = NULL;
struct st_context_iface *st_share = NULL;
struct st_context_attribs attribs;
enum st_context_error ctx_err = 0;
memset(&attribs, 0, sizeof(attribs));
switch (api) {
case API_OPENGLES:
attribs.profile = ST_PROFILE_OPENGL_ES1;
break;
case API_OPENGLES2:
attribs.profile = ST_PROFILE_OPENGL_ES2;
break;
case API_OPENGL:
attribs.profile = ST_PROFILE_DEFAULT;
attribs.major = major_version;
attribs.minor = minor_version;
if ((flags & __DRI_CTX_FLAG_DEBUG) != 0)
attribs.flags |= ST_CONTEXT_FLAG_DEBUG;
if ((flags & __DRI_CTX_FLAG_FORWARD_COMPATIBLE) != 0)
attribs.flags |= ST_CONTEXT_FLAG_FORWARD_COMPATIBLE;
break;
default:
*error = __DRI_CTX_ERROR_BAD_API;
goto fail;
}
if (sharedContextPrivate) {
st_share = ((struct dri_context *)sharedContextPrivate)->st;
}
ctx = CALLOC_STRUCT(dri_context);
if (ctx == NULL) {
*error = __DRI_CTX_ERROR_NO_MEMORY;
goto fail;
}
cPriv->driverPrivate = ctx;
ctx->cPriv = cPriv;
ctx->sPriv = sPriv;
driParseConfigFiles(&ctx->optionCache,
&screen->optionCache, sPriv->myNum, driver_descriptor.name);
dri_fill_st_options(&attribs.options, &ctx->optionCache);
dri_fill_st_visual(&attribs.visual, screen, visual);
ctx->st = stapi->create_context(stapi, &screen->base, &attribs, &ctx_err,
st_share);
if (ctx->st == NULL) {
switch (ctx_err) {
case ST_CONTEXT_SUCCESS:
*error = __DRI_CTX_ERROR_SUCCESS;
break;
case ST_CONTEXT_ERROR_NO_MEMORY:
*error = __DRI_CTX_ERROR_NO_MEMORY;
break;
case ST_CONTEXT_ERROR_BAD_API:
*error = __DRI_CTX_ERROR_BAD_API;
break;
case ST_CONTEXT_ERROR_BAD_VERSION:
*error = __DRI_CTX_ERROR_BAD_VERSION;
break;
case ST_CONTEXT_ERROR_BAD_FLAG:
*error = __DRI_CTX_ERROR_BAD_FLAG;
break;
case ST_CONTEXT_ERROR_UNKNOWN_ATTRIBUTE:
*error = __DRI_CTX_ERROR_UNKNOWN_ATTRIBUTE;
break;
case ST_CONTEXT_ERROR_UNKNOWN_FLAG:
*error = __DRI_CTX_ERROR_UNKNOWN_FLAG;
break;
}
goto fail;
}
ctx->st->st_manager_private = (void *) ctx;
ctx->stapi = stapi;
// Context successfully created. See if post-processing is requested.
dri_pp_query(ctx);
ctx->pp = pp_init(screen->base.screen, ctx->pp_enabled);
*error = __DRI_CTX_ERROR_SUCCESS;
return GL_TRUE;
fail:
if (ctx && ctx->st)
ctx->st->destroy(ctx->st);
FREE(ctx);
return GL_FALSE;
}
/* Create the device specific rendering context.
*/
GLboolean r200CreateContext( const __GLcontextModes *glVisual,
__DRIcontextPrivate *driContextPriv,
void *sharedContextPrivate)
{
__DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
radeonScreenPtr screen = (radeonScreenPtr)(sPriv->private);
struct dd_function_table functions;
r200ContextPtr rmesa;
GLcontext *ctx, *shareCtx;
int i;
int tcl_mode, fthrottle_mode;
assert(glVisual);
assert(driContextPriv);
assert(screen);
/* Allocate the R200 context */
rmesa = (r200ContextPtr) CALLOC( sizeof(*rmesa) );
if ( !rmesa )
return GL_FALSE;
/* init exp fog table data */
r200InitStaticFogData();
/* Parse configuration files.
* Do this here so that initialMaxAnisotropy is set before we create
* the default textures.
*/
driParseConfigFiles (&rmesa->optionCache, &screen->optionCache,
screen->driScreen->myNum, "r200");
rmesa->initialMaxAnisotropy = driQueryOptionf(&rmesa->optionCache,
"def_max_anisotropy");
if ( driQueryOptionb( &rmesa->optionCache, "hyperz" ) ) {
if ( sPriv->drmMinor < 13 )
fprintf( stderr, "DRM version 1.%d too old to support HyperZ, "
"disabling.\n",sPriv->drmMinor );
else
rmesa->using_hyperz = GL_TRUE;
}
if ( sPriv->drmMinor >= 15 )
rmesa->texmicrotile = GL_TRUE;
/* Init default driver functions then plug in our R200-specific functions
* (the texture functions are especially important)
*/
_mesa_init_driver_functions(&functions);
r200InitDriverFuncs(&functions);
r200InitIoctlFuncs(&functions);
r200InitStateFuncs(&functions);
r200InitTextureFuncs(&functions);
r200InitShaderFuncs(&functions);
/* Allocate and initialize the Mesa context */
if (sharedContextPrivate)
shareCtx = ((r200ContextPtr) sharedContextPrivate)->glCtx;
else
shareCtx = NULL;
rmesa->glCtx = _mesa_create_context(glVisual, shareCtx,
&functions, (void *) rmesa);
if (!rmesa->glCtx) {
FREE(rmesa);
return GL_FALSE;
}
driContextPriv->driverPrivate = rmesa;
/* Init r200 context data */
rmesa->dri.context = driContextPriv;
rmesa->dri.screen = sPriv;
rmesa->dri.drawable = NULL; /* Set by XMesaMakeCurrent */
rmesa->dri.hwContext = driContextPriv->hHWContext;
rmesa->dri.hwLock = &sPriv->pSAREA->lock;
rmesa->dri.fd = sPriv->fd;
rmesa->dri.drmMinor = sPriv->drmMinor;
rmesa->r200Screen = screen;
rmesa->sarea = (drm_radeon_sarea_t *)((GLubyte *)sPriv->pSAREA +
screen->sarea_priv_offset);
rmesa->dma.buf0_address = rmesa->r200Screen->buffers->list[0].address;
(void) memset( rmesa->texture_heaps, 0, sizeof( rmesa->texture_heaps ) );
make_empty_list( & rmesa->swapped );
rmesa->nr_heaps = 1 /* screen->numTexHeaps */ ;
assert(rmesa->nr_heaps < RADEON_NR_TEX_HEAPS);
for ( i = 0 ; i < rmesa->nr_heaps ; i++ ) {
rmesa->texture_heaps[i] = driCreateTextureHeap( i, rmesa,
screen->texSize[i],
12,
RADEON_NR_TEX_REGIONS,
(drmTextureRegionPtr)rmesa->sarea->tex_list[i],
& rmesa->sarea->tex_age[i],
& rmesa->swapped,
sizeof( r200TexObj ),
(destroy_texture_object_t *) r200DestroyTexObj );
}
rmesa->texture_depth = driQueryOptioni (&rmesa->optionCache,
"texture_depth");
if (rmesa->texture_depth == DRI_CONF_TEXTURE_DEPTH_FB)
rmesa->texture_depth = ( screen->cpp == 4 ) ?
DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16;
rmesa->swtcl.RenderIndex = ~0;
rmesa->hw.all_dirty = 1;
/* Set the maximum texture size small enough that we can guarentee that
* all texture units can bind a maximal texture and have all of them in
* texturable memory at once. Depending on the allow_large_textures driconf
* setting allow larger textures.
*/
ctx = rmesa->glCtx;
ctx->Const.MaxTextureUnits = driQueryOptioni (&rmesa->optionCache,
"texture_units");
ctx->Const.MaxTextureImageUnits = ctx->Const.MaxTextureUnits;
ctx->Const.MaxTextureCoordUnits = ctx->Const.MaxTextureUnits;
i = driQueryOptioni( &rmesa->optionCache, "allow_large_textures");
driCalculateMaxTextureLevels( rmesa->texture_heaps,
rmesa->nr_heaps,
& ctx->Const,
4,
11, /* max 2D texture size is 2048x2048 */
#if ENABLE_HW_3D_TEXTURE
8, /* max 3D texture size is 256^3 */
#else
0, /* 3D textures unsupported */
#endif
11, /* max cube texture size is 2048x2048 */
11, /* max texture rectangle size is 2048x2048 */
12,
GL_FALSE,
i );
ctx->Const.MaxTextureMaxAnisotropy = 16.0;
/* No wide AA points.
*/
ctx->Const.MinPointSize = 1.0;
ctx->Const.MinPointSizeAA = 1.0;
ctx->Const.MaxPointSizeAA = 1.0;
ctx->Const.PointSizeGranularity = 0.0625;
if (rmesa->r200Screen->drmSupportsPointSprites)
ctx->Const.MaxPointSize = 2047.0;
else
ctx->Const.MaxPointSize = 1.0;
/* mesa initialization problem - _mesa_init_point was already called */
ctx->Point.MaxSize = ctx->Const.MaxPointSize;
ctx->Const.MinLineWidth = 1.0;
ctx->Const.MinLineWidthAA = 1.0;
ctx->Const.MaxLineWidth = 10.0;
ctx->Const.MaxLineWidthAA = 10.0;
ctx->Const.LineWidthGranularity = 0.0625;
ctx->Const.VertexProgram.MaxNativeInstructions = R200_VSF_MAX_INST;
ctx->Const.VertexProgram.MaxNativeAttribs = 12;
ctx->Const.VertexProgram.MaxNativeTemps = R200_VSF_MAX_TEMPS;
ctx->Const.VertexProgram.MaxNativeParameters = R200_VSF_MAX_PARAM;
ctx->Const.VertexProgram.MaxNativeAddressRegs = 1;
/* Initialize the software rasterizer and helper modules.
*/
_swrast_CreateContext( ctx );
_vbo_CreateContext( ctx );
_tnl_CreateContext( ctx );
_swsetup_CreateContext( ctx );
_ae_create_context( ctx );
/* Install the customized pipeline:
*/
_tnl_destroy_pipeline( ctx );
_tnl_install_pipeline( ctx, r200_pipeline );
/* Try and keep materials and vertices separate:
*/
/* _tnl_isolate_materials( ctx, GL_TRUE ); */
/* Configure swrast and TNL to match hardware characteristics:
*/
_swrast_allow_pixel_fog( ctx, GL_FALSE );
_swrast_allow_vertex_fog( ctx, GL_TRUE );
_tnl_allow_pixel_fog( ctx, GL_FALSE );
_tnl_allow_vertex_fog( ctx, GL_TRUE );
for ( i = 0 ; i < R200_MAX_TEXTURE_UNITS ; i++ ) {
_math_matrix_ctr( &rmesa->TexGenMatrix[i] );
_math_matrix_set_identity( &rmesa->TexGenMatrix[i] );
}
_math_matrix_ctr( &rmesa->tmpmat );
_math_matrix_set_identity( &rmesa->tmpmat );
driInitExtensions( ctx, card_extensions, GL_TRUE );
if (!(rmesa->r200Screen->chip_flags & R200_CHIPSET_YCBCR_BROKEN)) {
/* yuv textures don't work with some chips - R200 / rv280 okay so far
others get the bit ordering right but don't actually do YUV-RGB conversion */
_mesa_enable_extension( ctx, "GL_MESA_ycbcr_texture" );
}
if (rmesa->glCtx->Mesa_DXTn) {
_mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" );
_mesa_enable_extension( ctx, "GL_S3_s3tc" );
}
else if (driQueryOptionb (&rmesa->optionCache, "force_s3tc_enable")) {
_mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" );
}
if (rmesa->r200Screen->drmSupportsCubeMapsR200)
_mesa_enable_extension( ctx, "GL_ARB_texture_cube_map" );
if (rmesa->r200Screen->drmSupportsBlendColor) {
driInitExtensions( ctx, blend_extensions, GL_FALSE );
}
if(rmesa->r200Screen->drmSupportsVertexProgram)
driInitSingleExtension( ctx, ARB_vp_extension );
if(driQueryOptionb(&rmesa->optionCache, "nv_vertex_program"))
driInitSingleExtension( ctx, NV_vp_extension );
if ((ctx->Const.MaxTextureUnits == 6) && rmesa->r200Screen->drmSupportsFragShader)
driInitSingleExtension( ctx, ATI_fs_extension );
if (rmesa->r200Screen->drmSupportsPointSprites)
driInitExtensions( ctx, point_extensions, GL_FALSE );
#if 0
r200InitDriverFuncs( ctx );
r200InitIoctlFuncs( ctx );
r200InitStateFuncs( ctx );
r200InitTextureFuncs( ctx );
#endif
/* plug in a few more device driver functions */
/* XXX these should really go right after _mesa_init_driver_functions() */
r200InitPixelFuncs( ctx );
r200InitSpanFuncs( ctx );
r200InitTnlFuncs( ctx );
r200InitState( rmesa );
r200InitSwtcl( ctx );
fthrottle_mode = driQueryOptioni(&rmesa->optionCache, "fthrottle_mode");
rmesa->iw.irq_seq = -1;
rmesa->irqsEmitted = 0;
rmesa->do_irqs = (fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS &&
rmesa->r200Screen->irq);
rmesa->do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
if (!rmesa->do_irqs)
fprintf(stderr,
"IRQ's not enabled, falling back to %s: %d %d\n",
rmesa->do_usleeps ? "usleeps" : "busy waits",
fthrottle_mode,
rmesa->r200Screen->irq);
rmesa->vblank_flags = (rmesa->r200Screen->irq != 0)
? driGetDefaultVBlankFlags(&rmesa->optionCache) : VBLANK_FLAG_NO_IRQ;
rmesa->prefer_gart_client_texturing =
(getenv("R200_GART_CLIENT_TEXTURES") != 0);
(*dri_interface->getUST)( & rmesa->swap_ust );
#if DO_DEBUG
R200_DEBUG = driParseDebugString( getenv( "R200_DEBUG" ),
debug_control );
R200_DEBUG |= driParseDebugString( getenv( "RADEON_DEBUG" ),
debug_control );
#endif
tcl_mode = driQueryOptioni(&rmesa->optionCache, "tcl_mode");
if (driQueryOptionb(&rmesa->optionCache, "no_rast")) {
fprintf(stderr, "disabling 3D acceleration\n");
FALLBACK(rmesa, R200_FALLBACK_DISABLE, 1);
}
else if (tcl_mode == DRI_CONF_TCL_SW || getenv("R200_NO_TCL") ||
!(rmesa->r200Screen->chip_flags & RADEON_CHIPSET_TCL)) {
if (rmesa->r200Screen->chip_flags & RADEON_CHIPSET_TCL) {
rmesa->r200Screen->chip_flags &= ~RADEON_CHIPSET_TCL;
fprintf(stderr, "Disabling HW TCL support\n");
}
TCL_FALLBACK(rmesa->glCtx, R200_TCL_FALLBACK_TCL_DISABLE, 1);
}
return GL_TRUE;
}
/* Create the device specific context.
*/
GLboolean
radeonCreateContext( const __GLcontextModes *glVisual,
__DRIcontextPrivate *driContextPriv,
void *sharedContextPrivate)
{
__DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
radeonScreenPtr screen = (radeonScreenPtr)(sPriv->private);
struct dd_function_table functions;
radeonContextPtr rmesa;
GLcontext *ctx, *shareCtx;
int i;
int tcl_mode, fthrottle_mode;
assert(glVisual);
assert(driContextPriv);
assert(screen);
/* Allocate the Radeon context */
rmesa = (radeonContextPtr) CALLOC( sizeof(*rmesa) );
if ( !rmesa )
return GL_FALSE;
/* init exp fog table data */
radeonInitStaticFogData();
/* Parse configuration files.
* Do this here so that initialMaxAnisotropy is set before we create
* the default textures.
*/
driParseConfigFiles (&rmesa->optionCache, &screen->optionCache,
screen->driScreen->myNum, "radeon");
rmesa->initialMaxAnisotropy = driQueryOptionf(&rmesa->optionCache,
"def_max_anisotropy");
if ( driQueryOptionb( &rmesa->optionCache, "hyperz" ) ) {
if ( sPriv->drm_version.minor < 13 )
fprintf( stderr, "DRM version 1.%d too old to support HyperZ, "
"disabling.\n", sPriv->drm_version.minor );
else
rmesa->using_hyperz = GL_TRUE;
}
if ( sPriv->drm_version.minor >= 15 )
rmesa->texmicrotile = GL_TRUE;
/* Init default driver functions then plug in our Radeon-specific functions
* (the texture functions are especially important)
*/
_mesa_init_driver_functions( &functions );
radeonInitDriverFuncs( &functions );
radeonInitTextureFuncs( &functions );
/* Allocate the Mesa context */
if (sharedContextPrivate)
shareCtx = ((radeonContextPtr) sharedContextPrivate)->glCtx;
else
shareCtx = NULL;
rmesa->glCtx = _mesa_create_context(glVisual, shareCtx,
&functions, (void *) rmesa);
if (!rmesa->glCtx) {
FREE(rmesa);
return GL_FALSE;
}
driContextPriv->driverPrivate = rmesa;
/* Init radeon context data */
rmesa->dri.context = driContextPriv;
rmesa->dri.screen = sPriv;
rmesa->dri.drawable = NULL;
rmesa->dri.readable = NULL;
rmesa->dri.hwContext = driContextPriv->hHWContext;
rmesa->dri.hwLock = &sPriv->pSAREA->lock;
rmesa->dri.fd = sPriv->fd;
rmesa->dri.drmMinor = sPriv->drm_version.minor;
rmesa->radeonScreen = screen;
rmesa->sarea = (drm_radeon_sarea_t *)((GLubyte *)sPriv->pSAREA +
screen->sarea_priv_offset);
rmesa->dma.buf0_address = rmesa->radeonScreen->buffers->list[0].address;
(void) memset( rmesa->texture_heaps, 0, sizeof( rmesa->texture_heaps ) );
make_empty_list( & rmesa->swapped );
rmesa->nr_heaps = screen->numTexHeaps;
for ( i = 0 ; i < rmesa->nr_heaps ; i++ ) {
rmesa->texture_heaps[i] = driCreateTextureHeap( i, rmesa,
screen->texSize[i],
12,
RADEON_NR_TEX_REGIONS,
(drmTextureRegionPtr)rmesa->sarea->tex_list[i],
& rmesa->sarea->tex_age[i],
& rmesa->swapped,
sizeof( radeonTexObj ),
(destroy_texture_object_t *) radeonDestroyTexObj );
driSetTextureSwapCounterLocation( rmesa->texture_heaps[i],
& rmesa->c_textureSwaps );
}
rmesa->texture_depth = driQueryOptioni (&rmesa->optionCache,
"texture_depth");
if (rmesa->texture_depth == DRI_CONF_TEXTURE_DEPTH_FB)
rmesa->texture_depth = ( screen->cpp == 4 ) ?
DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16;
rmesa->swtcl.RenderIndex = ~0;
rmesa->hw.all_dirty = GL_TRUE;
/* Set the maximum texture size small enough that we can guarentee that
* all texture units can bind a maximal texture and have all of them in
* texturable memory at once. Depending on the allow_large_textures driconf
* setting allow larger textures.
*/
ctx = rmesa->glCtx;
ctx->Const.MaxTextureUnits = driQueryOptioni (&rmesa->optionCache,
"texture_units");
ctx->Const.MaxTextureImageUnits = ctx->Const.MaxTextureUnits;
ctx->Const.MaxTextureCoordUnits = ctx->Const.MaxTextureUnits;
i = driQueryOptioni( &rmesa->optionCache, "allow_large_textures");
driCalculateMaxTextureLevels( rmesa->texture_heaps,
rmesa->nr_heaps,
& ctx->Const,
4,
11, /* max 2D texture size is 2048x2048 */
8, /* 256^3 */
9, /* \todo: max cube texture size seems to be 512x512(x6) */
11, /* max rect texture size is 2048x2048. */
12,
GL_FALSE,
i );
ctx->Const.MaxTextureMaxAnisotropy = 16.0;
/* No wide points.
*/
ctx->Const.MinPointSize = 1.0;
ctx->Const.MinPointSizeAA = 1.0;
ctx->Const.MaxPointSize = 1.0;
ctx->Const.MaxPointSizeAA = 1.0;
ctx->Const.MinLineWidth = 1.0;
ctx->Const.MinLineWidthAA = 1.0;
ctx->Const.MaxLineWidth = 10.0;
ctx->Const.MaxLineWidthAA = 10.0;
ctx->Const.LineWidthGranularity = 0.0625;
/* Set maxlocksize (and hence vb size) small enough to avoid
* fallbacks in radeon_tcl.c. ie. guarentee that all vertices can
* fit in a single dma buffer for indexed rendering of quad strips,
* etc.
*/
ctx->Const.MaxArrayLockSize =
MIN2( ctx->Const.MaxArrayLockSize,
RADEON_BUFFER_SIZE / RADEON_MAX_TCL_VERTSIZE );
rmesa->boxes = 0;
ctx->Const.MaxDrawBuffers = 1;
_mesa_set_mvp_with_dp4( ctx, GL_TRUE );
/* Initialize the software rasterizer and helper modules.
*/
_swrast_CreateContext( ctx );
_vbo_CreateContext( ctx );
_tnl_CreateContext( ctx );
_swsetup_CreateContext( ctx );
_ae_create_context( ctx );
/* Install the customized pipeline:
*/
_tnl_destroy_pipeline( ctx );
_tnl_install_pipeline( ctx, radeon_pipeline );
/* Try and keep materials and vertices separate:
*/
/* _tnl_isolate_materials( ctx, GL_TRUE ); */
/* Configure swrast and T&L to match hardware characteristics:
*/
_swrast_allow_pixel_fog( ctx, GL_FALSE );
_swrast_allow_vertex_fog( ctx, GL_TRUE );
_tnl_allow_pixel_fog( ctx, GL_FALSE );
_tnl_allow_vertex_fog( ctx, GL_TRUE );
for ( i = 0 ; i < RADEON_MAX_TEXTURE_UNITS ; i++ ) {
_math_matrix_ctr( &rmesa->TexGenMatrix[i] );
_math_matrix_ctr( &rmesa->tmpmat[i] );
_math_matrix_set_identity( &rmesa->TexGenMatrix[i] );
_math_matrix_set_identity( &rmesa->tmpmat[i] );
}
driInitExtensions( ctx, card_extensions, GL_TRUE );
if (rmesa->radeonScreen->drmSupportsCubeMapsR100)
_mesa_enable_extension( ctx, "GL_ARB_texture_cube_map" );
if (rmesa->glCtx->Mesa_DXTn) {
_mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" );
_mesa_enable_extension( ctx, "GL_S3_s3tc" );
}
else if (driQueryOptionb (&rmesa->optionCache, "force_s3tc_enable")) {
_mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" );
}
if (rmesa->dri.drmMinor >= 9)
_mesa_enable_extension( ctx, "GL_NV_texture_rectangle");
/* XXX these should really go right after _mesa_init_driver_functions() */
radeonInitIoctlFuncs( ctx );
radeonInitStateFuncs( ctx );
radeonInitSpanFuncs( ctx );
radeonInitState( rmesa );
radeonInitSwtcl( ctx );
_mesa_vector4f_alloc( &rmesa->tcl.ObjClean, 0,
ctx->Const.MaxArrayLockSize, 32 );
fthrottle_mode = driQueryOptioni(&rmesa->optionCache, "fthrottle_mode");
rmesa->iw.irq_seq = -1;
rmesa->irqsEmitted = 0;
rmesa->do_irqs = (rmesa->radeonScreen->irq != 0 &&
fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS);
rmesa->do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
(*sPriv->systemTime->getUST)( & rmesa->swap_ust );
#if DO_DEBUG
RADEON_DEBUG = driParseDebugString( getenv( "RADEON_DEBUG" ),
debug_control );
#endif
tcl_mode = driQueryOptioni(&rmesa->optionCache, "tcl_mode");
if (driQueryOptionb(&rmesa->optionCache, "no_rast")) {
fprintf(stderr, "disabling 3D acceleration\n");
FALLBACK(rmesa, RADEON_FALLBACK_DISABLE, 1);
} else if (tcl_mode == DRI_CONF_TCL_SW ||
!(rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
if (rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
rmesa->radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL;
fprintf(stderr, "Disabling HW TCL support\n");
}
TCL_FALLBACK(rmesa->glCtx, RADEON_TCL_FALLBACK_TCL_DISABLE, 1);
}
if (rmesa->radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
/* _tnl_need_dlist_norm_lengths( ctx, GL_FALSE ); */
}
return GL_TRUE;
}
static HRESULT WINAPI
drm_create_adapter( int fd,
ID3DAdapter9 **ppAdapter )
{
struct d3dadapter9drm_context *ctx = CALLOC_STRUCT(d3dadapter9drm_context);
HRESULT hr;
bool different_device;
driOptionCache defaultInitOptions;
driOptionCache userInitOptions;
int throttling_value_user = -2;
int override_vendorid = -1;
if (!ctx) { return E_OUTOFMEMORY; }
ctx->base.destroy = drm_destroy;
/* Although the fd is provided from external source, mesa/nine
* takes ownership of it. */
fd = loader_get_user_preferred_fd(fd, &different_device);
ctx->fd = fd;
ctx->base.linear_framebuffer = different_device;
if (!pipe_loader_drm_probe_fd(&ctx->dev, fd)) {
ERR("Failed to probe drm fd %d.\n", fd);
FREE(ctx);
close(fd);
return D3DERR_DRIVERINTERNALERROR;
}
ctx->base.hal = pipe_loader_create_screen(ctx->dev);
if (!ctx->base.hal) {
ERR("Unable to load requested driver.\n");
drm_destroy(&ctx->base);
return D3DERR_DRIVERINTERNALERROR;
}
if (!ctx->base.hal->get_param(ctx->base.hal, PIPE_CAP_DMABUF)) {
ERR("The driver is not capable of dma-buf sharing."
"Abandon to load nine state tracker\n");
drm_destroy(&ctx->base);
return D3DERR_DRIVERINTERNALERROR;
}
/* Previously was set to PIPE_CAP_MAX_FRAMES_IN_FLIGHT,
* but the change of value of this cap to 1 seems to cause
* regressions. */
ctx->base.throttling_value = 2;
ctx->base.throttling = ctx->base.throttling_value > 0;
driParseOptionInfo(&defaultInitOptions, __driConfigOptionsNine);
driParseConfigFiles(&userInitOptions, &defaultInitOptions, 0, "nine", NULL);
if (driCheckOption(&userInitOptions, "throttle_value", DRI_INT)) {
throttling_value_user = driQueryOptioni(&userInitOptions, "throttle_value");
if (throttling_value_user == -1)
ctx->base.throttling = FALSE;
else if (throttling_value_user >= 0) {
ctx->base.throttling = TRUE;
ctx->base.throttling_value = throttling_value_user;
}
}
if (driCheckOption(&userInitOptions, "vblank_mode", DRI_ENUM))
ctx->base.vblank_mode = driQueryOptioni(&userInitOptions, "vblank_mode");
else
ctx->base.vblank_mode = 1;
if (driCheckOption(&userInitOptions, "thread_submit", DRI_BOOL))
ctx->base.thread_submit = driQueryOptionb(&userInitOptions, "thread_submit");
else
ctx->base.thread_submit = different_device;
if (driCheckOption(&userInitOptions, "override_vendorid", DRI_INT)) {
override_vendorid = driQueryOptioni(&userInitOptions, "override_vendorid");
}
if (driCheckOption(&userInitOptions, "discard_delayed_release", DRI_BOOL))
ctx->base.discard_delayed_release = driQueryOptionb(&userInitOptions, "discard_delayed_release");
else
ctx->base.discard_delayed_release = TRUE;
if (driCheckOption(&userInitOptions, "tearfree_discard", DRI_BOOL))
ctx->base.tearfree_discard = driQueryOptionb(&userInitOptions, "tearfree_discard");
else
ctx->base.tearfree_discard = FALSE;
if (ctx->base.tearfree_discard && !ctx->base.discard_delayed_release) {
ERR("tearfree_discard requires discard_delayed_release\n");
ctx->base.tearfree_discard = FALSE;
}
if (driCheckOption(&userInitOptions, "csmt_force", DRI_INT))
ctx->base.csmt_force = driQueryOptioni(&userInitOptions, "csmt_force");
else
ctx->base.csmt_force = -1;
if (driCheckOption(&userInitOptions, "dynamic_texture_workaround", DRI_BOOL))
ctx->base.dynamic_texture_workaround = driQueryOptionb(&userInitOptions, "dynamic_texture_workaround");
else
ctx->base.dynamic_texture_workaround = FALSE;
if (driCheckOption(&userInitOptions, "shader_inline_constants", DRI_BOOL))
ctx->base.shader_inline_constants = driQueryOptionb(&userInitOptions, "shader_inline_constants");
else
ctx->base.shader_inline_constants = FALSE;
driDestroyOptionCache(&userInitOptions);
driDestroyOptionInfo(&defaultInitOptions);
/* wrap it to create a software screen that can share resources */
if (pipe_loader_sw_probe_wrapped(&ctx->swdev, ctx->base.hal))
ctx->base.ref = pipe_loader_create_screen(ctx->swdev);
if (!ctx->base.ref) {
ERR("Couldn't wrap drm screen to swrast screen. Software devices "
"will be unavailable.\n");
}
/* read out PCI info */
read_descriptor(&ctx->base, fd, override_vendorid);
/* create and return new ID3DAdapter9 */
hr = NineAdapter9_new(&ctx->base, (struct NineAdapter9 **)ppAdapter);
if (FAILED(hr)) {
drm_destroy(&ctx->base);
return hr;
}
return D3D_OK;
}
/* Create the device specific rendering context.
*/
GLboolean r200CreateContext( gl_api api,
const struct gl_config *glVisual,
__DRIcontext *driContextPriv,
const struct __DriverContextConfig *ctx_config,
unsigned *error,
void *sharedContextPrivate)
{
__DRIscreen *sPriv = driContextPriv->driScreenPriv;
radeonScreenPtr screen = (radeonScreenPtr)(sPriv->driverPrivate);
struct dd_function_table functions;
r200ContextPtr rmesa;
struct gl_context *ctx;
int i;
int tcl_mode;
if (ctx_config->flags & ~(__DRI_CTX_FLAG_DEBUG | __DRI_CTX_FLAG_NO_ERROR)) {
*error = __DRI_CTX_ERROR_UNKNOWN_FLAG;
return false;
}
if (ctx_config->attribute_mask) {
*error = __DRI_CTX_ERROR_UNKNOWN_ATTRIBUTE;
return false;
}
assert(driContextPriv);
assert(screen);
/* Allocate the R200 context */
rmesa = calloc(1, sizeof(*rmesa));
if ( !rmesa ) {
*error = __DRI_CTX_ERROR_NO_MEMORY;
return GL_FALSE;
}
rmesa->radeon.radeonScreen = screen;
r200_init_vtbl(&rmesa->radeon);
/* init exp fog table data */
radeonInitStaticFogData();
/* Parse configuration files.
* Do this here so that initialMaxAnisotropy is set before we create
* the default textures.
*/
driParseConfigFiles (&rmesa->radeon.optionCache, &screen->optionCache,
screen->driScreen->myNum, "r200", NULL);
rmesa->radeon.initialMaxAnisotropy = driQueryOptionf(&rmesa->radeon.optionCache,
"def_max_anisotropy");
if (driQueryOptionb( &rmesa->radeon.optionCache, "hyperz"))
rmesa->using_hyperz = GL_TRUE;
/* Init default driver functions then plug in our R200-specific functions
* (the texture functions are especially important)
*/
_mesa_init_driver_functions(&functions);
_tnl_init_driver_draw_function(&functions);
r200InitDriverFuncs(&functions);
r200InitIoctlFuncs(&functions);
r200InitStateFuncs(&rmesa->radeon, &functions);
r200InitTextureFuncs(&rmesa->radeon, &functions);
r200InitShaderFuncs(&functions);
radeonInitQueryObjFunctions(&functions);
if (!radeonInitContext(&rmesa->radeon, api, &functions,
glVisual, driContextPriv,
sharedContextPrivate)) {
free(rmesa);
*error = __DRI_CTX_ERROR_NO_MEMORY;
return GL_FALSE;
}
rmesa->radeon.swtcl.RenderIndex = ~0;
rmesa->radeon.hw.all_dirty = 1;
ctx = &rmesa->radeon.glCtx;
driContextSetFlags(ctx, ctx_config->flags);
/* Initialize the software rasterizer and helper modules.
*/
_swrast_CreateContext( ctx );
_vbo_CreateContext( ctx );
_tnl_CreateContext( ctx );
_swsetup_CreateContext( ctx );
ctx->Const.MaxTextureUnits = driQueryOptioni (&rmesa->radeon.optionCache,
"texture_units");
ctx->Const.Program[MESA_SHADER_FRAGMENT].MaxTextureImageUnits = ctx->Const.MaxTextureUnits;
ctx->Const.MaxTextureCoordUnits = ctx->Const.MaxTextureUnits;
ctx->Const.MaxCombinedTextureImageUnits = ctx->Const.MaxTextureUnits;
ctx->Const.StripTextureBorder = GL_TRUE;
/* FIXME: When no memory manager is available we should set this
* to some reasonable value based on texture memory pool size */
ctx->Const.MaxTextureLevels = 12;
ctx->Const.Max3DTextureLevels = 9;
ctx->Const.MaxCubeTextureLevels = 12;
ctx->Const.MaxTextureRectSize = 2048;
ctx->Const.MaxRenderbufferSize = 2048;
ctx->Const.MaxTextureMaxAnisotropy = 16.0;
/* No wide AA points.
*/
ctx->Const.MinPointSize = 1.0;
ctx->Const.MinPointSizeAA = 1.0;
ctx->Const.MaxPointSizeAA = 1.0;
ctx->Const.PointSizeGranularity = 0.0625;
ctx->Const.MaxPointSize = 2047.0;
/* mesa initialization problem - _mesa_init_point was already called */
ctx->Point.MaxSize = ctx->Const.MaxPointSize;
ctx->Const.MinLineWidth = 1.0;
ctx->Const.MinLineWidthAA = 1.0;
ctx->Const.MaxLineWidth = 10.0;
ctx->Const.MaxLineWidthAA = 10.0;
ctx->Const.LineWidthGranularity = 0.0625;
ctx->Const.Program[MESA_SHADER_VERTEX].MaxNativeInstructions = R200_VSF_MAX_INST;
ctx->Const.Program[MESA_SHADER_VERTEX].MaxNativeAttribs = 12;
ctx->Const.Program[MESA_SHADER_VERTEX].MaxNativeTemps = R200_VSF_MAX_TEMPS;
ctx->Const.Program[MESA_SHADER_VERTEX].MaxNativeParameters = R200_VSF_MAX_PARAM;
ctx->Const.Program[MESA_SHADER_VERTEX].MaxNativeAddressRegs = 1;
ctx->Const.MaxDrawBuffers = 1;
ctx->Const.MaxColorAttachments = 1;
ctx->Const.ShaderCompilerOptions[MESA_SHADER_VERTEX].OptimizeForAOS = GL_TRUE;
/* Install the customized pipeline:
*/
_tnl_destroy_pipeline( ctx );
_tnl_install_pipeline( ctx, r200_pipeline );
/* Try and keep materials and vertices separate:
*/
/* _tnl_isolate_materials( ctx, GL_TRUE ); */
/* Configure swrast and TNL to match hardware characteristics:
*/
_swrast_allow_pixel_fog( ctx, GL_FALSE );
_swrast_allow_vertex_fog( ctx, GL_TRUE );
_tnl_allow_pixel_fog( ctx, GL_FALSE );
_tnl_allow_vertex_fog( ctx, GL_TRUE );
for ( i = 0 ; i < R200_MAX_TEXTURE_UNITS ; i++ ) {
_math_matrix_ctr( &rmesa->TexGenMatrix[i] );
_math_matrix_set_identity( &rmesa->TexGenMatrix[i] );
}
_math_matrix_ctr( &rmesa->tmpmat );
_math_matrix_set_identity( &rmesa->tmpmat );
ctx->Extensions.ARB_occlusion_query = true;
ctx->Extensions.ARB_point_sprite = true;
ctx->Extensions.ARB_texture_border_clamp = true;
ctx->Extensions.ARB_texture_cube_map = true;
ctx->Extensions.ARB_texture_env_combine = true;
ctx->Extensions.ARB_texture_env_dot3 = true;
ctx->Extensions.ARB_texture_env_crossbar = true;
ctx->Extensions.ARB_texture_filter_anisotropic = true;
ctx->Extensions.ARB_texture_mirror_clamp_to_edge = true;
ctx->Extensions.ARB_vertex_program = true;
ctx->Extensions.ATI_fragment_shader = (ctx->Const.MaxTextureUnits == 6);
ctx->Extensions.ATI_texture_env_combine3 = true;
ctx->Extensions.ATI_texture_mirror_once = true;
ctx->Extensions.EXT_blend_color = true;
ctx->Extensions.EXT_blend_equation_separate = true;
ctx->Extensions.EXT_blend_func_separate = true;
ctx->Extensions.EXT_blend_minmax = true;
ctx->Extensions.EXT_gpu_program_parameters = true;
ctx->Extensions.EXT_point_parameters = true;
ctx->Extensions.EXT_texture_env_dot3 = true;
ctx->Extensions.EXT_texture_filter_anisotropic = true;
ctx->Extensions.EXT_texture_mirror_clamp = true;
ctx->Extensions.MESA_pack_invert = true;
ctx->Extensions.NV_fog_distance = true;
ctx->Extensions.NV_texture_rectangle = true;
ctx->Extensions.OES_EGL_image = true;
if (!(rmesa->radeon.radeonScreen->chip_flags & R200_CHIPSET_YCBCR_BROKEN)) {
/* yuv textures don't work with some chips - R200 / rv280 okay so far
others get the bit ordering right but don't actually do YUV-RGB conversion */
ctx->Extensions.MESA_ycbcr_texture = true;
}
ctx->Extensions.EXT_texture_compression_s3tc = true;
ctx->Extensions.ANGLE_texture_compression_dxt = true;
#if 0
r200InitDriverFuncs( ctx );
r200InitIoctlFuncs( ctx );
r200InitStateFuncs( ctx );
r200InitTextureFuncs( ctx );
#endif
/* plug in a few more device driver functions */
/* XXX these should really go right after _mesa_init_driver_functions() */
radeon_fbo_init(&rmesa->radeon);
radeonInitSpanFuncs( ctx );
r200InitTnlFuncs( ctx );
r200InitState( rmesa );
r200InitSwtcl( ctx );
rmesa->prefer_gart_client_texturing =
(getenv("R200_GART_CLIENT_TEXTURES") != 0);
tcl_mode = driQueryOptioni(&rmesa->radeon.optionCache, "tcl_mode");
if (getenv("R200_NO_RAST")) {
fprintf(stderr, "disabling 3D acceleration\n");
FALLBACK(rmesa, R200_FALLBACK_DISABLE, 1);
}
else if (tcl_mode == DRI_CONF_TCL_SW || getenv("R200_NO_TCL") ||
!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
rmesa->radeon.radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL;
fprintf(stderr, "Disabling HW TCL support\n");
}
TCL_FALLBACK(&rmesa->radeon.glCtx, R200_TCL_FALLBACK_TCL_DISABLE, 1);
}
_mesa_override_extensions(ctx);
_mesa_compute_version(ctx);
/* Exec table initialization requires the version to be computed */
_mesa_initialize_dispatch_tables(ctx);
_mesa_initialize_vbo_vtxfmt(ctx);
*error = __DRI_CTX_ERROR_SUCCESS;
return GL_TRUE;
}
GLboolean
sisCreateContext( const __GLcontextModes *glVisual,
__DRIcontextPrivate *driContextPriv,
void *sharedContextPrivate )
{
GLcontext *ctx, *shareCtx;
__DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
sisContextPtr smesa;
sisScreenPtr sisScreen;
int i;
struct dd_function_table functions;
smesa = (sisContextPtr)CALLOC( sizeof(*smesa) );
if (smesa == NULL)
return GL_FALSE;
/* Init default driver functions then plug in our SIS-specific functions
* (the texture functions are especially important)
*/
_mesa_init_driver_functions(&functions);
sisInitDriverFuncs(&functions);
sisInitTextureFuncs(&functions);
/* Allocate the Mesa context */
if (sharedContextPrivate)
shareCtx = ((sisContextPtr)sharedContextPrivate)->glCtx;
else
shareCtx = NULL;
smesa->glCtx = _mesa_create_context( glVisual, shareCtx,
&functions, (void *) smesa);
if (!smesa->glCtx) {
FREE(smesa);
return GL_FALSE;
}
driContextPriv->driverPrivate = smesa;
ctx = smesa->glCtx;
sisScreen = smesa->sisScreen = (sisScreenPtr)(sPriv->private);
smesa->driContext = driContextPriv;
smesa->driScreen = sPriv;
smesa->driDrawable = NULL;
smesa->hHWContext = driContextPriv->hHWContext;
smesa->driHwLock = &sPriv->pSAREA->lock;
smesa->driFd = sPriv->fd;
smesa->virtualX = sisScreen->screenX;
smesa->virtualY = sisScreen->screenY;
smesa->bytesPerPixel = sisScreen->cpp;
smesa->IOBase = sisScreen->mmio.map;
smesa->Chipset = sisScreen->deviceID;
smesa->irqEnabled = sisScreen->irqEnabled;
smesa->FbBase = sPriv->pFB;
smesa->displayWidth = sPriv->fbWidth;
smesa->frontPitch = sPriv->fbStride;
smesa->sarea = (SISSAREAPriv *)((char *)sPriv->pSAREA +
sisScreen->sarea_priv_offset);
#if defined(SIS_DUMP)
IOBase4Debug = GET_IOBase (smesa);
#endif
/* support ARGB8888 and RGB565 */
switch (smesa->bytesPerPixel)
{
case 4:
smesa->redMask = 0x00ff0000;
smesa->greenMask = 0x0000ff00;
smesa->blueMask = 0x000000ff;
smesa->alphaMask = 0xff000000;
smesa->colorFormat = DST_FORMAT_ARGB_8888;
break;
case 2:
smesa->redMask = 0xf800;
smesa->greenMask = 0x07e0;
smesa->blueMask = 0x001f;
smesa->alphaMask = 0;
smesa->colorFormat = DST_FORMAT_RGB_565;
break;
default:
sis_fatal_error("Bad bytesPerPixel.\n");
}
/* Parse configuration files */
driParseConfigFiles (&smesa->optionCache, &sisScreen->optionCache,
sisScreen->driScreen->myNum, "sis");
/* TODO: index mode */
smesa->CurrentQueueLenPtr = &(smesa->sarea->QueueLength);
smesa->FrameCountPtr = &(smesa->sarea->FrameCount);
/* set AGP */
smesa->AGPSize = sisScreen->agp.size;
smesa->AGPBase = sisScreen->agp.map;
smesa->AGPAddr = sisScreen->agp.handle;
/* Create AGP command buffer */
if (smesa->AGPSize != 0 &&
!driQueryOptionb(&smesa->optionCache, "agp_disable"))
{
smesa->vb = sisAllocAGP(smesa, 64 * 1024, &smesa->vb_agp_handle);
if (smesa->vb != NULL) {
smesa->using_agp = GL_TRUE;
smesa->vb_cur = smesa->vb;
smesa->vb_last = smesa->vb;
smesa->vb_end = smesa->vb + 64 * 1024;
smesa->vb_agp_offset = ((long)smesa->vb - (long)smesa->AGPBase +
(long)smesa->AGPAddr);
}
}
if (!smesa->using_agp) {
smesa->vb = malloc(64 * 1024);
if (smesa->vb == NULL) {
FREE(smesa);
return GL_FALSE;
}
smesa->vb_cur = smesa->vb;
smesa->vb_last = smesa->vb;
smesa->vb_end = smesa->vb + 64 * 1024;
}
smesa->GlobalFlag = 0L;
smesa->Fallback = 0;
/* Initialize the software rasterizer and helper modules.
*/
_swrast_CreateContext( ctx );
_ac_CreateContext( ctx );
_tnl_CreateContext( ctx );
_swsetup_CreateContext( ctx );
_swrast_allow_pixel_fog( ctx, GL_TRUE );
_swrast_allow_vertex_fog( ctx, GL_FALSE );
_tnl_allow_pixel_fog( ctx, GL_TRUE );
_tnl_allow_vertex_fog( ctx, GL_FALSE );
/* XXX these should really go right after _mesa_init_driver_functions() */
sisDDInitStateFuncs( ctx );
sisDDInitState( smesa ); /* Initializes smesa->zFormat, important */
sisInitTriFuncs( ctx );
sisDDInitSpanFuncs( ctx );
sisDDInitStencilFuncs( ctx );
driInitExtensions( ctx, card_extensions, GL_FALSE );
/* TODO */
/* smesa->blockWrite = SGRAMbw = IsBlockWrite (); */
smesa->blockWrite = GL_FALSE;
for (i = 0; i < SIS_MAX_TEXTURES; i++) {
smesa->TexStates[i] = 0;
smesa->PrevTexFormat[i] = 0;
}
return GL_TRUE;
}
bool
intelInitContext(struct brw_context *brw,
int api,
unsigned major_version,
unsigned minor_version,
const struct gl_config * mesaVis,
__DRIcontext * driContextPriv,
void *sharedContextPrivate,
struct dd_function_table *functions,
unsigned *dri_ctx_error)
{
struct gl_context *ctx = &brw->ctx;
struct gl_context *shareCtx = (struct gl_context *) sharedContextPrivate;
__DRIscreen *sPriv = driContextPriv->driScreenPriv;
struct intel_screen *intelScreen = sPriv->driverPrivate;
int bo_reuse_mode;
struct gl_config visual;
/* we can't do anything without a connection to the device */
if (intelScreen->bufmgr == NULL) {
*dri_ctx_error = __DRI_CTX_ERROR_NO_MEMORY;
return false;
}
if (!validate_context_version(intelScreen,
api, major_version, minor_version,
dri_ctx_error))
return false;
/* Can't rely on invalidate events, fall back to glViewport hack */
if (!driContextPriv->driScreenPriv->dri2.useInvalidate) {
brw->saved_viewport = functions->Viewport;
functions->Viewport = intel_viewport;
}
if (mesaVis == NULL) {
memset(&visual, 0, sizeof visual);
mesaVis = &visual;
}
brw->intelScreen = intelScreen;
if (!_mesa_initialize_context(&brw->ctx, api, mesaVis, shareCtx,
functions)) {
*dri_ctx_error = __DRI_CTX_ERROR_NO_MEMORY;
printf("%s: failed to init mesa context\n", __FUNCTION__);
return false;
}
driContextPriv->driverPrivate = brw;
brw->driContext = driContextPriv;
brw->gen = intelScreen->gen;
const int devID = intelScreen->deviceID;
if (IS_SNB_GT1(devID) || IS_IVB_GT1(devID) || IS_HSW_GT1(devID))
brw->gt = 1;
else if (IS_SNB_GT2(devID) || IS_IVB_GT2(devID) || IS_HSW_GT2(devID))
brw->gt = 2;
else if (IS_HSW_GT3(devID))
brw->gt = 3;
else
brw->gt = 0;
if (IS_HASWELL(devID)) {
brw->is_haswell = true;
} else if (IS_BAYTRAIL(devID)) {
brw->is_baytrail = true;
brw->gt = 1;
} else if (IS_G4X(devID)) {
brw->is_g4x = true;
}
brw->has_separate_stencil = brw->intelScreen->hw_has_separate_stencil;
brw->must_use_separate_stencil = brw->intelScreen->hw_must_use_separate_stencil;
brw->has_hiz = brw->gen >= 6;
brw->has_llc = brw->intelScreen->hw_has_llc;
brw->has_swizzling = brw->intelScreen->hw_has_swizzling;
memset(&ctx->TextureFormatSupported,
0, sizeof(ctx->TextureFormatSupported));
driParseConfigFiles(&brw->optionCache, &intelScreen->optionCache,
sPriv->myNum, "i965");
/* Estimate the size of the mappable aperture into the GTT. There's an
* ioctl to get the whole GTT size, but not one to get the mappable subset.
* It turns out it's basically always 256MB, though some ancient hardware
* was smaller.
*/
uint32_t gtt_size = 256 * 1024 * 1024;
/* We don't want to map two objects such that a memcpy between them would
* just fault one mapping in and then the other over and over forever. So
* we would need to divide the GTT size by 2. Additionally, some GTT is
* taken up by things like the framebuffer and the ringbuffer and such, so
* be more conservative.
*/
brw->max_gtt_map_object_size = gtt_size / 4;
brw->bufmgr = intelScreen->bufmgr;
bo_reuse_mode = driQueryOptioni(&brw->optionCache, "bo_reuse");
switch (bo_reuse_mode) {
case DRI_CONF_BO_REUSE_DISABLED:
break;
case DRI_CONF_BO_REUSE_ALL:
intel_bufmgr_gem_enable_reuse(brw->bufmgr);
break;
}
/* Initialize the software rasterizer and helper modules.
*
* As of GL 3.1 core, the gen4+ driver doesn't need the swrast context for
* software fallbacks (which we have to support on legacy GL to do weird
* glDrawPixels(), glBitmap(), and other functions).
*/
if (api != API_OPENGL_CORE && api != API_OPENGLES2) {
_swrast_CreateContext(ctx);
}
_vbo_CreateContext(ctx);
if (ctx->swrast_context) {
_tnl_CreateContext(ctx);
_swsetup_CreateContext(ctx);
/* Configure swrast to match hardware characteristics: */
_swrast_allow_pixel_fog(ctx, false);
_swrast_allow_vertex_fog(ctx, true);
}
_mesa_meta_init(ctx);
intelInitExtensions(ctx);
INTEL_DEBUG = driParseDebugString(getenv("INTEL_DEBUG"), debug_control);
if (INTEL_DEBUG & DEBUG_BUFMGR)
dri_bufmgr_set_debug(brw->bufmgr, true);
if ((INTEL_DEBUG & DEBUG_SHADER_TIME) && brw->gen < 7) {
fprintf(stderr,
"shader_time debugging requires gen7 (Ivybridge) or better.\n");
INTEL_DEBUG &= ~DEBUG_SHADER_TIME;
}
if (INTEL_DEBUG & DEBUG_PERF)
brw->perf_debug = true;
if (INTEL_DEBUG & DEBUG_AUB)
drm_intel_bufmgr_gem_set_aub_dump(brw->bufmgr, true);
intel_batchbuffer_init(brw);
intel_fbo_init(brw);
if (!driQueryOptionb(&brw->optionCache, "hiz")) {
brw->has_hiz = false;
/* On gen6, you can only do separate stencil with HIZ. */
if (brw->gen == 6)
brw->has_separate_stencil = false;
}
if (driQueryOptionb(&brw->optionCache, "always_flush_batch")) {
fprintf(stderr, "flushing batchbuffer before/after each draw call\n");
brw->always_flush_batch = 1;
}
if (driQueryOptionb(&brw->optionCache, "always_flush_cache")) {
fprintf(stderr, "flushing GPU caches before/after each draw call\n");
brw->always_flush_cache = 1;
}
if (driQueryOptionb(&brw->optionCache, "disable_throttling")) {
fprintf(stderr, "disabling flush throttling\n");
brw->disable_throttling = 1;
}
return true;
}
/* Create the device specific context.
*/
GLboolean
r100CreateContext( gl_api api,
const struct gl_config *glVisual,
__DRIcontext *driContextPriv,
unsigned major_version,
unsigned minor_version,
uint32_t flags,
unsigned *error,
void *sharedContextPrivate)
{
__DRIscreen *sPriv = driContextPriv->driScreenPriv;
radeonScreenPtr screen = (radeonScreenPtr)(sPriv->driverPrivate);
struct dd_function_table functions;
r100ContextPtr rmesa;
struct gl_context *ctx;
int i;
int tcl_mode, fthrottle_mode;
switch (api) {
case API_OPENGL_COMPAT:
if (major_version > 1 || minor_version > 3) {
*error = __DRI_CTX_ERROR_BAD_VERSION;
return GL_FALSE;
}
break;
case API_OPENGLES:
break;
default:
*error = __DRI_CTX_ERROR_BAD_API;
return GL_FALSE;
}
/* Flag filtering is handled in dri2CreateContextAttribs.
*/
(void) flags;
assert(glVisual);
assert(driContextPriv);
assert(screen);
/* Allocate the Radeon context */
rmesa = calloc(1, sizeof(*rmesa));
if ( !rmesa ) {
*error = __DRI_CTX_ERROR_NO_MEMORY;
return GL_FALSE;
}
rmesa->radeon.radeonScreen = screen;
r100_init_vtbl(&rmesa->radeon);
/* init exp fog table data */
radeonInitStaticFogData();
/* Parse configuration files.
* Do this here so that initialMaxAnisotropy is set before we create
* the default textures.
*/
driParseConfigFiles (&rmesa->radeon.optionCache, &screen->optionCache,
screen->driScreen->myNum, "radeon");
rmesa->radeon.initialMaxAnisotropy = driQueryOptionf(&rmesa->radeon.optionCache,
"def_max_anisotropy");
if ( driQueryOptionb( &rmesa->radeon.optionCache, "hyperz" ) ) {
if ( sPriv->drm_version.minor < 13 )
fprintf( stderr, "DRM version 1.%d too old to support HyperZ, "
"disabling.\n", sPriv->drm_version.minor );
else
rmesa->using_hyperz = GL_TRUE;
}
if ( sPriv->drm_version.minor >= 15 )
rmesa->texmicrotile = GL_TRUE;
/* Init default driver functions then plug in our Radeon-specific functions
* (the texture functions are especially important)
*/
_mesa_init_driver_functions( &functions );
radeonInitTextureFuncs( &rmesa->radeon, &functions );
radeonInitQueryObjFunctions(&functions);
if (!radeonInitContext(&rmesa->radeon, &functions,
glVisual, driContextPriv,
sharedContextPrivate)) {
free(rmesa);
*error = __DRI_CTX_ERROR_NO_MEMORY;
return GL_FALSE;
}
rmesa->radeon.swtcl.RenderIndex = ~0;
rmesa->radeon.hw.all_dirty = GL_TRUE;
ctx = &rmesa->radeon.glCtx;
/* Initialize the software rasterizer and helper modules.
*/
_swrast_CreateContext( ctx );
_vbo_CreateContext( ctx );
_tnl_CreateContext( ctx );
_swsetup_CreateContext( ctx );
_ae_create_context( ctx );
/* Set the maximum texture size small enough that we can guarentee that
* all texture units can bind a maximal texture and have all of them in
* texturable memory at once. Depending on the allow_large_textures driconf
* setting allow larger textures.
*/
ctx->Const.MaxTextureUnits = driQueryOptioni (&rmesa->radeon.optionCache,
"texture_units");
ctx->Const.FragmentProgram.MaxTextureImageUnits = ctx->Const.MaxTextureUnits;
ctx->Const.MaxTextureCoordUnits = ctx->Const.MaxTextureUnits;
ctx->Const.MaxCombinedTextureImageUnits = ctx->Const.MaxTextureUnits;
ctx->Const.StripTextureBorder = GL_TRUE;
i = driQueryOptioni( &rmesa->radeon.optionCache, "allow_large_textures");
/* FIXME: When no memory manager is available we should set this
* to some reasonable value based on texture memory pool size */
ctx->Const.MaxTextureLevels = 12;
ctx->Const.Max3DTextureLevels = 9;
ctx->Const.MaxCubeTextureLevels = 12;
ctx->Const.MaxTextureRectSize = 2048;
ctx->Const.MaxTextureMaxAnisotropy = 16.0;
/* No wide points.
*/
ctx->Const.MinPointSize = 1.0;
ctx->Const.MinPointSizeAA = 1.0;
ctx->Const.MaxPointSize = 1.0;
ctx->Const.MaxPointSizeAA = 1.0;
ctx->Const.MinLineWidth = 1.0;
ctx->Const.MinLineWidthAA = 1.0;
ctx->Const.MaxLineWidth = 10.0;
ctx->Const.MaxLineWidthAA = 10.0;
ctx->Const.LineWidthGranularity = 0.0625;
/* Set maxlocksize (and hence vb size) small enough to avoid
* fallbacks in radeon_tcl.c. ie. guarentee that all vertices can
* fit in a single dma buffer for indexed rendering of quad strips,
* etc.
*/
ctx->Const.MaxArrayLockSize =
MIN2( ctx->Const.MaxArrayLockSize,
RADEON_BUFFER_SIZE / RADEON_MAX_TCL_VERTSIZE );
rmesa->boxes = 0;
ctx->Const.MaxDrawBuffers = 1;
ctx->Const.MaxColorAttachments = 1;
ctx->Const.MaxRenderbufferSize = 2048;
ctx->ShaderCompilerOptions[MESA_SHADER_VERTEX].PreferDP4 = true;
/* Install the customized pipeline:
*/
_tnl_destroy_pipeline( ctx );
_tnl_install_pipeline( ctx, radeon_pipeline );
/* Try and keep materials and vertices separate:
*/
/* _tnl_isolate_materials( ctx, GL_TRUE ); */
/* Configure swrast and T&L to match hardware characteristics:
*/
_swrast_allow_pixel_fog( ctx, GL_FALSE );
_swrast_allow_vertex_fog( ctx, GL_TRUE );
_tnl_allow_pixel_fog( ctx, GL_FALSE );
_tnl_allow_vertex_fog( ctx, GL_TRUE );
for ( i = 0 ; i < RADEON_MAX_TEXTURE_UNITS ; i++ ) {
_math_matrix_ctr( &rmesa->TexGenMatrix[i] );
_math_matrix_ctr( &rmesa->tmpmat[i] );
_math_matrix_set_identity( &rmesa->TexGenMatrix[i] );
_math_matrix_set_identity( &rmesa->tmpmat[i] );
}
ctx->Extensions.ARB_texture_border_clamp = true;
ctx->Extensions.ARB_texture_env_combine = true;
ctx->Extensions.ARB_texture_env_crossbar = true;
ctx->Extensions.ARB_texture_env_dot3 = true;
ctx->Extensions.EXT_fog_coord = true;
ctx->Extensions.EXT_packed_depth_stencil = true;
ctx->Extensions.EXT_secondary_color = true;
ctx->Extensions.EXT_texture_env_dot3 = true;
ctx->Extensions.EXT_texture_filter_anisotropic = true;
ctx->Extensions.EXT_texture_mirror_clamp = true;
ctx->Extensions.ATI_texture_env_combine3 = true;
ctx->Extensions.ATI_texture_mirror_once = true;
ctx->Extensions.MESA_ycbcr_texture = true;
ctx->Extensions.NV_blend_square = true;
ctx->Extensions.OES_EGL_image = true;
ctx->Extensions.EXT_framebuffer_object = true;
ctx->Extensions.ARB_texture_cube_map = true;
if (rmesa->radeon.glCtx.Mesa_DXTn) {
ctx->Extensions.EXT_texture_compression_s3tc = true;
ctx->Extensions.ANGLE_texture_compression_dxt = true;
}
else if (driQueryOptionb (&rmesa->radeon.optionCache, "force_s3tc_enable")) {
ctx->Extensions.EXT_texture_compression_s3tc = true;
ctx->Extensions.ANGLE_texture_compression_dxt = true;
}
ctx->Extensions.NV_texture_rectangle = true;
ctx->Extensions.ARB_occlusion_query = true;
/* XXX these should really go right after _mesa_init_driver_functions() */
radeon_fbo_init(&rmesa->radeon);
radeonInitSpanFuncs( ctx );
radeonInitIoctlFuncs( ctx );
radeonInitStateFuncs( ctx );
radeonInitState( rmesa );
radeonInitSwtcl( ctx );
_mesa_vector4f_alloc( &rmesa->tcl.ObjClean, 0,
ctx->Const.MaxArrayLockSize, 32 );
fthrottle_mode = driQueryOptioni(&rmesa->radeon.optionCache, "fthrottle_mode");
rmesa->radeon.iw.irq_seq = -1;
rmesa->radeon.irqsEmitted = 0;
rmesa->radeon.do_irqs = (rmesa->radeon.radeonScreen->irq != 0 &&
fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS);
rmesa->radeon.do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
#if DO_DEBUG
RADEON_DEBUG = driParseDebugString( getenv( "RADEON_DEBUG" ),
debug_control );
#endif
tcl_mode = driQueryOptioni(&rmesa->radeon.optionCache, "tcl_mode");
if (driQueryOptionb(&rmesa->radeon.optionCache, "no_rast")) {
fprintf(stderr, "disabling 3D acceleration\n");
FALLBACK(rmesa, RADEON_FALLBACK_DISABLE, 1);
} else if (tcl_mode == DRI_CONF_TCL_SW ||
!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
rmesa->radeon.radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL;
fprintf(stderr, "Disabling HW TCL support\n");
}
TCL_FALLBACK(&rmesa->radeon.glCtx, RADEON_TCL_FALLBACK_TCL_DISABLE, 1);
}
if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
/* _tnl_need_dlist_norm_lengths( ctx, GL_FALSE ); */
}
_mesa_compute_version(ctx);
/* Exec table initialization requires the version to be computed */
_mesa_initialize_dispatch_tables(ctx);
_mesa_initialize_vbo_vtxfmt(ctx);
*error = __DRI_CTX_ERROR_SUCCESS;
return GL_TRUE;
}
/* Create the device specific context.
*/
GLboolean mach64CreateContext( const __GLcontextModes *glVisual,
__DRIcontextPrivate *driContextPriv,
void *sharedContextPrivate )
{
GLcontext *ctx, *shareCtx;
__DRIscreenPrivate *driScreen = driContextPriv->driScreenPriv;
struct dd_function_table functions;
mach64ContextPtr mmesa;
mach64ScreenPtr mach64Screen;
int i, heap;
GLuint *c_textureSwapsPtr = NULL;
#if DO_DEBUG
MACH64_DEBUG = driParseDebugString(getenv("MACH64_DEBUG"), debug_control);
#endif
/* Allocate the mach64 context */
mmesa = (mach64ContextPtr) CALLOC( sizeof(*mmesa) );
if ( !mmesa )
return GL_FALSE;
/* Init default driver functions then plug in our Mach64-specific functions
* (the texture functions are especially important)
*/
_mesa_init_driver_functions( &functions );
mach64InitDriverFuncs( &functions );
mach64InitIoctlFuncs( &functions );
mach64InitTextureFuncs( &functions );
/* Allocate the Mesa context */
if (sharedContextPrivate)
shareCtx = ((mach64ContextPtr) sharedContextPrivate)->glCtx;
else
shareCtx = NULL;
mmesa->glCtx = _mesa_create_context(glVisual, shareCtx,
&functions, (void *)mmesa);
if (!mmesa->glCtx) {
FREE(mmesa);
return GL_FALSE;
}
driContextPriv->driverPrivate = mmesa;
ctx = mmesa->glCtx;
mmesa->driContext = driContextPriv;
mmesa->driScreen = driScreen;
mmesa->driDrawable = NULL;
mmesa->hHWContext = driContextPriv->hHWContext;
mmesa->driHwLock = &driScreen->pSAREA->lock;
mmesa->driFd = driScreen->fd;
mach64Screen = mmesa->mach64Screen = (mach64ScreenPtr)driScreen->private;
/* Parse configuration files */
driParseConfigFiles (&mmesa->optionCache, &mach64Screen->optionCache,
mach64Screen->driScreen->myNum, "mach64");
mmesa->sarea = (drm_mach64_sarea_t *)((char *)driScreen->pSAREA +
sizeof(drm_sarea_t));
mmesa->CurrentTexObj[0] = NULL;
mmesa->CurrentTexObj[1] = NULL;
(void) memset( mmesa->texture_heaps, 0, sizeof( mmesa->texture_heaps ) );
make_empty_list( &mmesa->swapped );
mmesa->firstTexHeap = mach64Screen->firstTexHeap;
mmesa->lastTexHeap = mach64Screen->firstTexHeap + mach64Screen->numTexHeaps;
for ( i = mmesa->firstTexHeap ; i < mmesa->lastTexHeap ; i++ ) {
mmesa->texture_heaps[i] = driCreateTextureHeap( i, mmesa,
mach64Screen->texSize[i],
6, /* align to 64-byte boundary, use 12 for page-size boundary */
MACH64_NR_TEX_REGIONS,
(drmTextureRegionPtr)mmesa->sarea->tex_list[i],
&mmesa->sarea->tex_age[i],
&mmesa->swapped,
sizeof( mach64TexObj ),
(destroy_texture_object_t *) mach64DestroyTexObj );
#if ENABLE_PERF_BOXES
c_textureSwapsPtr = & mmesa->c_textureSwaps;
#endif
driSetTextureSwapCounterLocation( mmesa->texture_heaps[i],
c_textureSwapsPtr );
}
mmesa->RenderIndex = -1; /* Impossible value */
mmesa->vert_buf = NULL;
mmesa->num_verts = 0;
mmesa->new_state = MACH64_NEW_ALL;
mmesa->dirty = MACH64_UPLOAD_ALL;
/* Set the maximum texture size small enough that we can
* guarentee that both texture units can bind a maximal texture
* and have them both in memory (on-card or AGP) at once.
* Test for 2 textures * bytes/texel * size * size. There's no
* need to account for mipmaps since we only upload one level.
*/
ctx->Const.MaxTextureUnits = 2;
ctx->Const.MaxTextureImageUnits = 2;
ctx->Const.MaxTextureCoordUnits = 2;
heap = mach64Screen->IsPCI ? MACH64_CARD_HEAP : MACH64_AGP_HEAP;
driCalculateMaxTextureLevels( & mmesa->texture_heaps[heap],
1,
& ctx->Const,
mach64Screen->cpp,
10, /* max 2D texture size is 1024x1024 */
0, /* 3D textures unsupported. */
0, /* cube textures unsupported. */
0, /* texture rectangles unsupported. */
1, /* mipmapping unsupported. */
GL_TRUE, /* need to have both textures in
either local or AGP memory */
0 );
#if ENABLE_PERF_BOXES
mmesa->boxes = ( getenv( "LIBGL_PERFORMANCE_BOXES" ) != NULL );
#endif
/* Allocate the vertex buffer
*/
mmesa->vert_buf = ALIGN_MALLOC(MACH64_BUFFER_SIZE, 32);
if ( !mmesa->vert_buf )
return GL_FALSE;
mmesa->vert_used = 0;
mmesa->vert_total = MACH64_BUFFER_SIZE;
/* Initialize the software rasterizer and helper modules.
*/
_swrast_CreateContext( ctx );
_vbo_CreateContext( ctx );
_tnl_CreateContext( ctx );
_swsetup_CreateContext( ctx );
/* Install the customized pipeline:
*/
/* _tnl_destroy_pipeline( ctx ); */
/* _tnl_install_pipeline( ctx, mach64_pipeline ); */
/* Configure swrast and T&L to match hardware characteristics:
*/
_swrast_allow_pixel_fog( ctx, GL_FALSE );
_swrast_allow_vertex_fog( ctx, GL_TRUE );
_tnl_allow_pixel_fog( ctx, GL_FALSE );
_tnl_allow_vertex_fog( ctx, GL_TRUE );
driInitExtensions( ctx, card_extensions, GL_TRUE );
mach64InitVB( ctx );
mach64InitTriFuncs( ctx );
mach64DDInitStateFuncs( ctx );
mach64DDInitSpanFuncs( ctx );
mach64DDInitState( mmesa );
mmesa->do_irqs = (mmesa->mach64Screen->irq && !getenv("MACH64_NO_IRQS"));
mmesa->vblank_flags = (mmesa->do_irqs)
? driGetDefaultVBlankFlags(&mmesa->optionCache) : VBLANK_FLAG_NO_IRQ;
driContextPriv->driverPrivate = (void *)mmesa;
if (driQueryOptionb(&mmesa->optionCache, "no_rast")) {
fprintf(stderr, "disabling 3D acceleration\n");
FALLBACK(mmesa, MACH64_FALLBACK_DISABLE, 1);
}
return GL_TRUE;
}
static HRESULT WINAPI
drm_create_adapter( int fd,
ID3DAdapter9 **ppAdapter )
{
struct d3dadapter9drm_context *ctx = CALLOC_STRUCT(d3dadapter9drm_context);
HRESULT hr;
int i, different_device;
const struct drm_conf_ret *throttle_ret = NULL;
const struct drm_conf_ret *dmabuf_ret = NULL;
driOptionCache defaultInitOptions;
driOptionCache userInitOptions;
int throttling_value_user = -2;
#if !GALLIUM_STATIC_TARGETS
const char *paths[] = {
getenv("D3D9_DRIVERS_PATH"),
getenv("D3D9_DRIVERS_DIR"),
PIPE_SEARCH_DIR
};
#endif
if (!ctx) { return E_OUTOFMEMORY; }
ctx->base.destroy = drm_destroy;
fd = loader_get_user_preferred_fd(fd, &different_device);
ctx->fd = fd;
ctx->base.linear_framebuffer = !!different_device;
#if GALLIUM_STATIC_TARGETS
ctx->base.hal = dd_create_screen(fd);
#else
/* use pipe-loader to dlopen appropriate drm driver */
if (!pipe_loader_drm_probe_fd(&ctx->dev, fd, FALSE)) {
ERR("Failed to probe drm fd %d.\n", fd);
FREE(ctx);
close(fd);
return D3DERR_DRIVERINTERNALERROR;
}
/* use pipe-loader to create a drm screen (hal) */
ctx->base.hal = NULL;
for (i = 0; !ctx->base.hal && i < Elements(paths); ++i) {
if (!paths[i]) { continue; }
ctx->base.hal = pipe_loader_create_screen(ctx->dev, paths[i]);
}
#endif
if (!ctx->base.hal) {
ERR("Unable to load requested driver.\n");
drm_destroy(&ctx->base);
return D3DERR_DRIVERINTERNALERROR;
}
#if GALLIUM_STATIC_TARGETS
dmabuf_ret = dd_configuration(DRM_CONF_SHARE_FD);
throttle_ret = dd_configuration(DRM_CONF_THROTTLE);
#else
dmabuf_ret = pipe_loader_configuration(ctx->dev, DRM_CONF_SHARE_FD);
throttle_ret = pipe_loader_configuration(ctx->dev, DRM_CONF_THROTTLE);
#endif // GALLIUM_STATIC_TARGETS
if (!dmabuf_ret || !dmabuf_ret->val.val_bool) {
ERR("The driver is not capable of dma-buf sharing."
"Abandon to load nine state tracker\n");
drm_destroy(&ctx->base);
return D3DERR_DRIVERINTERNALERROR;
}
if (throttle_ret && throttle_ret->val.val_int != -1) {
ctx->base.throttling = TRUE;
ctx->base.throttling_value = throttle_ret->val.val_int;
} else
ctx->base.throttling = FALSE;
driParseOptionInfo(&defaultInitOptions, __driConfigOptionsNine);
driParseConfigFiles(&userInitOptions, &defaultInitOptions, 0, "nine");
if (driCheckOption(&userInitOptions, "throttle_value", DRI_INT)) {
throttling_value_user = driQueryOptioni(&userInitOptions, "throttle_value");
if (throttling_value_user == -1)
ctx->base.throttling = FALSE;
else if (throttling_value_user >= 0) {
ctx->base.throttling = TRUE;
ctx->base.throttling_value = throttling_value_user;
}
}
if (driCheckOption(&userInitOptions, "vblank_mode", DRI_ENUM))
ctx->base.vblank_mode = driQueryOptioni(&userInitOptions, "vblank_mode");
else
ctx->base.vblank_mode = 1;
if (driCheckOption(&userInitOptions, "thread_submit", DRI_BOOL)) {
ctx->base.thread_submit = driQueryOptionb(&userInitOptions, "thread_submit");
if (ctx->base.thread_submit && (throttling_value_user == -2 || throttling_value_user == 0)) {
ctx->base.throttling_value = 0;
} else if (ctx->base.thread_submit) {
DBG("You have set a non standard throttling value in combination with thread_submit."
"We advise to use a throttling value of -2/0");
}
if (ctx->base.thread_submit && !different_device)
DBG("You have set thread_submit but do not use a different device than the server."
"You should not expect any benefit.");
}
driDestroyOptionCache(&userInitOptions);
driDestroyOptionInfo(&defaultInitOptions);
#if GALLIUM_STATIC_TARGETS
ctx->base.ref = ninesw_create_screen(ctx->base.hal);
#else
/* wrap it to create a software screen that can share resources */
if (pipe_loader_sw_probe_wrapped(&ctx->swdev, ctx->base.hal)) {
ctx->base.ref = NULL;
for (i = 0; !ctx->base.ref && i < Elements(paths); ++i) {
if (!paths[i]) { continue; }
ctx->base.ref = pipe_loader_create_screen(ctx->swdev, paths[i]);
}
}
#endif
if (!ctx->base.ref) {
ERR("Couldn't wrap drm screen to swrast screen. Software devices "
"will be unavailable.\n");
}
/* read out PCI info */
read_descriptor(&ctx->base, fd);
/* create and return new ID3DAdapter9 */
hr = NineAdapter9_new(&ctx->base, (struct NineAdapter9 **)ppAdapter);
if (FAILED(hr)) {
drm_destroy(&ctx->base);
return hr;
}
return D3D_OK;
}
/**
* This is the first entrypoint in the driver called by the DRI driver loader
* after dlopen()ing it.
*
* It's used to create global state for the driver across contexts on the same
* Display.
*/
static __DRIscreen *
driCreateNewScreen2(int scrn, int fd,
const __DRIextension **extensions,
const __DRIextension **driver_extensions,
const __DRIconfig ***driver_configs, void *data)
{
static const __DRIextension *emptyExtensionList[] = { NULL };
__DRIscreen *psp;
psp = calloc(1, sizeof(*psp));
if (!psp)
return NULL;
/* By default, use the global driDriverAPI symbol (non-megadrivers). */
psp->driver = globalDriverAPI;
/* If the driver exposes its vtable through its extensions list
* (megadrivers), use that instead.
*/
if (driver_extensions) {
for (int i = 0; driver_extensions[i]; i++) {
if (strcmp(driver_extensions[i]->name, __DRI_DRIVER_VTABLE) == 0) {
psp->driver =
((__DRIDriverVtableExtension *)driver_extensions[i])->vtable;
}
}
}
setupLoaderExtensions(psp, extensions);
#ifndef __NOT_HAVE_DRM_H
if (fd != -1) {
drmVersionPtr version = drmGetVersion(fd);
if (version) {
psp->drm_version.major = version->version_major;
psp->drm_version.minor = version->version_minor;
psp->drm_version.patch = version->version_patchlevel;
drmFreeVersion(version);
}
}
#endif
psp->loaderPrivate = data;
psp->extensions = emptyExtensionList;
psp->fd = fd;
psp->myNum = scrn;
*driver_configs = psp->driver->InitScreen(psp);
if (*driver_configs == NULL) {
free(psp);
return NULL;
}
int gl_version_override = _mesa_get_gl_version_override();
if (gl_version_override >= 31) {
psp->max_gl_core_version = MAX2(psp->max_gl_core_version,
gl_version_override);
} else {
psp->max_gl_compat_version = MAX2(psp->max_gl_compat_version,
gl_version_override);
}
psp->api_mask = (1 << __DRI_API_OPENGL);
if (psp->max_gl_core_version > 0)
psp->api_mask |= (1 << __DRI_API_OPENGL_CORE);
if (psp->max_gl_es1_version > 0)
psp->api_mask |= (1 << __DRI_API_GLES);
if (psp->max_gl_es2_version > 0)
psp->api_mask |= (1 << __DRI_API_GLES2);
if (psp->max_gl_es2_version >= 30)
psp->api_mask |= (1 << __DRI_API_GLES3);
driParseOptionInfo(&psp->optionInfo, __dri2ConfigOptions);
driParseConfigFiles(&psp->optionCache, &psp->optionInfo, psp->myNum, "dri2");
return psp;
}
bool
intelInitContext(struct intel_context *intel,
int api,
const struct gl_config * mesaVis,
__DRIcontext * driContextPriv,
void *sharedContextPrivate,
struct dd_function_table *functions)
{
struct gl_context *ctx = &intel->ctx;
struct gl_context *shareCtx = (struct gl_context *) sharedContextPrivate;
__DRIscreen *sPriv = driContextPriv->driScreenPriv;
struct intel_screen *intelScreen = sPriv->driverPrivate;
int bo_reuse_mode;
struct gl_config visual;
/* we can't do anything without a connection to the device */
if (intelScreen->bufmgr == NULL)
return false;
/* Can't rely on invalidate events, fall back to glViewport hack */
if (!driContextPriv->driScreenPriv->dri2.useInvalidate) {
intel->saved_viewport = functions->Viewport;
functions->Viewport = intel_viewport;
}
if (mesaVis == NULL) {
memset(&visual, 0, sizeof visual);
mesaVis = &visual;
}
if (!_mesa_initialize_context(&intel->ctx, api, mesaVis, shareCtx,
functions)) {
printf("%s: failed to init mesa context\n", __FUNCTION__);
return false;
}
driContextPriv->driverPrivate = intel;
intel->intelScreen = intelScreen;
intel->driContext = driContextPriv;
intel->driFd = sPriv->fd;
intel->gen = intelScreen->gen;
const int devID = intelScreen->deviceID;
if (IS_SNB_GT1(devID) || IS_IVB_GT1(devID) || IS_HSW_GT1(devID))
intel->gt = 1;
else if (IS_SNB_GT2(devID) || IS_IVB_GT2(devID) || IS_HSW_GT2(devID))
intel->gt = 2;
else
intel->gt = 0;
if (IS_HASWELL(devID)) {
intel->is_haswell = true;
} else if (IS_G4X(devID)) {
intel->is_g4x = true;
} else if (IS_945(devID)) {
intel->is_945 = true;
}
if (intel->gen >= 5) {
intel->needs_ff_sync = true;
}
intel->has_separate_stencil = intel->intelScreen->hw_has_separate_stencil;
intel->must_use_separate_stencil = intel->intelScreen->hw_must_use_separate_stencil;
intel->has_hiz = intel->gen >= 6 && !intel->is_haswell;
intel->has_llc = intel->intelScreen->hw_has_llc;
intel->has_swizzling = intel->intelScreen->hw_has_swizzling;
memset(&ctx->TextureFormatSupported,
0, sizeof(ctx->TextureFormatSupported));
driParseConfigFiles(&intel->optionCache, &intelScreen->optionCache,
sPriv->myNum, (intel->gen >= 4) ? "i965" : "i915");
if (intel->gen < 4)
intel->maxBatchSize = 4096;
else
intel->maxBatchSize = sizeof(intel->batch.map);
intel->bufmgr = intelScreen->bufmgr;
bo_reuse_mode = driQueryOptioni(&intel->optionCache, "bo_reuse");
switch (bo_reuse_mode) {
case DRI_CONF_BO_REUSE_DISABLED:
break;
case DRI_CONF_BO_REUSE_ALL:
intel_bufmgr_gem_enable_reuse(intel->bufmgr);
break;
}
ctx->Const.MinLineWidth = 1.0;
ctx->Const.MinLineWidthAA = 1.0;
ctx->Const.MaxLineWidth = 5.0;
ctx->Const.MaxLineWidthAA = 5.0;
ctx->Const.LineWidthGranularity = 0.5;
ctx->Const.MinPointSize = 1.0;
ctx->Const.MinPointSizeAA = 1.0;
ctx->Const.MaxPointSize = 255.0;
ctx->Const.MaxPointSizeAA = 3.0;
ctx->Const.PointSizeGranularity = 1.0;
ctx->Const.MaxSamples = 1.0;
if (intel->gen >= 6)
ctx->Const.MaxClipPlanes = 8;
ctx->Const.StripTextureBorder = GL_TRUE;
/* reinitialize the context point state.
* It depend on constants in __struct gl_contextRec::Const
*/
_mesa_init_point(ctx);
if (intel->gen >= 4) {
ctx->Const.MaxRenderbufferSize = 8192;
} else {
ctx->Const.MaxRenderbufferSize = 2048;
}
/* Initialize the software rasterizer and helper modules.
*
* As of GL 3.1 core, the gen4+ driver doesn't need the swrast context for
* software fallbacks (which we have to support on legacy GL to do weird
* glDrawPixels(), glBitmap(), and other functions).
*/
if (intel->gen <= 3 || api != API_OPENGL_CORE) {
_swrast_CreateContext(ctx);
}
_vbo_CreateContext(ctx);
if (ctx->swrast_context) {
_tnl_CreateContext(ctx);
_swsetup_CreateContext(ctx);
/* Configure swrast to match hardware characteristics: */
_swrast_allow_pixel_fog(ctx, false);
_swrast_allow_vertex_fog(ctx, true);
}
_mesa_meta_init(ctx);
intel->hw_stencil = mesaVis->stencilBits && mesaVis->depthBits == 24;
intel->hw_stipple = 1;
/* XXX FBO: this doesn't seem to be used anywhere */
switch (mesaVis->depthBits) {
case 0: /* what to do in this case? */
case 16:
intel->polygon_offset_scale = 1.0;
break;
case 24:
intel->polygon_offset_scale = 2.0; /* req'd to pass glean */
break;
default:
assert(0);
break;
}
if (intel->gen >= 4)
intel->polygon_offset_scale /= 0xffff;
intel->RenderIndex = ~0;
intelInitExtensions(ctx);
INTEL_DEBUG = driParseDebugString(getenv("INTEL_DEBUG"), debug_control);
if (INTEL_DEBUG & DEBUG_BUFMGR)
dri_bufmgr_set_debug(intel->bufmgr, true);
if ((INTEL_DEBUG & DEBUG_SHADER_TIME) && intel->gen < 7) {
fprintf(stderr,
"shader_time debugging requires gen7 (Ivybridge) or better.\n");
INTEL_DEBUG &= ~DEBUG_SHADER_TIME;
}
if (INTEL_DEBUG & DEBUG_AUB)
drm_intel_bufmgr_gem_set_aub_dump(intel->bufmgr, true);
intel_batchbuffer_init(intel);
intel_fbo_init(intel);
intel->use_texture_tiling = driQueryOptionb(&intel->optionCache,
"texture_tiling");
intel->use_early_z = driQueryOptionb(&intel->optionCache, "early_z");
if (!driQueryOptionb(&intel->optionCache, "hiz")) {
intel->has_hiz = false;
/* On gen6, you can only do separate stencil with HIZ. */
if (intel->gen == 6)
intel->has_separate_stencil = false;
}
intel->prim.primitive = ~0;
/* Force all software fallbacks */
#ifdef I915
if (driQueryOptionb(&intel->optionCache, "no_rast")) {
fprintf(stderr, "disabling 3D rasterization\n");
intel->no_rast = 1;
}
#endif
if (driQueryOptionb(&intel->optionCache, "always_flush_batch")) {
fprintf(stderr, "flushing batchbuffer before/after each draw call\n");
intel->always_flush_batch = 1;
}
if (driQueryOptionb(&intel->optionCache, "always_flush_cache")) {
fprintf(stderr, "flushing GPU caches before/after each draw call\n");
intel->always_flush_cache = 1;
}
return true;
}
/* Create the device specific context.
*/
GLboolean
r100CreateContext( gl_api api,
const struct gl_config *glVisual,
__DRIcontext *driContextPriv,
const struct __DriverContextConfig *ctx_config,
unsigned *error,
void *sharedContextPrivate)
{
__DRIscreen *sPriv = driContextPriv->driScreenPriv;
radeonScreenPtr screen = (radeonScreenPtr)(sPriv->driverPrivate);
struct dd_function_table functions;
r100ContextPtr rmesa;
struct gl_context *ctx;
int i;
int tcl_mode, fthrottle_mode;
if (ctx_config->flags & ~(__DRI_CTX_FLAG_DEBUG | __DRI_CTX_FLAG_NO_ERROR)) {
*error = __DRI_CTX_ERROR_UNKNOWN_FLAG;
return false;
}
if (ctx_config->attribute_mask) {
*error = __DRI_CTX_ERROR_UNKNOWN_ATTRIBUTE;
return false;
}
assert(driContextPriv);
assert(screen);
/* Allocate the Radeon context */
rmesa = calloc(1, sizeof(*rmesa));
if ( !rmesa ) {
*error = __DRI_CTX_ERROR_NO_MEMORY;
return GL_FALSE;
}
rmesa->radeon.radeonScreen = screen;
r100_init_vtbl(&rmesa->radeon);
/* init exp fog table data */
radeonInitStaticFogData();
/* Parse configuration files.
* Do this here so that initialMaxAnisotropy is set before we create
* the default textures.
*/
driParseConfigFiles (&rmesa->radeon.optionCache, &screen->optionCache,
screen->driScreen->myNum, "radeon", NULL);
rmesa->radeon.initialMaxAnisotropy = driQueryOptionf(&rmesa->radeon.optionCache,
"def_max_anisotropy");
if (driQueryOptionb(&rmesa->radeon.optionCache, "hyperz"))
rmesa->using_hyperz = GL_TRUE;
/* Init default driver functions then plug in our Radeon-specific functions
* (the texture functions are especially important)
*/
_mesa_init_driver_functions( &functions );
_tnl_init_driver_draw_function( &functions );
radeonInitTextureFuncs( &rmesa->radeon, &functions );
radeonInitQueryObjFunctions(&functions);
if (!radeonInitContext(&rmesa->radeon, api, &functions,
glVisual, driContextPriv,
sharedContextPrivate)) {
free(rmesa);
*error = __DRI_CTX_ERROR_NO_MEMORY;
return GL_FALSE;
}
rmesa->radeon.swtcl.RenderIndex = ~0;
rmesa->radeon.hw.all_dirty = GL_TRUE;
ctx = &rmesa->radeon.glCtx;
driContextSetFlags(ctx, ctx_config->flags);
/* Initialize the software rasterizer and helper modules.
*/
_swrast_CreateContext( ctx );
_vbo_CreateContext( ctx );
_tnl_CreateContext( ctx );
_swsetup_CreateContext( ctx );
ctx->Const.MaxTextureUnits = driQueryOptioni (&rmesa->radeon.optionCache,
"texture_units");
ctx->Const.Program[MESA_SHADER_FRAGMENT].MaxTextureImageUnits = ctx->Const.MaxTextureUnits;
ctx->Const.MaxTextureCoordUnits = ctx->Const.MaxTextureUnits;
ctx->Const.MaxCombinedTextureImageUnits = ctx->Const.MaxTextureUnits;
ctx->Const.StripTextureBorder = GL_TRUE;
/* FIXME: When no memory manager is available we should set this
* to some reasonable value based on texture memory pool size */
ctx->Const.MaxTextureLevels = 12;
ctx->Const.Max3DTextureLevels = 9;
ctx->Const.MaxCubeTextureLevels = 12;
ctx->Const.MaxTextureRectSize = 2048;
ctx->Const.MaxTextureMaxAnisotropy = 16.0;
/* No wide points.
*/
ctx->Const.MinPointSize = 1.0;
ctx->Const.MinPointSizeAA = 1.0;
ctx->Const.MaxPointSize = 1.0;
ctx->Const.MaxPointSizeAA = 1.0;
ctx->Const.MinLineWidth = 1.0;
ctx->Const.MinLineWidthAA = 1.0;
ctx->Const.MaxLineWidth = 10.0;
ctx->Const.MaxLineWidthAA = 10.0;
ctx->Const.LineWidthGranularity = 0.0625;
/* Set maxlocksize (and hence vb size) small enough to avoid
* fallbacks in radeon_tcl.c. ie. guarentee that all vertices can
* fit in a single dma buffer for indexed rendering of quad strips,
* etc.
*/
ctx->Const.MaxArrayLockSize =
MIN2( ctx->Const.MaxArrayLockSize,
RADEON_BUFFER_SIZE / RADEON_MAX_TCL_VERTSIZE );
rmesa->boxes = 0;
ctx->Const.MaxDrawBuffers = 1;
ctx->Const.MaxColorAttachments = 1;
ctx->Const.MaxRenderbufferSize = 2048;
ctx->Const.ShaderCompilerOptions[MESA_SHADER_VERTEX].OptimizeForAOS = true;
/* Install the customized pipeline:
*/
_tnl_destroy_pipeline( ctx );
_tnl_install_pipeline( ctx, radeon_pipeline );
/* Try and keep materials and vertices separate:
*/
/* _tnl_isolate_materials( ctx, GL_TRUE ); */
/* Configure swrast and T&L to match hardware characteristics:
*/
_swrast_allow_pixel_fog( ctx, GL_FALSE );
_swrast_allow_vertex_fog( ctx, GL_TRUE );
_tnl_allow_pixel_fog( ctx, GL_FALSE );
_tnl_allow_vertex_fog( ctx, GL_TRUE );
for ( i = 0 ; i < RADEON_MAX_TEXTURE_UNITS ; i++ ) {
_math_matrix_ctr( &rmesa->TexGenMatrix[i] );
_math_matrix_ctr( &rmesa->tmpmat[i] );
_math_matrix_set_identity( &rmesa->TexGenMatrix[i] );
_math_matrix_set_identity( &rmesa->tmpmat[i] );
}
ctx->Extensions.ARB_occlusion_query = true;
ctx->Extensions.ARB_texture_border_clamp = true;
ctx->Extensions.ARB_texture_cube_map = true;
ctx->Extensions.ARB_texture_env_combine = true;
ctx->Extensions.ARB_texture_env_crossbar = true;
ctx->Extensions.ARB_texture_env_dot3 = true;
ctx->Extensions.ARB_texture_filter_anisotropic = true;
ctx->Extensions.ARB_texture_mirror_clamp_to_edge = true;
ctx->Extensions.ATI_texture_env_combine3 = true;
ctx->Extensions.ATI_texture_mirror_once = true;
ctx->Extensions.EXT_texture_env_dot3 = true;
ctx->Extensions.EXT_texture_filter_anisotropic = true;
ctx->Extensions.EXT_texture_mirror_clamp = true;
ctx->Extensions.MESA_ycbcr_texture = true;
ctx->Extensions.NV_texture_rectangle = true;
ctx->Extensions.OES_EGL_image = true;
ctx->Extensions.EXT_texture_compression_s3tc = true;
ctx->Extensions.ANGLE_texture_compression_dxt = true;
/* XXX these should really go right after _mesa_init_driver_functions() */
radeon_fbo_init(&rmesa->radeon);
radeonInitSpanFuncs( ctx );
radeonInitIoctlFuncs( ctx );
radeonInitStateFuncs( ctx );
radeonInitState( rmesa );
radeonInitSwtcl( ctx );
_mesa_vector4f_alloc( &rmesa->tcl.ObjClean, 0,
ctx->Const.MaxArrayLockSize, 32 );
fthrottle_mode = driQueryOptioni(&rmesa->radeon.optionCache, "fthrottle_mode");
rmesa->radeon.iw.irq_seq = -1;
rmesa->radeon.irqsEmitted = 0;
rmesa->radeon.do_irqs = (rmesa->radeon.radeonScreen->irq != 0 &&
fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS);
rmesa->radeon.do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
tcl_mode = driQueryOptioni(&rmesa->radeon.optionCache, "tcl_mode");
if (getenv("RADEON_NO_RAST")) {
fprintf(stderr, "disabling 3D acceleration\n");
FALLBACK(rmesa, RADEON_FALLBACK_DISABLE, 1);
} else if (tcl_mode == DRI_CONF_TCL_SW ||
!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
rmesa->radeon.radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL;
fprintf(stderr, "Disabling HW TCL support\n");
}
TCL_FALLBACK(&rmesa->radeon.glCtx, RADEON_TCL_FALLBACK_TCL_DISABLE, 1);
}
if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
/* _tnl_need_dlist_norm_lengths( ctx, GL_FALSE ); */
}
_mesa_override_extensions(ctx);
_mesa_compute_version(ctx);
/* Exec table initialization requires the version to be computed */
_mesa_initialize_dispatch_tables(ctx);
_mesa_initialize_vbo_vtxfmt(ctx);
*error = __DRI_CTX_ERROR_SUCCESS;
return GL_TRUE;
}
/* Create the device specific context.
*/
GLboolean r128CreateContext( const __GLcontextModes *glVisual,
__DRIcontextPrivate *driContextPriv,
void *sharedContextPrivate )
{
GLcontext *ctx, *shareCtx;
__DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
struct dd_function_table functions;
r128ContextPtr rmesa;
r128ScreenPtr r128scrn;
int i;
/* Allocate the r128 context */
rmesa = (r128ContextPtr) CALLOC( sizeof(*rmesa) );
if ( !rmesa )
return GL_FALSE;
/* Init default driver functions then plug in our Radeon-specific functions
* (the texture functions are especially important)
*/
_mesa_init_driver_functions( &functions );
r128InitDriverFuncs( &functions );
r128InitIoctlFuncs( &functions );
r128InitTextureFuncs( &functions );
/* Allocate the Mesa context */
if (sharedContextPrivate)
shareCtx = ((r128ContextPtr) sharedContextPrivate)->glCtx;
else
shareCtx = NULL;
rmesa->glCtx = _mesa_create_context(glVisual, shareCtx,
&functions, (void *) rmesa);
if (!rmesa->glCtx) {
FREE(rmesa);
return GL_FALSE;
}
driContextPriv->driverPrivate = rmesa;
ctx = rmesa->glCtx;
rmesa->driContext = driContextPriv;
rmesa->driScreen = sPriv;
rmesa->driDrawable = NULL;
rmesa->hHWContext = driContextPriv->hHWContext;
rmesa->driHwLock = &sPriv->pSAREA->lock;
rmesa->driFd = sPriv->fd;
r128scrn = rmesa->r128Screen = (r128ScreenPtr)(sPriv->private);
/* Parse configuration files */
driParseConfigFiles (&rmesa->optionCache, &r128scrn->optionCache,
r128scrn->driScreen->myNum, "r128");
rmesa->sarea = (drm_r128_sarea_t *)((char *)sPriv->pSAREA +
r128scrn->sarea_priv_offset);
rmesa->CurrentTexObj[0] = NULL;
rmesa->CurrentTexObj[1] = NULL;
(void) memset( rmesa->texture_heaps, 0, sizeof( rmesa->texture_heaps ) );
make_empty_list( & rmesa->swapped );
rmesa->nr_heaps = r128scrn->numTexHeaps;
for ( i = 0 ; i < rmesa->nr_heaps ; i++ ) {
rmesa->texture_heaps[i] = driCreateTextureHeap( i, rmesa,
r128scrn->texSize[i],
12,
R128_NR_TEX_REGIONS,
(drmTextureRegionPtr)rmesa->sarea->tex_list[i],
&rmesa->sarea->tex_age[i],
&rmesa->swapped,
sizeof( r128TexObj ),
(destroy_texture_object_t *) r128DestroyTexObj );
driSetTextureSwapCounterLocation( rmesa->texture_heaps[i],
& rmesa->c_textureSwaps );
}
rmesa->texture_depth = driQueryOptioni (&rmesa->optionCache,
"texture_depth");
if (rmesa->texture_depth == DRI_CONF_TEXTURE_DEPTH_FB)
rmesa->texture_depth = ( r128scrn->cpp == 4 ) ?
DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16;
rmesa->RenderIndex = -1; /* Impossible value */
rmesa->vert_buf = NULL;
rmesa->num_verts = 0;
RENDERINPUTS_ONES( rmesa->tnl_state_bitset );
/* Set the maximum texture size small enough that we can guarentee that
* all texture units can bind a maximal texture and have them both in
* texturable memory at once.
*/
ctx->Const.MaxTextureUnits = 2;
ctx->Const.MaxTextureImageUnits = 2;
ctx->Const.MaxTextureCoordUnits = 2;
driCalculateMaxTextureLevels( rmesa->texture_heaps,
rmesa->nr_heaps,
& ctx->Const,
4,
10, /* max 2D texture size is 1024x1024 */
0, /* 3D textures unsupported. */
0, /* cube textures unsupported. */
0, /* texture rectangles unsupported. */
11,
GL_FALSE,
0 );
/* No wide points.
*/
ctx->Const.MinPointSize = 1.0;
ctx->Const.MinPointSizeAA = 1.0;
ctx->Const.MaxPointSize = 1.0;
ctx->Const.MaxPointSizeAA = 1.0;
/* No wide lines.
*/
ctx->Const.MinLineWidth = 1.0;
ctx->Const.MinLineWidthAA = 1.0;
ctx->Const.MaxLineWidth = 1.0;
ctx->Const.MaxLineWidthAA = 1.0;
ctx->Const.LineWidthGranularity = 1.0;
ctx->Const.MaxDrawBuffers = 1;
#if ENABLE_PERF_BOXES
rmesa->boxes = driQueryOptionb(&rmesa->optionCache, "performance_boxes");
#endif
/* Initialize the software rasterizer and helper modules.
*/
_swrast_CreateContext( ctx );
_vbo_CreateContext( ctx );
_tnl_CreateContext( ctx );
_swsetup_CreateContext( ctx );
/* Install the customized pipeline:
*/
/* _tnl_destroy_pipeline( ctx ); */
/* _tnl_install_pipeline( ctx, r128_pipeline ); */
/* Configure swrast and T&L to match hardware characteristics:
*/
_swrast_allow_pixel_fog( ctx, GL_FALSE );
_swrast_allow_vertex_fog( ctx, GL_TRUE );
_tnl_allow_pixel_fog( ctx, GL_FALSE );
_tnl_allow_vertex_fog( ctx, GL_TRUE );
driInitExtensions( ctx, card_extensions, GL_TRUE );
if (sPriv->drm_version.minor >= 4)
_mesa_enable_extension( ctx, "GL_MESA_ycbcr_texture" );
r128InitTriFuncs( ctx );
r128DDInitStateFuncs( ctx );
r128DDInitSpanFuncs( ctx );
r128DDInitState( rmesa );
driContextPriv->driverPrivate = (void *)rmesa;
#if DO_DEBUG
R128_DEBUG = driParseDebugString( getenv( "R128_DEBUG" ),
debug_control );
#endif
if (driQueryOptionb(&rmesa->optionCache, "no_rast")) {
fprintf(stderr, "disabling 3D acceleration\n");
FALLBACK(rmesa, R128_FALLBACK_DISABLE, 1);
}
return GL_TRUE;
}
/* Create the device specific rendering context.
*/
GLboolean r200CreateContext( gl_api api,
const struct gl_config *glVisual,
__DRIcontext *driContextPriv,
unsigned major_version,
unsigned minor_version,
uint32_t flags,
unsigned *error,
void *sharedContextPrivate)
{
__DRIscreen *sPriv = driContextPriv->driScreenPriv;
radeonScreenPtr screen = (radeonScreenPtr)(sPriv->driverPrivate);
struct dd_function_table functions;
r200ContextPtr rmesa;
struct gl_context *ctx;
int i;
int tcl_mode;
/* API and flag filtering is handled in dri2CreateContextAttribs.
*/
(void) api;
(void) flags;
assert(glVisual);
assert(driContextPriv);
assert(screen);
/* Allocate the R200 context */
rmesa = (r200ContextPtr) CALLOC( sizeof(*rmesa) );
if ( !rmesa ) {
*error = __DRI_CTX_ERROR_NO_MEMORY;
return GL_FALSE;
}
rmesa->radeon.radeonScreen = screen;
r200_init_vtbl(&rmesa->radeon);
/* init exp fog table data */
radeonInitStaticFogData();
/* Parse configuration files.
* Do this here so that initialMaxAnisotropy is set before we create
* the default textures.
*/
driParseConfigFiles (&rmesa->radeon.optionCache, &screen->optionCache,
screen->driScreen->myNum, "r200");
rmesa->radeon.initialMaxAnisotropy = driQueryOptionf(&rmesa->radeon.optionCache,
"def_max_anisotropy");
if ( sPriv->drm_version.major == 1
&& driQueryOptionb( &rmesa->radeon.optionCache, "hyperz" ) ) {
if ( sPriv->drm_version.minor < 13 )
fprintf( stderr, "DRM version 1.%d too old to support HyperZ, "
"disabling.\n", sPriv->drm_version.minor );
else
rmesa->using_hyperz = GL_TRUE;
}
if ( sPriv->drm_version.minor >= 15 )
rmesa->texmicrotile = GL_TRUE;
/* Init default driver functions then plug in our R200-specific functions
* (the texture functions are especially important)
*/
_mesa_init_driver_functions(&functions);
r200InitDriverFuncs(&functions);
r200InitIoctlFuncs(&functions);
r200InitStateFuncs(&rmesa->radeon, &functions);
r200InitTextureFuncs(&rmesa->radeon, &functions);
r200InitShaderFuncs(&functions);
radeonInitQueryObjFunctions(&functions);
if (!radeonInitContext(&rmesa->radeon, &functions,
glVisual, driContextPriv,
sharedContextPrivate)) {
FREE(rmesa);
*error = __DRI_CTX_ERROR_NO_MEMORY;
return GL_FALSE;
}
rmesa->radeon.swtcl.RenderIndex = ~0;
rmesa->radeon.hw.all_dirty = 1;
/* Set the maximum texture size small enough that we can guarentee that
* all texture units can bind a maximal texture and have all of them in
* texturable memory at once. Depending on the allow_large_textures driconf
* setting allow larger textures.
*/
ctx = rmesa->radeon.glCtx;
ctx->Const.MaxTextureUnits = driQueryOptioni (&rmesa->radeon.optionCache,
"texture_units");
ctx->Const.MaxTextureImageUnits = ctx->Const.MaxTextureUnits;
ctx->Const.MaxTextureCoordUnits = ctx->Const.MaxTextureUnits;
ctx->Const.MaxCombinedTextureImageUnits = ctx->Const.MaxTextureUnits;
ctx->Const.StripTextureBorder = GL_TRUE;
i = driQueryOptioni( &rmesa->radeon.optionCache, "allow_large_textures");
/* FIXME: When no memory manager is available we should set this
* to some reasonable value based on texture memory pool size */
ctx->Const.MaxTextureLevels = 12;
ctx->Const.Max3DTextureLevels = 9;
ctx->Const.MaxCubeTextureLevels = 12;
ctx->Const.MaxTextureRectSize = 2048;
ctx->Const.MaxRenderbufferSize = 2048;
ctx->Const.MaxTextureMaxAnisotropy = 16.0;
/* No wide AA points.
*/
ctx->Const.MinPointSize = 1.0;
ctx->Const.MinPointSizeAA = 1.0;
ctx->Const.MaxPointSizeAA = 1.0;
ctx->Const.PointSizeGranularity = 0.0625;
ctx->Const.MaxPointSize = 2047.0;
/* mesa initialization problem - _mesa_init_point was already called */
ctx->Point.MaxSize = ctx->Const.MaxPointSize;
ctx->Const.MinLineWidth = 1.0;
ctx->Const.MinLineWidthAA = 1.0;
ctx->Const.MaxLineWidth = 10.0;
ctx->Const.MaxLineWidthAA = 10.0;
ctx->Const.LineWidthGranularity = 0.0625;
ctx->Const.VertexProgram.MaxNativeInstructions = R200_VSF_MAX_INST;
ctx->Const.VertexProgram.MaxNativeAttribs = 12;
ctx->Const.VertexProgram.MaxNativeTemps = R200_VSF_MAX_TEMPS;
ctx->Const.VertexProgram.MaxNativeParameters = R200_VSF_MAX_PARAM;
ctx->Const.VertexProgram.MaxNativeAddressRegs = 1;
ctx->Const.MaxDrawBuffers = 1;
ctx->Const.MaxColorAttachments = 1;
_mesa_set_mvp_with_dp4( ctx, GL_TRUE );
/* Initialize the software rasterizer and helper modules.
*/
_swrast_CreateContext( ctx );
_vbo_CreateContext( ctx );
_tnl_CreateContext( ctx );
_swsetup_CreateContext( ctx );
_ae_create_context( ctx );
/* Install the customized pipeline:
*/
_tnl_destroy_pipeline( ctx );
_tnl_install_pipeline( ctx, r200_pipeline );
/* Try and keep materials and vertices separate:
*/
/* _tnl_isolate_materials( ctx, GL_TRUE ); */
/* Configure swrast and TNL to match hardware characteristics:
*/
_swrast_allow_pixel_fog( ctx, GL_FALSE );
_swrast_allow_vertex_fog( ctx, GL_TRUE );
_tnl_allow_pixel_fog( ctx, GL_FALSE );
_tnl_allow_vertex_fog( ctx, GL_TRUE );
for ( i = 0 ; i < R200_MAX_TEXTURE_UNITS ; i++ ) {
_math_matrix_ctr( &rmesa->TexGenMatrix[i] );
_math_matrix_set_identity( &rmesa->TexGenMatrix[i] );
}
_math_matrix_ctr( &rmesa->tmpmat );
_math_matrix_set_identity( &rmesa->tmpmat );
ctx->Extensions.ARB_half_float_pixel = true;
ctx->Extensions.ARB_occlusion_query = true;
ctx->Extensions.ARB_texture_border_clamp = true;
ctx->Extensions.ARB_texture_env_combine = true;
ctx->Extensions.ARB_texture_env_dot3 = true;
ctx->Extensions.ARB_texture_env_crossbar = true;
ctx->Extensions.ARB_vertex_array_object = true;
ctx->Extensions.EXT_blend_color = true;
ctx->Extensions.EXT_blend_minmax = true;
ctx->Extensions.EXT_fog_coord = true;
ctx->Extensions.EXT_packed_depth_stencil = true;
ctx->Extensions.EXT_secondary_color = true;
ctx->Extensions.EXT_texture_env_dot3 = true;
ctx->Extensions.EXT_texture_filter_anisotropic = true;
ctx->Extensions.EXT_texture_mirror_clamp = true;
ctx->Extensions.APPLE_vertex_array_object = true;
ctx->Extensions.ATI_texture_env_combine3 = true;
ctx->Extensions.ATI_texture_mirror_once = true;
ctx->Extensions.MESA_pack_invert = true;
ctx->Extensions.NV_blend_square = true;
ctx->Extensions.NV_texture_rectangle = true;
#if FEATURE_OES_EGL_image
ctx->Extensions.OES_EGL_image = true;
#endif
ctx->Extensions.EXT_framebuffer_object = true;
ctx->Extensions.ARB_occlusion_query = true;
if (!(rmesa->radeon.radeonScreen->chip_flags & R200_CHIPSET_YCBCR_BROKEN)) {
/* yuv textures don't work with some chips - R200 / rv280 okay so far
others get the bit ordering right but don't actually do YUV-RGB conversion */
ctx->Extensions.MESA_ycbcr_texture = true;
}
if (rmesa->radeon.glCtx->Mesa_DXTn) {
ctx->Extensions.EXT_texture_compression_s3tc = true;
ctx->Extensions.S3_s3tc = true;
}
else if (driQueryOptionb (&rmesa->radeon.optionCache, "force_s3tc_enable")) {
ctx->Extensions.EXT_texture_compression_s3tc = true;
}
ctx->Extensions.ARB_texture_cube_map = true;
ctx->Extensions.EXT_blend_equation_separate = true;
ctx->Extensions.EXT_blend_func_separate = true;
ctx->Extensions.ARB_vertex_program = true;
ctx->Extensions.EXT_gpu_program_parameters = true;
ctx->Extensions.NV_vertex_program =
driQueryOptionb(&rmesa->radeon.optionCache, "nv_vertex_program");
ctx->Extensions.ATI_fragment_shader = (ctx->Const.MaxTextureUnits == 6);
ctx->Extensions.ARB_point_sprite = true;
ctx->Extensions.EXT_point_parameters = true;
#if 0
r200InitDriverFuncs( ctx );
r200InitIoctlFuncs( ctx );
r200InitStateFuncs( ctx );
r200InitTextureFuncs( ctx );
#endif
/* plug in a few more device driver functions */
/* XXX these should really go right after _mesa_init_driver_functions() */
radeon_fbo_init(&rmesa->radeon);
radeonInitSpanFuncs( ctx );
r200InitTnlFuncs( ctx );
r200InitState( rmesa );
r200InitSwtcl( ctx );
rmesa->prefer_gart_client_texturing =
(getenv("R200_GART_CLIENT_TEXTURES") != 0);
tcl_mode = driQueryOptioni(&rmesa->radeon.optionCache, "tcl_mode");
if (driQueryOptionb(&rmesa->radeon.optionCache, "no_rast")) {
fprintf(stderr, "disabling 3D acceleration\n");
FALLBACK(rmesa, R200_FALLBACK_DISABLE, 1);
}
else if (tcl_mode == DRI_CONF_TCL_SW || getenv("R200_NO_TCL") ||
!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
rmesa->radeon.radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL;
fprintf(stderr, "Disabling HW TCL support\n");
}
TCL_FALLBACK(rmesa->radeon.glCtx, R200_TCL_FALLBACK_TCL_DISABLE, 1);
}
_mesa_compute_version(ctx);
if (ctx->Version < major_version * 10 + minor_version) {
r200DestroyContext(driContextPriv);
*error = __DRI_CTX_ERROR_BAD_VERSION;
return GL_FALSE;
}
*error = __DRI_CTX_ERROR_SUCCESS;
return GL_TRUE;
}
