static int dsi_mipi_430_cm_480_854_panel_enable(struct omap_dss_device *dssdev)
{
struct mapphone_data *map_data = (struct mapphone_data *) dssdev->data;
u8 data[7];
int ret;
DBG("dsi_mipi_430_cm_480_854_panel_enable() \n");
/* Exit sleep mode */
data[0] = EDISCO_CMD_EXIT_SLEEP_MODE;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 1);
/* 120ms delay for internal block stabilization */
msleep(120);
/* turn off mcs register acces protection */
data[0] = EDISCO_CMD_SET_MCS;
data[1] = 0x00;
ret = dsi_vc_write(EDISCO_CMD_VC, EDISCO_SHORT_WRITE_1, data, 2);
/* Enable 2 data lanes */
data[0] = EDISCO_CMD_DATA_LANE_CONFIG;
data[1] = EDISCO_CMD_DATA_LANE_TWO;
ret = dsi_vc_write(EDISCO_CMD_VC, EDISCO_SHORT_WRITE_1, data, 2);
msleep(10);
/* Set dynamic backlight control and PWM; D[7:4] = PWM_DIV[3:0];*/
/* D[3]=0 (PWM OFF);
* D[2]=0 (auto BL control OFF);
* D[1]=0 (Grama correction On);
* D[0]=0 (Enhanced Image Correction OFF) */
data[0] = 0xb4;
data[1] = 0x0f;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 2);
/* set page, column address */
data[0] = EDISCO_CMD_SET_COLUMN_ADDRESS;
data[1] = 0x00;
data[2] = 0x00;
data[3] = (dssdev->panel.timings.x_res - 1) >> 8;
data[4] = (dssdev->panel.timings.x_res - 1) & 0xff;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 5);
if (ret)
goto error;
data[0] = EDISCO_CMD_SET_PAGE_ADDRESS;
data[1] = 0x00;
data[2] = 0x00;
data[3] = (dssdev->panel.timings.y_res - 1) >> 8;
data[4] = (dssdev->panel.timings.y_res - 1) & 0xff;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 5);
if (ret)
goto error;
mdelay(200);
if (atomic_cmpxchg(&map_data->state, PANEL_OFF, PANEL_ENABLED) ==
PANEL_OFF) {
DBG("panel enabled\n");
schedule_work(&map_data->work);
}
return 0;
error:
return -EINVAL;
}
static int sholes_panel_enable(struct omap_dss_device *dssdev)
{
u8 data[7];
int ret;
DBG("enable\n");
if (dssdev->platform_enable) {
ret = dssdev->platform_enable(dssdev);
if (ret)
return ret;
}
/* turn of mcs register acces protection */
data[0] = 0xb2;
data[1] = 0x00;
ret = dsi_vc_write(EDISCO_CMD_VC, EDISCO_SHORT_WRITE_1, data, 2);
/* enable lane setting and test registers*/
data[0] = 0xef;
data[1] = 0x01;
data[2] = 0x01;
ret = dsi_vc_write(EDISCO_CMD_VC, EDISCO_LONG_WRITE, data, 3);
/* 2nd param 61 = 1 line; 63 = 2 lanes */
data[0] = 0xef;
data[1] = 0x60;
data[2] = 0x63;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 3);
/* 2nd param 0 = WVGA; 1 = WQVGA */
data[0] = 0xb3;
data[1] = 0x00;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 2);
/* Set dynamic backlight control and PWM; D[7:4] = PWM_DIV[3:0];*/
/* D[3]=0 (PWM OFF);
* D[2]=0 (auto BL control OFF);
* D[1]=0 (Grama correction On);
* D[0]=0 (Enhanced Image Correction OFF) */
data[0] = 0xb4;
data[1] = 0x1f;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 2);
/* set page, column address */
data[0] = EDISCO_CMD_SET_PAGE_ADDRESS;
data[1] = 0x00;
data[2] = 0x00;
data[3] = (dssdev->panel.timings.y_res - 1) >> 8;
data[4] = (dssdev->panel.timings.y_res - 1) & 0xff;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 5);
if (ret)
goto error;
data[0] = EDISCO_CMD_SET_COLUMN_ADDRESS;
data[1] = 0x00;
data[2] = 0x00;
data[3] = (dssdev->panel.timings.x_res - 1) >> 8;
data[4] = (dssdev->panel.timings.x_res - 1) & 0xff;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 5);
if (ret)
goto error;
/* turn it on */
data[0] = EDISCO_CMD_EXIT_SLEEP_MODE;
//ret = dsi_vc_write(EDISCO_CMD_VC, EDISCO_SHORT_WRITE_0, data, 1);
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 1);
mdelay(200);
return 0;
error:
return -EINVAL;
}
static int dsi_mipi_cm_480_854_panel_enable(struct omap_dss_device *dssdev)
{
struct mapphone_data *map_data = (struct mapphone_data *) dssdev->data;
u8 data[7];
int ret;
DBG("dsi_mipi_cm_480_854_panel_enable() \n");
/* turn off mcs register acces protection */
data[0] = EDISCO_CMD_SET_MCS;
data[1] = 0x00;
ret = dsi_vc_write(EDISCO_CMD_VC, EDISCO_SHORT_WRITE_1, data, 2);
/* enable lane setting and test registers*/
data[0] = 0xef;
data[1] = 0x01;
data[2] = 0x01;
ret = dsi_vc_write(EDISCO_CMD_VC, EDISCO_LONG_WRITE, data, 3);
/* 2nd param 61 = 1 line; 63 = 2 lanes */
data[0] = 0xef;
data[1] = 0x60;
data[2] = 0x63;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 3);
/* 2nd param 0 = WVGA; 1 = WQVGA */
data[0] = 0xb3;
data[1] = 0x00;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 2);
/* Set dynamic backlight control and PWM; D[7:4] = PWM_DIV[3:0];*/
/* D[3]=0 (PWM OFF);
* D[2]=0 (auto BL control OFF);
* D[1]=0 (Grama correction On);
* D[0]=0 (Enhanced Image Correction OFF) */
data[0] = 0xb4;
data[1] = 0x1f;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 2);
/* set page, column address */
data[0] = EDISCO_CMD_SET_PAGE_ADDRESS;
data[1] = 0x00;
data[2] = 0x00;
data[3] = (dssdev->panel.timings.y_res - 1) >> 8;
data[4] = (dssdev->panel.timings.y_res - 1) & 0xff;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 5);
if (ret)
goto error;
data[0] = EDISCO_CMD_SET_COLUMN_ADDRESS;
data[1] = 0x00;
data[2] = 0x00;
data[3] = (dssdev->panel.timings.x_res - 1) >> 8;
data[4] = (dssdev->panel.timings.x_res - 1) & 0xff;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 5);
if (ret)
goto error;
data[0] = EDISCO_CMD_EXIT_SLEEP_MODE;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 1);
mdelay(200);
if (atomic_cmpxchg(&map_data->state, PANEL_OFF, PANEL_ENABLED) ==
PANEL_OFF) {
DBG("panel enabled\n");
schedule_work(&map_data->work);
}
printk(KERN_INFO "done EDISCO CTRL ENABLE\n");
return 0;
error:
return -EINVAL;
}
static int dsi_mipi_280_vm_320_240_panel_enable(struct omap_dss_device *dssdev)
{
u8 data[10];
int ret;
DBG(" dsi_mipi_280_vm_320_240_panel_enable() \n");
/* turn off mcs register acces protection */
data[0] = EDISCO_CMD_SET_MCS;
data[1] = 0x00;
ret = dsi_vc_write(EDISCO_CMD_VC, EDISCO_SHORT_WRITE_1, data, 2);
/* Internal display set up */
data[0] = 0xC0;
data[1] = 0x11;
data[2] = 0x04;
ret = dsi_vc_write(EDISCO_CMD_VC, EDISCO_LONG_WRITE, data, 3);
/* Internal voltage set up */
data[0] = 0xD3;
data[1] = 0x1F;
data[2] = 0x01;
data[3] = 0x02;
data[4] = 0x15;
ret = dsi_vc_write(EDISCO_CMD_VC, EDISCO_LONG_WRITE, data, 5);
/* Internal voltage set up */
data[0] = 0xD4;
data[1] = 0x62;
data[2] = 0x1E;
data[3] = 0x00;
data[4] = 0xB7;
ret = dsi_vc_write(EDISCO_CMD_VC, EDISCO_LONG_WRITE, data, 5);
/* Internal display set up */
data[0] = 0xC5;
data[1] = 0x01;
ret = dsi_vc_write(EDISCO_CMD_VC, EDISCO_SHORT_WRITE_1, data, 2);
/* Load optimized red gamma (+) settings*/
data[0] = 0xE9;
data[1] = 0x01;
data[2] = 0x0B;
data[3] = 0x05;
data[4] = 0x21;
data[5] = 0x05;
data[6] = 0x0D;
data[7] = 0x01;
data[8] = 0x0B;
data[9] = 0x04;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 10);
/* Load optimized red gamma (-) settings*/
data[0] = 0xEA;
data[1] = 0x04;
data[2] = 0x0B;
data[3] = 0x05;
data[4] = 0x21;
data[5] = 0x05;
data[6] = 0x0D;
data[7] = 0x01;
data[8] = 0x08;
data[9] = 0x04;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 10);
/* Load optimized green gamma (+) settings*/
data[0] = 0xEB;
data[1] = 0x02;
data[2] = 0x0B;
data[3] = 0x05;
data[4] = 0x21;
data[5] = 0x05;
data[6] = 0x0D;
data[7] = 0x01;
data[8] = 0x0B;
data[9] = 0x04;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 10);
/* Load optimized green gamma (-) settings*/
data[0] = 0xEC;
data[1] = 0x05;
data[2] = 0x0B;
data[3] = 0x05;
data[4] = 0x21;
data[5] = 0x05;
data[6] = 0x0D;
data[7] = 0x01;
data[8] = 0x08;
data[9] = 0x04;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 10);
/* Load optimized blue gamma (+) settings*/
data[0] = 0xED;
data[1] = 0x04;
data[2] = 0x0B;
data[3] = 0x05;
data[4] = 0x21;
data[5] = 0x05;
data[6] = 0x0D;
data[7] = 0x01;
data[8] = 0x0B;
data[9] = 0x04;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 10);
/* Load optimized blue gamma (-) settings*/
data[0] = 0xEE;
data[1] = 0x07;
data[2] = 0x0B;
data[3] = 0x05;
data[4] = 0x21;
data[5] = 0x05;
data[6] = 0x0D;
data[7] = 0x01;
data[8] = 0x08;
data[9] = 0x04;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 10);
/* turn on mcs register acces protection */
data[0] = EDISCO_CMD_SET_MCS;
data[1] = 0x03;
ret = dsi_vc_write(EDISCO_CMD_VC, EDISCO_SHORT_WRITE_1, data, 2);
/* turn it on */
data[0] = EDISCO_CMD_EXIT_SLEEP_MODE;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 1);
if (ret)
goto error;
mdelay(10);
data[0] = EDISCO_CMD_SET_DISPLAY_ON;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 1);
if (ret) {
printk(KERN_ERR "failed to send EDISCO_CMD_SET_DISPLAY_ON \n");
goto error;
}
printk(KERN_INFO "done EDISCO CTRL ENABLE\n");
return 0;
error:
return -EINVAL;
}
static int dsi_mipi_cm_480_854_panel_enable(struct omap_dss_device *dssdev)
{
u8 data[7];
int ret;
struct mapphone_data *map_data = (struct mapphone_data *) dssdev->data;
DBG("dsi_mipi_cm_480_854_panel_enable() \n");
/* Check if the display we are using is actually a TMD display */
if (dssdev->panel.panel_id == MOT_DISP_370_MIPI_480_854_CM) {
printk(KERN_INFO "te_scan_line is set = %d \n",
map_data->te_scan_line);
if (mapphone_panel_read_supplier_id() == SUPPLIER_ID_TMD) {
DBG("dsi_mipi_cm_480_854_panel_enable() - TMD panel\n");
dssdev->panel.panel_id = MOT_DISP_MIPI_480_854_CM;
map_data->te_scan_line = DISP_480_854_CM_TE_SCANLINE;
printk(KERN_INFO "Overwrite te_scan_line=%d\n",
map_data->te_scan_line);
}
}
/* turn off mcs register acces protection */
data[0] = EDISCO_CMD_SET_MCS;
data[1] = 0x00;
ret = mapphone_panel_lp_cmd_wrt_sync(false, EDISCO_SHORT_WRITE_1,
data, 2,
EDISCO_CMD_SET_MCS, 1,
EDISCO_CMD_MCS_OFF, 0x3);
if (ret)
printk(KERN_ERR "failed to send SET_MCS \n");
/* enable lane setting and test registers*/
data[0] = 0xef;
data[1] = 0x01;
data[2] = 0x01;
data[3] = 0x00;
ret = dsi_vc_write(EDISCO_CMD_VC, EDISCO_LONG_WRITE, data, 4);
/* 2nd param 61 = 1 line; 63 = 2 lanes */
data[0] = 0xef;
data[1] = 0x60;
data[2] = 0x63;
data[3] = 0x00;
if (dssdev->panel.panel_id == MOT_DISP_MIPI_480_854_CM)
/* Reading lane_config and it will return
* 0x63 or 2-lanes, 0x60 for 1-lane (1st source displ only)*/
ret = mapphone_panel_lp_cmd_wrt_sync(true, 0x00,
data, 4,
0xef, 1,
0x63, 0x63);
else
/* Reading lane_config and it will return
* 0x1 for 2-lanes, 0x0 for 1-lane (2nd source displ only)*/
ret = mapphone_panel_lp_cmd_wrt_sync(true, 0x00,
data, 4,
EDISCO_CMD_DATA_LANE_CONFIG, 1,
0x1, 0x1);
if (ret)
printk(KERN_ERR "failed to send LANE_CONFIG \n");
/* Forcing display inversion off for hardware issue
* on some phones (observed inverted color, ~1% of powerups fail)
*/
data[0] = EDISCO_CMD_SET_INVERSION_OFF;
ret = mapphone_panel_lp_cmd_wrt_sync(true, 0,
data, 1,
EDISCO_CMD_READ_DISPLAY_IMAGE_MODE, 1,
0x00, EDISCO_CMD_SET_INVERSION_OFF);
if (ret)
printk(KERN_ERR "failed to send EDISCO_CMD_SET_INVERSION_OFF \n");
/* 2nd param 0 = WVGA; 1 = WQVGA */
data[0] = EDISCO_CMD_SET_DISPLAY_MODE;
data[1] = 0x00;
ret = mapphone_panel_lp_cmd_wrt_sync(true, 0x00,
data, 2,
EDISCO_CMD_SET_DISPLAY_MODE, 1,
data[1], 0x01);
if (ret)
printk(KERN_ERR "failed to send SET_DISPLAY_MODE \n");
/* Set dynamic backlight control and PWM; D[7:4] = PWM_DIV[3:0];*/
/* D[3]=0 (PWM OFF);
* D[2]=0 (auto BL control OFF for 1st source display only);
* D[1]=0 (Grama correction On for 1st source display only);
* D[0]=0 (Enhanced Image Correction OFF) */
data[0] = EDISCO_CMD_SET_BCKLGHT_PWM;
/* AUO displays require a different setting */
if (dssdev->panel.panel_id == MOT_DISP_370_MIPI_480_854_CM)
data[1] = 0x09;
else
data[1] = 0x1f;
ret = mapphone_panel_lp_cmd_wrt_sync(true, 0x00,
data, 2,
EDISCO_CMD_SET_BCKLGHT_PWM, 1,
data[1], 0x1f);
if (ret)
printk(KERN_ERR "failed to send CABC/PWM \n");
data[0] = EDISCO_CMD_EXIT_SLEEP_MODE;
ret = mapphone_panel_lp_cmd_wrt_sync(true, 0x0,
data, 1,
EDISCO_CMD_GET_POWER_MODE, 1,
EDISCO_CMD_SLEEP_MODE_OUT, EDISCO_CMD_SLEEP_MODE_OUT);
if (ret) {
printk(KERN_ERR "failed to send EXIT_SLEEP_MODE \n");
goto error;
}
/*
* 200ms delay for internal block stabilization required before panel
* turns on after EDISCO_CMD_SLEEP_MODE_OUT command
*/
set_delay_timer(dssdev, 200);
/*
* Allow the OTP setting to load
*/
msleep(5);
printk(KERN_INFO "done EDISCO CTRL ENABLE\n");
return 0;
error:
return -EINVAL;
}
/* - In the LP mode, some panels have problems to receive command correctly
* so we will send command out and read it back to make sure the write
* command is accepted
* - if the dsi_vc_dcs_write() request, then we will not care about the
* write_dt (data type) */
static int mapphone_panel_lp_cmd_wrt_sync(bool dcs_cmd, int write_dt,
u8 *write_data, int write_len,
int read_cmd, int read_len,
int chk_val, int chk_mask)
{
int i, ret;
u8 data[7];
for (i = 0; i < DCS_CMD_RETRY_MAX; i++) {
if (dcs_cmd == true) {
ret = dsi_vc_dcs_write(EDISCO_CMD_VC,
write_data, write_len);
DBG("call dsi_vc_dcs_write"
"(len=0%d, p1/p2/p3/p4=0x%x/0x%x/0x%x/0x%x)\n",
write_len, write_data[0],
write_data[1], write_data[2], write_data[3]);
} else {
ret = dsi_vc_write(EDISCO_CMD_VC, write_dt,
write_data, write_len);
DBG("call dsi_vc_write"
"(dt=0x%x len=%d, p1/p2/p3/p4 = "
"0x%x/0x%x/0x%x/0x%x)\n",
write_dt, write_len, write_data[0],
write_data[1], write_data[2], write_data[3]);
}
if (ret) {
printk(KERN_ERR "failed to send cmd=0x%x \n",
write_data[0]);
continue;
}
mdelay(1);
/* TODO. Do not know how to handle and to check if more than
* 1 byte to read is requested*/
if (read_len < 0 || read_len > 1) {
printk(KERN_ERR "Invalid read_len=%d\n", read_len);
return -1;
}
/* Read the data back to make sure write_command is working */
data[0] = 0;
ret = dsi_vc_dcs_read(EDISCO_CMD_VC, read_cmd,
&data[0], read_len);
DBG("read_chk_cmd dcs_cmd=%d read_cmd=0x%x "
"read_len=%d chk_val=0x%x chk_mask=0x%x "
"read_val=0x%x \n",
dcs_cmd, read_cmd, read_len, chk_val,
chk_mask, data[0]);
if (ret < 0)
DBG("fail to read 0x%x cmd and "
"will try it again \n", read_cmd);
if ((data[0] & chk_mask) == chk_val) {
/* break if read back the same writing value*/
ret = 0;
break;
}
}
if (i >= DCS_CMD_RETRY_MAX) {
printk(KERN_ERR "failed to read dcs_cmd=%d read_cmd=0x%x "
"read_len=%d chk_val=0x%x chk_mask=0x%x\n"
"read_val=0x%x \n",
dcs_cmd, read_cmd, read_len, chk_val,
chk_mask, data[0]);
ret = -1;
}
return ret;
}
static int dsi_mipi_310_2_cm_320_480_panel_enable(
struct omap_dss_device *dssdev)
{
u8 data[7];
int ret = 0;
DBG("dsi_mipi_310_2_cm_320_480_panel_enable \n");
data[0] = EDISCO_CMD_EXIT_SLEEP_MODE;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 1);
data[0] = 0;
mdelay(10);
/* turn off mcs register acces protection */
data[0] = EDISCO_CMD_SET_MCS;
data[1] = 0x00;
ret = dsi_vc_write(EDISCO_CMD_VC, EDISCO_SHORT_WRITE_1, data, 2);
ret = dsi_vc_set_max_rx_packet_size(EDISCO_CMD_VC, 6);
if (ret)
printk(KERN_ERR "failed to set max_rx__packet_size\n");
memset(data, 0, sizeof(data));
ret = dsi_vc_dcs_read(EDISCO_CMD_VC, EDISCO_CMD_READ_DDB_START,
data, 6);
printk(KERN_INFO "Supplier id return=0x%x%x, "
"Manufacturer Version=0x%x%x, Revision=0x%x%x\n",
data[0], data[1], data[2], data[3],
data[4], data[5]);
dsi_vc_set_max_rx_packet_size(EDISCO_CMD_VC, 1);
data[0] = 0x3a;
if (dssdev->ctrl.pixel_size == 16)
data[1] = 0x05;
else if (dssdev->ctrl.pixel_size != 18)
data[1] = 0x06;
else {
printk(KERN_ERR "Invalied format pixel_size =%d\n",
dssdev->ctrl.pixel_size);
goto error;
}
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 2);
/* Enable maximum brightness */
data[0] = 0x51;
data[1] = 0xff;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 2);
memset(data, 0, sizeof(data));
/* Enable CABC Output */
data[0] = 0x53;
data[1] = 0x2c;
ret = dsi_vc_dcs_write(EDISCO_CMD_VC, data, 2);
printk(KERN_INFO "done EDISCO CTRL ENABLE\n");
return 0;
error:
return -EINVAL;
}
