int main(void)
{
mailbox = (unsigned *)0x00006000;
mailbox1 = (unsigned *)0x00006100;
// Initialize the mailbox
mailbox[0] = 0x00000000;
mailbox1[0] = 0x00000000;
// Preparing for the interrupt
// Attach the ISR with this interrupt
e_irq_attach(E_MESSAGE_INT, int_isr);
// Clear the IMASK
e_irq_mask(E_MESSAGE_INT, E_FALSE);
// Enable the global interrupt
e_irq_global_mask(E_FALSE);
// Making slave_core into idle and wait for the finishing transfer interrupt
__asm__ __volatile__("idle");
// Showing coming back from the interrupt
mailbox1[0] = 0xffffffff;
// Set the IMASK
e_irq_mask(E_MESSAGE_INT, E_TRUE);
// Disable the global interrupt
e_irq_global_mask(E_TRUE);
return 0;
}
/**
* stop this trace, free resources
*/
int trace_stop()
{
// make sure we stop things
e_ctimer_stop(E_CTIMER_1);
e_irq_mask(E_TIMER1_INT, 1);
// unregister ISR?
return 0;
}
/**
* Start trace, but wait until all processors on this chip are ready and waiting to start
*/
int trace_start_wait_all()
{
e_irq_attach(E_WAND_INT, wand_trace_isr);
e_irq_mask(E_WAND_INT, 0);
__asm__ __volatile__("wand"); // Set our WAND bit
__asm__ __volatile__("idle"); // Idle and wait for an interrupt
e_ctimer_start(E_CTIMER_1, E_CTIMER_CLK); // Start counting
return 0;
}
int main(void){
test_t *me = (void *) 0x7000;
void *pmem, *src, *dst;
pmem = (void *) (e_emem_config.base + 0x01000000);
me->eot = 0;
me->sram_clocks_read = me->sram_clocks_write = 11223344;
me->eram_clocks_read = me->eram_clocks_write = 55667788;
me->eot = 1;
// Initialize timer
e_irq_mask(E_TIMER0_INT, E_TRUE);
e_ctimer_start(E_CTIMER_0, E_CTIMER_CLK);
// Measure time for local -> SRAM
src = (void *) (Abuf);
dst = (void *) e_get_global_address(0, 1, (void *) 0x2000);
me->sram_clocks_write = e_ctimer_set(E_CTIMER_0, E_CTIMER_MAX);
e_memcopy(dst, src, _BUF_SZ);
me->sram_clocks_write -= e_ctimer_get(E_CTIMER_0);
me->eot = 2;
// Measure time for SRAM -> local
src = (void *) e_get_global_address(0, 1, (void *) 0x4000);
dst = (void *) (Bbuf);
me->sram_clocks_read = e_ctimer_set(E_CTIMER_0, E_CTIMER_MAX);
e_memcopy(dst, src, _BUF_SZ);
me->sram_clocks_read -= e_ctimer_get(E_CTIMER_0);
me->eot = 3;
// Measure time for local -> ERAM
src = (void *) (Abuf);
dst = (void *) (pmem+0x0000);
me->eram_clocks_write = e_ctimer_set(E_CTIMER_0, E_CTIMER_MAX);
e_memcopy(dst, src, _BUF_SZ);
me->eram_clocks_write -= e_ctimer_get(E_CTIMER_0);
me->eot = 4;
// Measure time for ERAM -> local
src = (void *) (pmem+0x0000);
dst = (void *) (Bbuf);
me->eram_clocks_read = e_ctimer_set(E_CTIMER_0, E_CTIMER_MAX);
e_memcopy(dst, src, _BUF_SZ);
me->eram_clocks_read -= e_ctimer_get(E_CTIMER_0);
me->eot = 5;
return EXIT_SUCCESS;
}
int trace_start_wait_all()
{
unsigned irqState;
e_irq_global_mask(E_FALSE);
e_irq_attach(E_WAND_INT, wand_trace_isr);
e_irq_mask(E_WAND_INT, E_FALSE);
__asm__ __volatile__("wand"); // Set our WAND bit
__asm__ __volatile__("idle"); // Idle and wait for an interrupt
irqState = e_reg_read(E_REG_STATUS);
irqState = irqState & (~0x8); // This is the WAND interrupt flag
e_reg_write(E_REG_FSTATUS, irqState);
//e_ctimer_start(E_CTIMER_1, E_CTIMER_CLK); // Start counting
return 0;
}
static void sync(void)
{
uint32_t irq_state;
/* enable WAND interrupt */
e_irq_attach(WAND_BIT, wand_trace_isr);
e_irq_mask(WAND_BIT, E_FALSE);
/* WAND + IDLE */
__asm__ __volatile__("wand");
__asm__ __volatile__("idle");
/* acknowledge interrupt */
irq_state = e_reg_read(E_REG_STATUS);
irq_state &= ~WAND_BIT;
e_reg_write(E_REG_STATUS, irq_state);
}
/**
* Initialize data structures, call this first before using trace functions
*/
int trace_init()
{
// If I am the master
if(e_get_coreid() == TRACE_MASTER_ID) {
// setup my DMA engine
setupDMA2(); // REMEMBER TO CHANGE
}
//register timer ISR
e_irq_global_mask(0);
e_irq_attach(E_TIMER1_INT, timer1_trace_isr);
e_irq_mask(E_TIMER1_INT, 0);
// setup timer 1 for work
e_ctimer_stop(E_CTIMER_1);
e_ctimer_set(E_CTIMER_1, E_CTIMER_MAX);
logCoreid = (e_get_coreid()& 0xFFF) << 8; // make it easy to use core-id
return 0;
}
int main(void) {
//initialize
int i;
unsigned row, col, delay, num;
unsigned *ivt;
e_irq_global_mask(E_FALSE);
e_irq_attach(E_WAND_INT, wand_isr);
e_irq_mask(E_WAND_INT, E_FALSE);
row = e_group_config.core_row;
col = e_group_config.core_col;
num = row * e_group_config.group_cols + col;
pause = (volatile uint32_t *) (0x7000);
result = (volatile unsigned *) (0x8f000000 + 0x4*num);
delay = 0x2000 * num + 0x2000;
if (num == 0)
*pause = 0;
*result = 0xdeadbeef;
for(i=0; i<0x10000; i++)
{
*result = i;
e_wait(E_CTIMER_0, delay);
if (num == 0)
while ((*pause));
__asm__ __volatile__("wand");
__asm__ __volatile__("idle");
// clear wand bit
state = e_reg_read(E_REG_STATUS);
state = state & (~0x8);
e_reg_write(E_REG_FSTATUS, state);
}
return EXIT_SUCCESS;
}
int main(void)
{
unsigned *a, *b, *c, *size;
unsigned i, j;
int coreid;
unsigned *src, *dest;
unsigned row, col;
coreid = e_get_coreid() ^ 0x0c3; // Copy to the opposite core in chip
src = (unsigned *) 0x6000;
dest = (void *) ((coreid<<20) | 0x6000);
size = (unsigned *) 0x1e00;
a = (unsigned *) 0x2000;
b = (unsigned *) 0x4000;
c = (unsigned *) 0x6000;
// Doing convolution to generate busy level
for (i=0; i<(*size); i++)
{
for (j=0; j<=i; j++)
{
c[i] += a[i-j] * b[j];
}
}
for(i=0; i<100000; i++)
{
e_dma_copy(dest, src, *size);
}
// clear the IMASK
e_irq_mask(E_SYNC, E_FALSE);
// enable the global interrupt
e_irq_global_mask(E_FALSE);
__asm__ __volatile__("idle");
return EXIT_SUCCESS;
}
