/* * Given a NIC memory source address and a host memory destination * address, copy 'amount' from NIC to host using Programmed I/O. * The 'amount' is rounded up to a word - okay as long as mbufs * are word sized. * This routine is currently Novell-specific. */ void ed_pio_readmem(struct ed_softc *sc, bus_size_t src, uint8_t *dst, uint16_t amount) { /* Regular Novell cards */ /* select page 0 registers */ ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA); /* round up to a word */ if (amount & 1) ++amount; /* set up DMA byte count */ ed_nic_outb(sc, ED_P0_RBCR0, amount); ed_nic_outb(sc, ED_P0_RBCR1, amount >> 8); /* set up source address in NIC mem */ ed_nic_outb(sc, ED_P0_RSAR0, src); ed_nic_outb(sc, ED_P0_RSAR1, src >> 8); ed_nic_outb(sc, ED_P0_CR, ED_CR_RD0 | ED_CR_STA); if (sc->isa16bit) ed_asic_insw(sc, ED_NOVELL_DATA, dst, amount / 2); else ed_asic_insb(sc, ED_NOVELL_DATA, dst, amount); }
/* * This routine actually starts the transmission on the interface */ static __inline void ed_xmit(struct ed_softc *sc) { unsigned short len; len = sc->txb_len[sc->txb_next_tx]; /* * Set NIC for page 0 register access */ ed_nic_barrier(sc, ED_P0_CR, 1, BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA); ed_nic_barrier(sc, ED_P0_CR, 1, BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); /* * Set TX buffer start page */ ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start + sc->txb_next_tx * ED_TXBUF_SIZE); /* * Set TX length */ ed_nic_outb(sc, ED_P0_TBCR0, len); ed_nic_outb(sc, ED_P0_TBCR1, len >> 8); /* * Set page 0, Remote DMA complete, Transmit Packet, and *Start* */ ed_nic_barrier(sc, ED_P0_CR, 1, BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA); ed_nic_barrier(sc, ED_P0_CR, 1, BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); sc->xmit_busy = 1; /* * Point to next transmit buffer slot and wrap if necessary. */ sc->txb_next_tx++; if (sc->txb_next_tx == sc->txb_cnt) sc->txb_next_tx = 0; /* * Set a timer just in case we never hear from the board again */ sc->tx_timer = 2; }
/* * MII bus support routines. */ static int ed_miibus_readreg(device_t dev, int phy, int reg) { struct ed_softc *sc; int val; uint8_t cr = 0; sc = device_get_softc(dev); /* * The AX88790 has an interesting quirk. It has an internal phy that * needs a special bit set to access, but can also have additional * external PHYs set for things like HomeNET media. When accessing * the internal PHY, a bit has to be set, when accessing the external * PHYs, it must be clear. See Errata 1, page 51, in the AX88790 * datasheet for more details. * * Also, PHYs above 16 appear to be phantoms on some cards, but not * others. Registers read for this are often the same as prior values * read. Filter all register requests to 17-31. */ if (sc->chip_type == ED_CHIP_TYPE_AX88790) { if (phy > 0x10) return (0); if (phy == 0x10) ed_asic_outb(sc, ED_AX88X90_GPIO, ED_AX88X90_GPIO_INT_PHY); else ed_asic_outb(sc, ED_AX88X90_GPIO, 0); ed_asic_barrier(sc, ED_AX88X90_GPIO, 1, BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); } else if (sc->chip_type == ED_CHIP_TYPE_TC5299J) { /* Select page 3. */ ed_nic_barrier(sc, ED_P0_CR, 1, BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); cr = ed_nic_inb(sc, ED_P0_CR); ed_nic_outb(sc, ED_P0_CR, cr | ED_CR_PAGE_3); ed_nic_barrier(sc, ED_P0_CR, 1, BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); } val = mii_bitbang_readreg(dev, sc->mii_bitbang_ops, phy, reg); if (sc->chip_type == ED_CHIP_TYPE_TC5299J) { /* Restore prior page. */ ed_nic_outb(sc, ED_P0_CR, cr); ed_nic_barrier(sc, ED_P0_CR, 1, BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); } return (val); }
static void ed_rtl_get_media(struct ifnet *ifp, struct ifmediareq *imr) { struct ed_softc *sc; sc = ifp->if_softc; imr->ifm_active = sc->ifmedia.ifm_cur->ifm_media; if (IFM_SUBTYPE(imr->ifm_active) == IFM_AUTO) { ED_LOCK(sc); ed_nic_barrier(sc, ED_P0_CR, 1, BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_3 | (ed_nic_inb(sc, ED_P0_CR) & (ED_CR_STA | ED_CR_STP))); ed_nic_barrier(sc, ED_P0_CR, 1, BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); switch (ed_nic_inb(sc, ED_RTL80X9_CONFIG0) & (sc->chip_type == ED_CHIP_TYPE_RTL8029 ? ED_RTL80X9_CF0_BNC : (ED_RTL80X9_CF0_AUI | ED_RTL80X9_CF0_BNC))) { case ED_RTL80X9_CF0_BNC: imr->ifm_active |= IFM_10_2; break; case ED_RTL80X9_CF0_AUI: imr->ifm_active |= IFM_10_5; break; default: imr->ifm_active |= IFM_10_T; break; } ED_UNLOCK(sc); } imr->ifm_status = 0; }
static void ed_stop_hw(struct ed_softc *sc) { int n = 5000; /* * Stop everything on the interface, and select page 0 registers. */ ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP); /* * Wait for interface to enter stopped state, but limit # of checks to * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but * just in case it's an old one. * * The AX88x90 chips don't seem to implement this behavor. The * datasheets say it is only turned on when the chip enters a RESET * state and is silent about behavior for the stopped state we just * entered. */ if (sc->chip_type == ED_CHIP_TYPE_AX88190 || sc->chip_type == ED_CHIP_TYPE_AX88790) return; while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) == 0) && --n) continue; if (n <= 0) device_printf(sc->dev, "ed_stop_hw RST never set\n"); }
/* * Stripped down routine for writing a linear buffer to NIC memory. * Only used in the probe routine to test the memory. 'len' must * be even. */ void ed_pio_writemem(struct ed_softc *sc, uint8_t *src, uint16_t dst, uint16_t len) { int maxwait = 200; /* about 240us */ /* select page 0 registers */ ed_nic_barrier(sc, ED_P0_CR, 1, BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA); ed_nic_barrier(sc, ED_P0_CR, 1, BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); /* reset remote DMA complete flag */ ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC); /* set up DMA byte count */ ed_nic_outb(sc, ED_P0_RBCR0, len); ed_nic_outb(sc, ED_P0_RBCR1, len >> 8); /* set up destination address in NIC mem */ ed_nic_outb(sc, ED_P0_RSAR0, dst); ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8); /* set remote DMA write */ ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA); if (sc->isa16bit) ed_asic_outsw(sc, ED_NOVELL_DATA, src, len / 2); else ed_asic_outsb(sc, ED_NOVELL_DATA, src, len); /* * Wait for remote DMA complete. This is necessary because on the * transmit side, data is handled internally by the NIC in bursts and * we can't start another remote DMA until this one completes. Not * waiting causes really bad things to happen - like the NIC * irrecoverably jamming the ISA bus. */ while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait) continue; }
static void ed_pccard_tc5299j_mii_bitbang_write(device_t dev, uint32_t val) { struct ed_softc *sc; sc = device_get_softc(dev); /* We are already on page 3. */ ed_nic_outb(sc, ED_TC5299J_MIIBUS, val); ed_nic_barrier(sc, ED_TC5299J_MIIBUS, 1, BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); }
static void ed_pccard_ax88x90_reset(struct ed_softc *sc) { int i; /* Reset Card */ ed_nic_barrier(sc, ED_P0_CR, 1, BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STP | ED_CR_PAGE_0); ed_nic_barrier(sc, ED_P0_CR, 1, BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); ed_asic_outb(sc, ED_NOVELL_RESET, ed_asic_inb(sc, ED_NOVELL_RESET)); /* Wait for the RST bit to assert, but cap it at 10ms */ for (i = 10000; !(ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) && i > 0; i--) continue; ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RST); /* ACK INTR */ if (i == 0) device_printf(sc->dev, "Reset didn't finish\n"); }
static int ed_miibus_writereg(device_t dev, int phy, int reg, int data) { struct ed_softc *sc; uint8_t cr = 0; sc = device_get_softc(dev); /* See ed_miibus_readreg for details */ if (sc->chip_type == ED_CHIP_TYPE_AX88790) { if (phy > 0x10) return (0); if (phy == 0x10) ed_asic_outb(sc, ED_AX88X90_GPIO, ED_AX88X90_GPIO_INT_PHY); else ed_asic_outb(sc, ED_AX88X90_GPIO, 0); ed_asic_barrier(sc, ED_AX88X90_GPIO, 1, BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); } else if (sc->chip_type == ED_CHIP_TYPE_TC5299J) { /* Select page 3. */ ed_nic_barrier(sc, ED_P0_CR, 1, BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); cr = ed_nic_inb(sc, ED_P0_CR); ed_nic_outb(sc, ED_P0_CR, cr | ED_CR_PAGE_3); ed_nic_barrier(sc, ED_P0_CR, 1, BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); } mii_bitbang_writereg(dev, sc->mii_bitbang_ops, phy, reg, data); if (sc->chip_type == ED_CHIP_TYPE_TC5299J) { /* Restore prior page. */ ed_nic_outb(sc, ED_P0_CR, cr); ed_nic_barrier(sc, ED_P0_CR, 1, BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); } return (0); }
static int ed_rtl_set_media(struct ifnet *ifp) { struct ed_softc *sc; sc = ifp->if_softc; ED_LOCK(sc); ed_nic_barrier(sc, ED_P0_CR, 1, BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_3 | (ed_nic_inb(sc, ED_P0_CR) & (ED_CR_STA | ED_CR_STP))); ed_nic_barrier(sc, ED_P0_CR, 1, BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); switch(IFM_SUBTYPE(sc->ifmedia.ifm_cur->ifm_media)) { case IFM_10_T: ed_nic_outb(sc, ED_RTL80X9_CONFIG2, ED_RTL80X9_CF2_10_T | (ed_nic_inb(sc, ED_RTL80X9_CONFIG2) & ~ED_RTL80X9_CF2_MEDIA)); break; case IFM_10_2: ed_nic_outb(sc, ED_RTL80X9_CONFIG2, ED_RTL80X9_CF2_10_2 | (ed_nic_inb(sc, ED_RTL80X9_CONFIG2) & ~ED_RTL80X9_CF2_MEDIA)); break; case IFM_10_5: ed_nic_outb(sc, ED_RTL80X9_CONFIG2, ED_RTL80X9_CF2_10_5 | (ed_nic_inb(sc, ED_RTL80X9_CONFIG2) & ~ED_RTL80X9_CF2_MEDIA)); break; case IFM_AUTO: ed_nic_outb(sc, ED_RTL80X9_CONFIG2, ED_RTL80X9_CF2_AUTO | (ed_nic_inb(sc, ED_RTL80X9_CONFIG2) & ~ED_RTL80X9_CF2_MEDIA)); break; } ed_nic_outb(sc, ED_RTL80X9_CONFIG3, (sc->ifmedia.ifm_cur->ifm_media & IFM_FDX) ? (ed_nic_inb(sc, ED_RTL80X9_CONFIG3) | ED_RTL80X9_CF3_FUDUP) : (ed_nic_inb(sc, ED_RTL80X9_CONFIG3) & ~ED_RTL80X9_CF3_FUDUP)); ED_UNLOCK(sc); return (0); }
/* * Probe and vendor-specific initialization routine for ax88x90 boards */ static int ed_probe_ax88x90_generic(device_t dev, int flags) { struct ed_softc *sc = device_get_softc(dev); u_int memsize; static char test_pattern[32] = "THIS is A memory TEST pattern"; char test_buffer[32]; ed_pccard_ax88x90_reset(sc); DELAY(10*1000); /* Make sure that we really have an 8390 based board */ if (!ed_probe_generic8390(sc)) return (ENXIO); sc->vendor = ED_VENDOR_NOVELL; sc->mem_shared = 0; sc->cr_proto = ED_CR_RD2; /* * This prevents packets from being stored in the NIC memory when the * readmem routine turns on the start bit in the CR. We write some * bytes in word mode and verify we can read them back. If we can't * then we don't have an AX88x90 chip here. */ sc->isa16bit = 1; ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON); ed_nic_outb(sc, ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS); ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern)); ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern)); if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) != 0) return (ENXIO); /* * Hard code values based on the datasheet. We're NE-2000 compatible * NIC with 16kb of packet memory starting at 16k offset. */ sc->type = ED_TYPE_NE2000; memsize = sc->mem_size = 16*1024; sc->mem_start = 16 * 1024; if (ed_asic_inb(sc, ED_AX88X90_TEST) != 0) sc->chip_type = ED_CHIP_TYPE_AX88790; else { sc->chip_type = ED_CHIP_TYPE_AX88190; /* * The AX88190 (not A) has external 64k SRAM. Probe for this * here. Most of the cards I have either use the AX88190A * part, or have only 32k SRAM for some reason, so I don't * know if this works or not. */ ed_pio_writemem(sc, test_pattern, 32768, sizeof(test_pattern)); ed_pio_readmem(sc, 32768, test_buffer, sizeof(test_pattern)); if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) { sc->mem_start = 2*1024; memsize = sc->mem_size = 62 * 1024; } } sc->mem_end = sc->mem_start + memsize; sc->tx_page_start = memsize / ED_PAGE_SIZE; if (sc->mem_size > 16 * 1024) sc->txb_cnt = 3; else sc->txb_cnt = 2; sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE; sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE; sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE; ed_nic_outb(sc, ED_P0_PSTART, sc->mem_start / ED_PAGE_SIZE); ed_nic_outb(sc, ED_P0_PSTOP, sc->mem_end / ED_PAGE_SIZE); /* Get the mac before we go -- It's just at 0x400 in "SRAM" */ ed_pio_readmem(sc, 0x400, sc->enaddr, ETHER_ADDR_LEN); /* clear any pending interrupts that might have occurred above */ ed_nic_outb(sc, ED_P0_ISR, 0xff); sc->sc_write_mbufs = ed_pio_write_mbufs; return (0); }
/* * Probe and vendor-specific initialization routine for 3Com 3c503 boards */ int ed_probe_3Com(device_t dev, int port_rid, int flags) { struct ed_softc *sc = device_get_softc(dev); int error; int i; u_int memsize; u_char isa16bit; u_long conf_maddr, conf_msize, irq, junk, pmem; error = ed_alloc_port(dev, 0, ED_3COM_IO_PORTS); if (error) return (error); sc->asic_offset = ED_3COM_ASIC_OFFSET; sc->nic_offset = ED_3COM_NIC_OFFSET; /* * Verify that the kernel configured I/O address matches the board * configured address */ switch (ed_asic_inb(sc, ED_3COM_BCFR)) { case ED_3COM_BCFR_300: if (rman_get_start(sc->port_res) != 0x300) return (ENXIO); break; case ED_3COM_BCFR_310: if (rman_get_start(sc->port_res) != 0x310) return (ENXIO); break; case ED_3COM_BCFR_330: if (rman_get_start(sc->port_res) != 0x330) return (ENXIO); break; case ED_3COM_BCFR_350: if (rman_get_start(sc->port_res) != 0x350) return (ENXIO); break; case ED_3COM_BCFR_250: if (rman_get_start(sc->port_res) != 0x250) return (ENXIO); break; case ED_3COM_BCFR_280: if (rman_get_start(sc->port_res) != 0x280) return (ENXIO); break; case ED_3COM_BCFR_2A0: if (rman_get_start(sc->port_res) != 0x2a0) return (ENXIO); break; case ED_3COM_BCFR_2E0: if (rman_get_start(sc->port_res) != 0x2e0) return (ENXIO); break; default: return (ENXIO); } error = bus_get_resource(dev, SYS_RES_MEMORY, 0, &conf_maddr, &conf_msize); if (error) return (error); /* * Verify that the kernel shared memory address matches the board * configured address. */ switch (ed_asic_inb(sc, ED_3COM_PCFR)) { case ED_3COM_PCFR_DC000: if (conf_maddr != 0xdc000) return (ENXIO); break; case ED_3COM_PCFR_D8000: if (conf_maddr != 0xd8000) return (ENXIO); break; case ED_3COM_PCFR_CC000: if (conf_maddr != 0xcc000) return (ENXIO); break; case ED_3COM_PCFR_C8000: if (conf_maddr != 0xc8000) return (ENXIO); break; default: return (ENXIO); } /* * Reset NIC and ASIC. Enable on-board transceiver throughout reset * sequence because it'll lock up if the cable isn't connected if we * don't. */ ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL); /* * Wait for a while, then un-reset it */ DELAY(50); /* * The 3Com ASIC defaults to rather strange settings for the CR after * a reset - it's important to set it again after the following outb * (this is done when we map the PROM below). */ ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL); /* * Wait a bit for the NIC to recover from the reset */ DELAY(5000); sc->vendor = ED_VENDOR_3COM; sc->type_str = "3c503"; sc->mem_shared = 1; sc->cr_proto = ED_CR_RD2; /* * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k window * to it. */ memsize = 8192; /* * Get station address from on-board ROM */ /* * First, map ethernet address PROM over the top of where the NIC * registers normally appear. */ ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL); for (i = 0; i < ETHER_ADDR_LEN; ++i) sc->enaddr[i] = ed_nic_inb(sc, i); /* * Unmap PROM - select NIC registers. The proper setting of the * tranceiver is set in ed_init so that the attach code is given a * chance to set the default based on a compile-time config option */ ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL); /* * Determine if this is an 8bit or 16bit board */ /* * select page 0 registers */ ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STP); /* * Attempt to clear WTS bit. If it doesn't clear, then this is a 16bit * board. */ ed_nic_outb(sc, ED_P0_DCR, 0); /* * select page 2 registers */ ed_nic_outb(sc, ED_P0_CR, ED_CR_PAGE_2 | ED_CR_RD2 | ED_CR_STP); /* * The 3c503 forces the WTS bit to a one if this is a 16bit board */ if (ed_nic_inb(sc, ED_P2_DCR) & ED_DCR_WTS) isa16bit = 1; else isa16bit = 0; /* * select page 0 registers */ ed_nic_outb(sc, ED_P2_CR, ED_CR_RD2 | ED_CR_STP); error = ed_alloc_memory(dev, 0, memsize); if (error) return (error); pmem = rman_get_start(sc->mem_res); error = ed_isa_mem_ok(dev, pmem, memsize); if (error) return (error); sc->mem_start = 0; sc->mem_size = memsize; sc->mem_end = sc->mem_start + memsize; /* * We have an entire 8k window to put the transmit buffers on the * 16bit boards. But since the 16bit 3c503's shared memory is only * fast enough to overlap the loading of one full-size packet, trying * to load more than 2 buffers can actually leave the transmitter idle * during the load. So 2 seems the best value. (Although a mix of * variable-sized packets might change this assumption. Nonetheless, * we optimize for linear transfers of same-size packets.) */ if (isa16bit) { if (flags & ED_FLAGS_NO_MULTI_BUFFERING) sc->txb_cnt = 1; else sc->txb_cnt = 2; sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT; sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT; sc->rec_page_stop = memsize / ED_PAGE_SIZE + ED_3COM_RX_PAGE_OFFSET_16BIT; sc->mem_ring = sc->mem_start; } else { sc->txb_cnt = 1; sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT; sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT; sc->rec_page_stop = memsize / ED_PAGE_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT; sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE); } sc->isa16bit = isa16bit; /* * Initialize GA page start/stop registers. Probably only needed if * doing DMA, but what the hell. */ ed_asic_outb(sc, ED_3COM_PSTR, sc->rec_page_start); ed_asic_outb(sc, ED_3COM_PSPR, sc->rec_page_stop); /* * Set IRQ. 3c503 only allows a choice of irq 2-5. */ error = bus_get_resource(dev, SYS_RES_IRQ, 0, &irq, &junk); if (error) return (error); switch (irq) { case 2: case 9: ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2); break; case 3: ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3); break; case 4: ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4); break; case 5: ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5); break; default: device_printf(dev, "Invalid irq configuration (%ld) must be 3-5,9 for 3c503\n", irq); return (ENXIO); } /* * Initialize GA configuration register. Set bank and enable shared * mem. */ ed_asic_outb(sc, ED_3COM_GACFR, ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0); /* * Initialize "Vector Pointer" registers. These gawd-awful things are * compared to 20 bits of the address on ISA, and if they match, the * shared memory is disabled. We set them to 0xffff0...allegedly the * reset vector. */ ed_asic_outb(sc, ED_3COM_VPTR2, 0xff); ed_asic_outb(sc, ED_3COM_VPTR1, 0xff); ed_asic_outb(sc, ED_3COM_VPTR0, 0x00); error = ed_clear_memory(dev); if (error == 0) { sc->sc_mediachg = ed_3c503_mediachg; sc->sc_write_mbufs = ed_shmem_write_mbufs; } return (error); }
/* * Write an mbuf chain to the destination NIC memory address using * programmed I/O. */ u_short ed_pio_write_mbufs(struct ed_softc *sc, struct mbuf *m, bus_size_t dst) { struct ifnet *ifp = sc->ifp; unsigned short total_len, dma_len; struct mbuf *mp; int maxwait = 200; /* about 240us */ ED_ASSERT_LOCKED(sc); /* Regular Novell cards */ /* First, count up the total number of bytes to copy */ for (total_len = 0, mp = m; mp; mp = mp->m_next) total_len += mp->m_len; dma_len = total_len; if (sc->isa16bit && (dma_len & 1)) dma_len++; /* select page 0 registers */ ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA); /* reset remote DMA complete flag */ ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC); /* set up DMA byte count */ ed_nic_outb(sc, ED_P0_RBCR0, dma_len); ed_nic_outb(sc, ED_P0_RBCR1, dma_len >> 8); /* set up destination address in NIC mem */ ed_nic_outb(sc, ED_P0_RSAR0, dst); ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8); /* set remote DMA write */ ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA); /* * Transfer the mbuf chain to the NIC memory. * 16-bit cards require that data be transferred as words, and only words. * So that case requires some extra code to patch over odd-length mbufs. */ if (!sc->isa16bit) { /* NE1000s are easy */ while (m) { if (m->m_len) ed_asic_outsb(sc, ED_NOVELL_DATA, m->m_data, m->m_len); m = m->m_next; } } else { /* NE2000s are a pain */ uint8_t *data; int len, wantbyte; union { uint16_t w; uint8_t b[2]; } saveword; wantbyte = 0; while (m) { len = m->m_len; if (len) { data = mtod(m, caddr_t); /* finish the last word */ if (wantbyte) { saveword.b[1] = *data; ed_asic_outw(sc, ED_NOVELL_DATA, saveword.w); data++; len--; wantbyte = 0; } /* output contiguous words */ if (len > 1) { ed_asic_outsw(sc, ED_NOVELL_DATA, data, len >> 1); data += len & ~1; len &= 1; } /* save last byte, if necessary */ if (len == 1) { saveword.b[0] = *data; wantbyte = 1; } } m = m->m_next; } /* spit last byte */ if (wantbyte) ed_asic_outw(sc, ED_NOVELL_DATA, saveword.w); }
/* * Probe the Ethernet MAC addrees for PCMCIA Linksys EtherFast 10/100 * and compatible cards (DL10019C Ethernet controller). */ static int ed_pccard_dl100xx(device_t dev, const struct ed_product *pp) { struct ed_softc *sc = device_get_softc(dev); u_char sum; uint8_t id; u_int memsize; int i, error; if (!(pp->flags & NE2000DVF_DL100XX)) return (ENXIO); if (bootverbose) device_printf(dev, "Trying DL100xx\n"); error = ed_probe_Novell_generic(dev, device_get_flags(dev)); if (bootverbose && error) device_printf(dev, "Novell generic probe failed: %d\n", error); if (error != 0) return (error); /* * Linksys registers(offset from ASIC base) * * 0x04-0x09 : Physical Address Register 0-5 (PAR0-PAR5) * 0x0A : Card ID Register (CIR) * 0x0B : Check Sum Register (SR) */ for (sum = 0, i = 0x04; i < 0x0c; i++) sum += ed_asic_inb(sc, i); if (sum != 0xff) { if (bootverbose) device_printf(dev, "Bad checksum %#x\n", sum); return (ENXIO); /* invalid DL10019C */ } if (bootverbose) device_printf(dev, "CIR is %d\n", ed_asic_inb(sc, 0xa)); for (i = 0; i < ETHER_ADDR_LEN; i++) sc->enaddr[i] = ed_asic_inb(sc, 0x04 + i); ed_nic_outb(sc, ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS); id = ed_asic_inb(sc, 0xf); sc->isa16bit = 1; /* * Hard code values based on the datasheet. We're NE-2000 compatible * NIC with 24kb of packet memory starting at 24k offset. These * cards also work with 16k at 16k, but don't work with 24k at 16k * or 32k at 16k. */ sc->type = ED_TYPE_NE2000; sc->mem_start = 24 * 1024; memsize = sc->mem_size = 24 * 1024; sc->mem_end = sc->mem_start + memsize; sc->tx_page_start = memsize / ED_PAGE_SIZE; sc->txb_cnt = 3; sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE; sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE; sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE; ed_nic_outb(sc, ED_P0_PSTART, sc->mem_start / ED_PAGE_SIZE); ed_nic_outb(sc, ED_P0_PSTOP, sc->mem_end / ED_PAGE_SIZE); sc->vendor = ED_VENDOR_NOVELL; sc->chip_type = (id & 0x90) == 0x90 ? ED_CHIP_TYPE_DL10022 : ED_CHIP_TYPE_DL10019; sc->type_str = ((id & 0x90) == 0x90) ? "DL10022" : "DL10019"; sc->mii_bitbang_ops = &ed_pccard_dl100xx_mii_bitbang_ops; return (0); }
static void ed_init_locked(struct ed_softc *sc) { struct ifnet *ifp = sc->ifp; int i; ED_ASSERT_LOCKED(sc); /* * Initialize the NIC in the exact order outlined in the NS manual. * This init procedure is "mandatory"...don't change what or when * things happen. */ /* reset transmitter flags */ sc->xmit_busy = 0; sc->tx_timer = 0; sc->txb_inuse = 0; sc->txb_new = 0; sc->txb_next_tx = 0; /* This variable is used below - don't move this assignment */ sc->next_packet = sc->rec_page_start + 1; /* * Set interface for page 0, Remote DMA complete, Stopped */ ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP); if (sc->isa16bit) /* * Set FIFO threshold to 8, No auto-init Remote DMA, byte * order=80x86, word-wide DMA xfers, */ ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS); else /* * Same as above, but byte-wide DMA xfers */ ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS); /* * Clear Remote Byte Count Registers */ ed_nic_outb(sc, ED_P0_RBCR0, 0); ed_nic_outb(sc, ED_P0_RBCR1, 0); /* * For the moment, don't store incoming packets in memory. */ ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON); /* * Place NIC in internal loopback mode */ ed_nic_outb(sc, ED_P0_TCR, ED_TCR_LB0); /* * Initialize transmit/receive (ring-buffer) Page Start */ ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start); ed_nic_outb(sc, ED_P0_PSTART, sc->rec_page_start); /* Set lower bits of byte addressable framing to 0 */ if (sc->chip_type == ED_CHIP_TYPE_WD790) ed_nic_outb(sc, 0x09, 0); /* * Initialize Receiver (ring-buffer) Page Stop and Boundry */ ed_nic_outb(sc, ED_P0_PSTOP, sc->rec_page_stop); ed_nic_outb(sc, ED_P0_BNRY, sc->rec_page_start); /* * Clear all interrupts. A '1' in each bit position clears the * corresponding flag. */ ed_nic_outb(sc, ED_P0_ISR, 0xff); /* * Enable the following interrupts: receive/transmit complete, * receive/transmit error, and Receiver OverWrite. * * Counter overflow and Remote DMA complete are *not* enabled. */ ed_nic_outb(sc, ED_P0_IMR, ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE); /* * Program Command Register for page 1 */ ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP); /* * Copy out our station address */ for (i = 0; i < ETHER_ADDR_LEN; ++i) ed_nic_outb(sc, ED_P1_PAR(i), IF_LLADDR(sc->ifp)[i]); /* * Set Current Page pointer to next_packet (initialized above) */ ed_nic_outb(sc, ED_P1_CURR, sc->next_packet); /* * Program Receiver Configuration Register and multicast filter. CR is * set to page 0 on return. */ ed_setrcr(sc); /* * Take interface out of loopback */ ed_nic_outb(sc, ED_P0_TCR, 0); if (sc->sc_mediachg) sc->sc_mediachg(sc); /* * Set 'running' flag, and clear output active flag. */ ifp->if_drv_flags |= IFF_DRV_RUNNING; ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; /* * ...and attempt to start output */ ed_start_locked(ifp); callout_reset(&sc->tick_ch, hz, ed_tick, sc); }
/* * Ethernet interface receiver interrupt. */ static __inline void ed_rint(struct ed_softc *sc) { struct ifnet *ifp = sc->ifp; u_char boundry; u_short len; struct ed_ring packet_hdr; bus_size_t packet_ptr; ED_ASSERT_LOCKED(sc); /* * Set NIC to page 1 registers to get 'current' pointer */ ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); /* * 'sc->next_packet' is the logical beginning of the ring-buffer - * i.e. it points to where new data has been buffered. The 'CURR' * (current) register points to the logical end of the ring-buffer - * i.e. it points to where additional new data will be added. We loop * here until the logical beginning equals the logical end (or in * other words, until the ring-buffer is empty). */ while (sc->next_packet != ed_nic_inb(sc, ED_P1_CURR)) { /* get pointer to this buffer's header structure */ packet_ptr = sc->mem_ring + (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE; /* * The byte count includes a 4 byte header that was added by * the NIC. */ sc->readmem(sc, packet_ptr, (char *) &packet_hdr, sizeof(packet_hdr)); len = packet_hdr.count; if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) || len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) { /* * Length is a wild value. There's a good chance that * this was caused by the NIC being old and buggy. * The bug is that the length low byte is duplicated * in the high byte. Try to recalculate the length * based on the pointer to the next packet. Also, * need ot preserve offset into page. * * NOTE: sc->next_packet is pointing at the current * packet. */ len &= ED_PAGE_SIZE - 1; if (packet_hdr.next_packet >= sc->next_packet) len += (packet_hdr.next_packet - sc->next_packet) * ED_PAGE_SIZE; else len += ((packet_hdr.next_packet - sc->rec_page_start) + (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE; /* * because buffers are aligned on 256-byte boundary, * the length computed above is off by 256 in almost * all cases. Fix it... */ if (len & 0xff) len -= 256; if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) sc->mibdata.dot3StatsFrameTooLongs++; } /* * Be fairly liberal about what we allow as a "reasonable" * length so that a [crufty] packet will make it to BPF (and * can thus be analyzed). Note that all that is really * important is that we have a length that will fit into one * mbuf cluster or less; the upper layer protocols can then * figure out the length from their own length field(s). But * make sure that we have at least a full ethernet header or * we would be unable to call ether_input() later. */ if ((len >= sizeof(struct ed_ring) + ETHER_HDR_LEN) && (len <= MCLBYTES) && (packet_hdr.next_packet >= sc->rec_page_start) && (packet_hdr.next_packet < sc->rec_page_stop)) { /* * Go get packet. */ ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring), len - sizeof(struct ed_ring)); ifp->if_ipackets++; } else { /* * Really BAD. The ring pointers are corrupted. */ log(LOG_ERR, "%s: NIC memory corrupt - invalid packet length %d\n", ifp->if_xname, len); ifp->if_ierrors++; ed_reset(ifp); return; } /* * Update next packet pointer */ sc->next_packet = packet_hdr.next_packet; /* * Update NIC boundry pointer - being careful to keep it one * buffer behind. (as recommended by NS databook) */ boundry = sc->next_packet - 1; if (boundry < sc->rec_page_start) boundry = sc->rec_page_stop - 1; /* * Set NIC to page 0 registers to update boundry register */ ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA); ed_nic_outb(sc, ED_P0_BNRY, boundry); /* * Set NIC to page 1 registers before looping to top (prepare * to get 'CURR' current pointer) */ ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); } }
/* * Ethernet interface interrupt processor */ void edintr(void *arg) { struct ed_softc *sc = (struct ed_softc*) arg; struct ifnet *ifp = sc->ifp; u_char isr; int count; ED_LOCK(sc); if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { ED_UNLOCK(sc); return; } /* * Set NIC to page 0 registers */ ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA); /* * loop until there are no more new interrupts. When the card goes * away, the hardware will read back 0xff. Looking at the interrupts, * it would appear that 0xff is impossible, or at least extremely * unlikely. */ while ((isr = ed_nic_inb(sc, ED_P0_ISR)) != 0 && isr != 0xff) { /* * reset all the bits that we are 'acknowledging' by writing a * '1' to each bit position that was set (writing a '1' * *clears* the bit) */ ed_nic_outb(sc, ED_P0_ISR, isr); /* * The AX88190 and AX88190A has problems acking an interrupt * and having them clear. This interferes with top-level loop * here. Wait for all the bits to clear. * * We limit this to 5000 iterations. At 1us per inb/outb, * this translates to about 15ms, which should be plenty of * time, and also gives protection in the card eject case. */ if (sc->chip_type == ED_CHIP_TYPE_AX88190) { count = 5000; /* 15ms */ while (count-- && (ed_nic_inb(sc, ED_P0_ISR) & isr)) { ed_nic_outb(sc, ED_P0_ISR,0); ed_nic_outb(sc, ED_P0_ISR,isr); } if (count == 0) break; } /* * Handle transmitter interrupts. Handle these first because * the receiver will reset the board under some conditions. */ if (isr & (ED_ISR_PTX | ED_ISR_TXE)) { u_char collisions = ed_nic_inb(sc, ED_P0_NCR) & 0x0f; /* * Check for transmit error. If a TX completed with an * error, we end up throwing the packet away. Really * the only error that is possible is excessive * collisions, and in this case it is best to allow * the automatic mechanisms of TCP to backoff the * flow. Of course, with UDP we're screwed, but this * is expected when a network is heavily loaded. */ (void) ed_nic_inb(sc, ED_P0_TSR); if (isr & ED_ISR_TXE) { u_char tsr; /* * Excessive collisions (16) */ tsr = ed_nic_inb(sc, ED_P0_TSR); if ((tsr & ED_TSR_ABT) && (collisions == 0)) { /* * When collisions total 16, the * P0_NCR will indicate 0, and the * TSR_ABT is set. */ collisions = 16; sc->mibdata.dot3StatsExcessiveCollisions++; sc->mibdata.dot3StatsCollFrequencies[15]++; } if (tsr & ED_TSR_OWC) sc->mibdata.dot3StatsLateCollisions++; if (tsr & ED_TSR_CDH) sc->mibdata.dot3StatsSQETestErrors++; if (tsr & ED_TSR_CRS) sc->mibdata.dot3StatsCarrierSenseErrors++; if (tsr & ED_TSR_FU) sc->mibdata.dot3StatsInternalMacTransmitErrors++; /* * update output errors counter */ ifp->if_oerrors++; } else { /* * Update total number of successfully * transmitted packets. */ ifp->if_opackets++; } /* * reset tx busy and output active flags */ sc->xmit_busy = 0; ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; /* * clear watchdog timer */ sc->tx_timer = 0; /* * Add in total number of collisions on last * transmission. */ ifp->if_collisions += collisions; switch(collisions) { case 0: case 16: break; case 1: sc->mibdata.dot3StatsSingleCollisionFrames++; sc->mibdata.dot3StatsCollFrequencies[0]++; break; default: sc->mibdata.dot3StatsMultipleCollisionFrames++; sc->mibdata. dot3StatsCollFrequencies[collisions-1] ++; break; } /* * Decrement buffer in-use count if not zero (can only * be zero if a transmitter interrupt occured while * not actually transmitting). If data is ready to * transmit, start it transmitting, otherwise defer * until after handling receiver */ if (sc->txb_inuse && --sc->txb_inuse) ed_xmit(sc); } /* * Handle receiver interrupts */ if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) { /* * Overwrite warning. In order to make sure that a * lockup of the local DMA hasn't occurred, we reset * and re-init the NIC. The NSC manual suggests only a * partial reset/re-init is necessary - but some chips * seem to want more. The DMA lockup has been seen * only with early rev chips - Methinks this bug was * fixed in later revs. -DG */ if (isr & ED_ISR_OVW) { ifp->if_ierrors++; #ifdef DIAGNOSTIC log(LOG_WARNING, "%s: warning - receiver ring buffer overrun\n", ifp->if_xname); #endif /* * Stop/reset/re-init NIC */ ed_reset(ifp); } else { /* * Receiver Error. One or more of: CRC error, * frame alignment error FIFO overrun, or * missed packet. */ if (isr & ED_ISR_RXE) { u_char rsr; rsr = ed_nic_inb(sc, ED_P0_RSR); if (rsr & ED_RSR_CRC) sc->mibdata.dot3StatsFCSErrors++; if (rsr & ED_RSR_FAE) sc->mibdata.dot3StatsAlignmentErrors++; if (rsr & ED_RSR_FO) sc->mibdata.dot3StatsInternalMacReceiveErrors++; ifp->if_ierrors++; #ifdef ED_DEBUG if_printf(ifp, "receive error %x\n", ed_nic_inb(sc, ED_P0_RSR)); #endif } /* * Go get the packet(s) XXX - Doing this on an * error is dubious because there shouldn't be * any data to get (we've configured the * interface to not accept packets with * errors). */ /* * Enable 16bit access to shared memory first * on WD/SMC boards. */ ed_enable_16bit_access(sc); ed_rint(sc); ed_disable_16bit_access(sc); } } /* * If it looks like the transmitter can take more data, * attempt to start output on the interface. This is done * after handling the receiver to give the receiver priority. */ if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) ed_start_locked(ifp); /* * return NIC CR to standard state: page 0, remote DMA * complete, start (toggling the TXP bit off, even if was just * set in the transmit routine, is *okay* - it is 'edge' * triggered from low to high) */ ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA); /* * If the Network Talley Counters overflow, read them to reset * them. It appears that old 8390's won't clear the ISR flag * otherwise - resulting in an infinite loop. */ if (isr & ED_ISR_CNT) { (void) ed_nic_inb(sc, ED_P0_CNTR0); (void) ed_nic_inb(sc, ED_P0_CNTR1); (void) ed_nic_inb(sc, ED_P0_CNTR2); } } ED_UNLOCK(sc); }
int ed_probe_RTL80x9(device_t dev, int port_rid, int flags) { struct ed_softc *sc = device_get_softc(dev); char *ts; int error; if ((error = ed_alloc_port(dev, port_rid, ED_NOVELL_IO_PORTS))) return (error); sc->asic_offset = ED_NOVELL_ASIC_OFFSET; sc->nic_offset = ED_NOVELL_NIC_OFFSET; if (ed_nic_inb(sc, ED_P0_CR) & (ED_CR_PS0 | ED_CR_PS1)) ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STP); if (ed_nic_inb(sc, ED_RTL80X9_80X9ID0) != ED_RTL80X9_ID0) return (ENXIO); switch (ed_nic_inb(sc, ED_RTL80X9_80X9ID1)) { case ED_RTL8019_ID1: sc->chip_type = ED_CHIP_TYPE_RTL8019; ts = "RTL8019"; break; case ED_RTL8029_ID1: sc->chip_type = ED_CHIP_TYPE_RTL8029; ts = "RTL8029"; break; default: return (ENXIO); } if ((error = ed_probe_Novell_generic(dev, flags))) return (error); sc->type_str = ts; sc->sc_media_ioctl = &ed_rtl80x9_media_ioctl; ifmedia_init(&sc->ifmedia, 0, ed_rtl_set_media, ed_rtl_get_media); ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 0, 0); ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, 0); ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_2, 0, 0); ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_5, 0, 0); ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, 0); ed_nic_barrier(sc, ED_P0_CR, 1, BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_PAGE_3 | ED_CR_STP); ed_nic_barrier(sc, ED_P0_CR, 1, BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); switch (ed_nic_inb(sc, ED_RTL80X9_CONFIG2) & ED_RTL80X9_CF2_MEDIA) { case ED_RTL80X9_CF2_AUTO: ifmedia_set(&sc->ifmedia, IFM_ETHER | IFM_AUTO); break; case ED_RTL80X9_CF2_10_5: ifmedia_set(&sc->ifmedia, IFM_ETHER | IFM_10_5); break; case ED_RTL80X9_CF2_10_2: ifmedia_set(&sc->ifmedia, IFM_ETHER | IFM_10_2); break; case ED_RTL80X9_CF2_10_T: ifmedia_set(&sc->ifmedia, IFM_ETHER | IFM_10_T | ((ed_nic_inb(sc, ED_RTL80X9_CONFIG3) & ED_RTL80X9_CF3_FUDUP) ? IFM_FDX : 0)); break; } return (0); }
/* * Probe and vendor-specific initialization routine for NE1000/2000 boards */ int ed_probe_Novell_generic(device_t dev, int flags) { struct ed_softc *sc = device_get_softc(dev); u_int memsize; int error; u_char tmp; static char test_pattern[32] = "THIS is A memory TEST pattern"; char test_buffer[32]; /* Reset the board */ if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) { ed_asic_outb(sc, ED_NOVELL_RESET, 0); DELAY(200); } tmp = ed_asic_inb(sc, ED_NOVELL_RESET); /* * I don't know if this is necessary; probably cruft leftover from * Clarkson packet driver code. Doesn't do a thing on the boards I've * tested. -DG */ ed_asic_outb(sc, ED_NOVELL_RESET, tmp); DELAY(5000); /* * This is needed because some NE clones apparently don't reset the * NIC properly (or the NIC chip doesn't reset fully on power-up) XXX * - this makes the probe invasive! ...Done against my better * judgement. -DLG */ ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STP); DELAY(5000); /* Make sure that we really have an 8390 based board */ if (!ed_probe_generic8390(sc)) return (ENXIO); sc->vendor = ED_VENDOR_NOVELL; sc->mem_shared = 0; sc->cr_proto = ED_CR_RD2; /* * Test the ability to read and write to the NIC memory. This has the * side affect of determining if this is an NE1000 or an NE2000. */ /* * This prevents packets from being stored in the NIC memory when the * readmem routine turns on the start bit in the CR. */ ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON); /* Temporarily initialize DCR for byte operations */ ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS); ed_nic_outb(sc, ED_P0_PSTART, 8192 / ED_PAGE_SIZE); ed_nic_outb(sc, ED_P0_PSTOP, 16384 / ED_PAGE_SIZE); /* * Some devices identify themselves. Some of those devices * can't handle being probed, so we allow forcing a mode. If * these flags are set, force it, otherwise probe. */ if (flags & ED_FLAGS_FORCE_8BIT_MODE) { sc->isa16bit = 0; sc->type = ED_TYPE_NE1000; sc->type_str = "NE1000"; } else if (flags & ED_FLAGS_FORCE_16BIT_MODE) { sc->isa16bit = 1; sc->type = ED_TYPE_NE2000; sc->type_str = "NE2000"; ed_nic_outb(sc, ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS); ed_nic_outb(sc, ED_P0_PSTART, 16384 / ED_PAGE_SIZE); ed_nic_outb(sc, ED_P0_PSTOP, 32768 / ED_PAGE_SIZE); } else { /* * Write a test pattern in byte mode. If this fails, then there * probably isn't any memory at 8k - which likely means that the board * is an NE2000. */ ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern)); ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern)); if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) { sc->type = ED_TYPE_NE1000; sc->type_str = "NE1000"; sc->isa16bit = 0; } else { /* Not an NE1000 - try NE2000 */ sc->isa16bit = 1; ed_nic_outb(sc, ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS); ed_nic_outb(sc, ED_P0_PSTART, 16384 / ED_PAGE_SIZE); ed_nic_outb(sc, ED_P0_PSTOP, 32768 / ED_PAGE_SIZE); /* * Write a test pattern in word mode. If this also fails, then * we don't know what this board is. */ ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern)); ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern)); if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) { sc->type = ED_TYPE_NE2000; sc->type_str = "NE2000"; } else { return (ENXIO); } } } sc->chip_type = ED_CHIP_TYPE_DP8390; /* 8k of memory plus an additional 8k if 16bit */ memsize = 8192 + sc->isa16bit * 8192; sc->mem_size = memsize; /* NIC memory doesn't start at zero on an NE board */ /* The start address is tied to the bus width */ sc->mem_start = 8192 + sc->isa16bit * 8192; sc->mem_end = sc->mem_start + memsize; sc->tx_page_start = memsize / ED_PAGE_SIZE; if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) { error = ed_probe_gwether(dev); if (error) return (error); } /* * Use one xmit buffer if < 16k, two buffers otherwise (if not told * otherwise). */ if ((memsize < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING)) sc->txb_cnt = 1; else sc->txb_cnt = 2; sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE; sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE; sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE; /* clear any pending interrupts that might have occurred above */ ed_nic_outb(sc, ED_P0_ISR, 0xff); sc->sc_write_mbufs = ed_pio_write_mbufs; return (0); }