void eeprom_write(uint8_t address, uint8_t *data, uint32_t length){
do{
int writelen = length;
if(length > 16){
writelen = 16;
}
length -= writelen;
eeprom_enable_write();
eeprom_select();
uint8_t header [2] = {0x02, address};
spiSend(&EEPROM_SPI_BUS, 2, header);
spiSend(&EEPROM_SPI_BUS, writelen, data);
eeprom_unselect();
//change where next writecycle writes and from where in the write array
if(length > 0){
address += writelen;
data += writelen;
}
uint8_t status = eeprom_get_status();
while ( status & 0x01){
status = eeprom_get_status();
}
} while(length > 0);
}
@interrupt void PWR_PRESSED_INT(void) {
PM_STATUS pm_status_cur;
if (g_pwrbtn_pressed == 0) {
SetBit (EICR, 2);
ClrBit (EICR, 3);
g_lt2_rtc_count = 0;
g_t_sec = 0;
g_pwrbtn_pressed = 1;
} else {
ClrBit (EICR, 2);
SetBit (EICR, 3);
g_pwrbtn_pressed = 0;
g_t_sec = 0;
pm_status_cur = eeprom_get_status();
if (pm_status_cur == PM_STATUS_POWEROFF) {
if (g_pwrbtn_long_pressed_poweroff != 1) {
g_traped_pm_status = PM_STATUS_POWERON;
} else {
g_pwrbtn_long_pressed_poweroff = 0;
}
} else if (pm_status_cur == PM_STATUS_STR) {
g_traped_pm_status = PM_STATUS_STR_RESUME;
} else if (pm_status_cur == PM_STATUS_STD) {
g_traped_pm_status = PM_STATUS_POWERON;
}
if (g_traped_pm_status != PM_STATUS_NULL) {
Trap;
}
}
}
int eeprom_wait(){
FLASH_Status status = FLASH_BUSY;
/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
Even if the FLASH operation fails, the BUSY flag will be reset and an error
flag will be set */
while(status == FLASH_BUSY)
status = eeprom_get_status();
/* Return the operation status */
return status;
}
void sys_power(PM_STATUS pm_status) {
if (pm_status == eeprom_get_status() || pm_status == eeprom_get_cfg()) {
if (g_traped_boot == 0) {
return;
}
}
switch (pm_status) {
case PM_STATUS_POWERON:
{
unsigned char i, j, k;
for (i = 0; i < 255; i++)
for (j = 0; j < 255; j++)
;
ClrBit (PBDR, 6);
for (i = 0; i < 255; i++)
for (j = 0; j < 255; j++)
;
SetBit (PBDR, 6);
for (i = 0; i < 255; i++)
for (j = 0; j < 255; j++)
;
SetBit (PADR, 4);
SetBit (PADR, 5);
}; break;
case PM_STATUS_POWEROFF:
case PM_STATUS_STD:
{
ClrBit (PADR, 4);
ClrBit (PADR, 5);
}; break;
case PM_STATUS_STR:
{
unsigned char i, j, k;
for (i = 0; i < 255; i++)
for (j = 0; j < 255; j++)
for (k = 0; k < 20; k++)
;
SetBit (PADR, 4);
ClrBit (PADR, 5);
}; break;
case PM_STATUS_STR_RESUME:
{
SetBit (PADR, 4);
SetBit (PADR, 5);
}; break;
default:
break;
}
eeprom_update_status(pm_status);
}
void eeprom_unlock(){
while(eeprom_get_status() == FLASH_BUSY);
if((FLASH->CR & FLASH_CR_LOCK) != RESET){
/* Authorize the FLASH Registers access */
FLASH->KEYR = FLASH_KEY1;
FLASH->KEYR = FLASH_KEY2;
}
/* clear pending flags - important! */
FLASH->SR = (FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |
FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR|FLASH_FLAG_PGSERR);
}
@interrupt void LT2_RTC_INT(void) {
g_lt2_rtc_count++;
LTCSR1;
if (g_pwrbtn_pressed == 1 && g_lt2_rtc_count ==250) {
g_t_sec ++;
g_lt2_rtc_count = 0;
if (g_t_sec == 4 && eeprom_get_status() != PM_STATUS_POWEROFF) {
g_pwrbtn_long_pressed_poweroff = 1;
g_traped_pm_status = PM_STATUS_POWEROFF;
Trap;
}
}
}
void eeprom_tests(){
printf("EEPROM TESTS:\n\r");
printf("\tWrite protection on upper 1/4: " );
eeprom_set_status(0x66);
uint8_t status = eeprom_get_status();
if((status & 0x80) == 0){
printf("Pass\n\r");
}
else{
printf("Fail - 0x%x\n\r", status);
chThdSleepMilliseconds(100);
return;
}
// test if write enable latch is set
printf("\tEnabling write: ");
eeprom_enable_write();
chThdSleepMilliseconds(100);
status = eeprom_get_status();
if(status & 0x02){
printf("Pass\n\r");
}
else{
printf("Fail - 0x%x\n\r", status);
chThdSleepMilliseconds(100);
return;
}
chThdSleepMilliseconds(100);
// test write and read from eeprom
uint32_t testint = 123485;
eeprom_write(0x00, (uint8_t *)&testint, sizeof(uint32_t));
uint32_t verify = 0;
eeprom_read(0x00, (uint8_t *)&verify, sizeof(uint32_t));
printf("\tTesting write: ");
if(verify == testint){
printf("Pass - %i\n\r", verify);
}
else{
printf("Fail - %i\n\r", verify);
}
chThdSleepMilliseconds(100);
//test write larger than 16
static uint8_t testarray[34] = {
[0] = 1,
[1] = 2,
[2] = 3,
[3] = 4,
[4] = 5,
[5] = 6,
[6] = 7,
[7] = 8,
[8] = 9,
[9] = 10,
[10] = 11,
[11] = 12,
[12] = 13,
[13] = 14,
[14] = 15,
[15] = 16,
[16] = 17,
[17] = 18,
[18] = 19,
[19] = 20,
[20] = 21,
[21] = 22,
[22] = 23,
[23] = 24,
[24] = 25,
[25] = 26,
[26] = 27,
[27] = 28,
[28] = 29,
[29] = 30,
[30] = 31,
[31] = 32,
[32] = 33,
[33] = 34,
};
printf("\tWriting and reading back long array:\n\r");
eeprom_write(0x00, testarray, sizeof(testarray) );
static uint8_t verifyarray[sizeof(testarray)];
eeprom_read(0x00, verifyarray, sizeof(testarray));
for(unsigned int i = 0; i < sizeof(testarray); i++)
{
if(testarray[i] == verifyarray[i]) {
printf("\tarray [%i]: pass\n\r", i);
}
else{
printf("\tarray [%i]: fail\n\r", i);
}
}
chThdSleepMilliseconds(100);
}
@interrupt void I2C_INT(void)
{
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
unsigned char SMBS_SR1 = I2CSR1;
unsigned char SMBS_SR2 = I2CSR2;
// stat[statnum][0] = SMBS_SR1;
// stat[statnum++][1] = SMBS_SR2;
if (SMBS_SR2 & BERR) //Check if Bus Error
{
ResetI2C();
return;
}
if (SMBS_SR2 & AF)
{
//EV3-1
STATE = EVT3_1;
I2CDR = 0xFF;
return;
}
//EV1: EVF=1, ADSL=1, cleared by reading SR1 register.
//EV2: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
//EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
//EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading SR1 register. BTF is cleared by releasing the lines
//(STOP=1, STOP=0) or by writing DR register (DR=FFh). If lines are released by STOP=1, STOP=0, the On-chip peripherals subsequent EV4 is not seen.
//EV4: EVF=1, STOPF=1, cleared by reading SR2 register.
if (SMBS_SR1 & EVF == 0)
return;
if (SMBS_SR1 & ADSL)
{
I2CAddress = I2CDR;
STATE = EVT1;
return;
}
if (SMBS_SR1 & BTF)
{
//Next, in 7-bit mode read the DR register to determine from the least significant bit (Data
//Direction Bit) if the slave must enter Receiver or Transmitter mode.
if (I2CAddress & BIT0)
{
//EV3
STATE = EVT3;
//Read OP
//I2CDR = EEPROM[I2COffset];
//I2CDR=eeprom[I2COffset];
if (I2COffset == 0)
{
I2CDR = eeprom_get_status();
}
else if (I2COffset == 1)
{
I2CDR = eeprom_get_cfg();
}
else if (I2COffset == 2)
{
I2CDR = eeprom_get_status_his();
}
else
{
I2CDR = 0xaa;
}
I2COffset++;
}
else
{
//EV2
STATE = EVT2;
if (I2COffset == INVALID_ADDR)
I2COffset = I2CDR;
else
{
//Write OP
//EEPROM[I2COffset] = I2CDR;
g_traped_pm_status = (PM_STATUS)I2CDR;
Trap;
//eeprom[I2COffset] = I2CDR;
//I2COffset++;
}
}
}
else if (SMBS_SR2 & STOPF)
{
//EV4
STATE = EVT_NONE;
I2COffset = INVALID_ADDR;
}
else
{
ResetI2C();
}
return;
}
int eeprom_read_block(uint32_t address, void* data, uint32_t size){
while(eeprom_get_status() == FLASH_BUSY);
memcpy(data, (const void*)address, size);
return eeprom_get_status();
}
uint8_t eeprom_read_byte(uint32_t address){
while(eeprom_get_status() == FLASH_BUSY);
return *(uint8_t*)address;
}
void eeprom_lock(){
while(eeprom_get_status() == FLASH_BUSY);
/* Set the LOCK Bit to lock the FLASH Registers access */
FLASH->CR |= FLASH_CR_LOCK;
}
