DPI_STATUS DPI_Init_PLL(unsigned int mipi_pll_clk_ref,unsigned int mipi_pll_clk_div1,unsigned int mipi_pll_clk_div2)
{
#if 1
MIPITX_CFG0_REG con0 = DSI_PHY_REG_DPI->MIPITX_CON0;
MIPITX_CFG1_REG con1 = DSI_PHY_REG_DPI->MIPITX_CON1;
#ifdef DPI_MIPI_API
enable_mipi(MT65XX_MIPI_TX, "DPI");
#endif
#ifdef BUILD_UBOOT
OUTREG16(0xc2080858, 0x8000);
OUTREG16(0xc20a3824, 0x4008);
MASKREG16(0xc20a380c, 0x000c, 0x0000); //default value is 0x7008, but should be 0x7000
#else
OUTREG16(0xf2080858, 0x8000); //??
OUTREG16(0xf20a3824, 0x4008);
MASKREG16(0xf20a380c, 0x000c, 0x0000); //default value is 0x7008, but should be 0x7000
#endif
MASKREG16(PLL_SOURCE, 0x0010, 0x0010); //
con1.RG_PLL_DIV1 = mipi_pll_clk_div1;
con1.RG_PLL_DIV2 = mipi_pll_clk_div2;
con0.PLL_CLKR_EN = 1;
con0.PLL_EN = 1;
con0.RG_DPI_EN = 1;
// Set to DSI_PHY_REG
OUTREG32(&DSI_PHY_REG_DPI->MIPITX_CON0, AS_UINT32(&con0));
OUTREG32(&DSI_PHY_REG_DPI->MIPITX_CON1, AS_UINT32(&con1));
#endif
return DPI_STATUS_OK;
}
void DSI_PHY_clk_switch(bool on)
{
if(on)
{
#ifdef DSI_MIPI_API
enable_mipi(MT65XX_MIPI_TX, "DSI");
#endif
mipitx_con0.PLL_EN=1;
DSI_PHY_REG->MIPITX_CON0=mipitx_con0;
}
else
{
mipitx_con0=DSI_PHY_REG->MIPITX_CON0;
mipitx_con1=DSI_PHY_REG->MIPITX_CON1;
mipitx_con3=DSI_PHY_REG->MIPITX_CON3;
mipitx_con6=DSI_PHY_REG->MIPITX_CON6;
mipitx_con8=DSI_PHY_REG->MIPITX_CON8;
mipitx_con9=DSI_PHY_REG->MIPITX_CON9;
#ifdef DSI_MIPI_API
disable_mipi(MT65XX_MIPI_TX, "DSI");
#else
OUTREG32(&DSI_PHY_REG->MIPITX_CON0, 0);
OUTREG32(&DSI_PHY_REG->MIPITX_CON6, 0);
OUTREG32(&DSI_PHY_REG->MIPITX_CON9, 0);
#endif
}
}
DPI_STATUS DPI_Init_PLL(unsigned int mipi_pll_clk_ref,unsigned int mipi_pll_clk_div1,unsigned int mipi_pll_clk_div2)
{
unsigned int reg_value = 0;
#if 0
MIPITX_CFG0_REG con0 = DSI_PHY_REG_DPI->MIPITX_CON0;
MIPITX_CFG1_REG con1 = DSI_PHY_REG_DPI->MIPITX_CON1;
#ifdef DPI_MIPI_API
enable_mipi(MT65XX_MIPI_TX, "DPI");
#endif
#ifdef BUILD_UBOOT
OUTREG16(0xc2080858, 0x8000);
OUTREG16(0xc20a3824, 0x4008);
MASKREG16(0xc20a380c, 0x000c, 0x0000); //default value is 0x7008, but should be 0x7000
#else
OUTREG16(0xf2080858, 0x8000); //??
OUTREG16(0xf20a3824, 0x4008);
MASKREG16(0xf20a380c, 0x000c, 0x0000); //default value is 0x7008, but should be 0x7000
MASKREG16(PLL_SOURCE, 0x0010, 0x0010); //
#endif
con1.RG_PLL_DIV1 = mipi_pll_clk_div1;
con1.RG_PLL_DIV2 = mipi_pll_clk_div2;
con0.PLL_CLKR_EN = 1;
con0.PLL_EN = 1;
con0.RG_DPI_EN = 1;
// Set to DSI_PHY_REG
OUTREG32(&DSI_PHY_REG_DPI->MIPITX_CON0, AS_UINT32(&con0));
OUTREG32(&DSI_PHY_REG_DPI->MIPITX_CON1, AS_UINT32(&con1));
#else
//#ifndef BUILD_UBOOT
#if 0
OUTREG32(DISPSYS_BASE + 0x34, 0x02);//set RDMA0 to DPI
#if 0
//CG
OUTREG32(DISPSYS_BASE + 0x104, 0xffffffff);//set CG
OUTREG32(DISPSYS_BASE + 0x108, 0xffffffff);
OUTREG32(DISPSYS_BASE + 0x114, 0xffffffff);
OUTREG32(DISPSYS_BASE + 0x118, 0xffffffff);
#endif
OUTREG32(DISP_MUTEX_BASE + 0x28, 0x01);//reset mutex
OUTREG32(DISP_MUTEX_BASE + 0x28, 0);
OUTREG32(DISP_MUTEX_BASE + 0x2c, 0x80); //rdma0 is in the mutex
OUTREG32(DISP_MUTEX_BASE + 0x30, 0x2); //dpi0 is the dst
OUTREG32(DISP_MUTEX_BASE + 0x24, 0x1); //lock mutex0
OUTREG32(DISP_MUTEX_BASE + 0, 0x1); //lock mutex0
// OUTREG32(MUTEX_BASE + 0x4, 0x1); //lock mutex0
while((INREG32(DISP_MUTEX_BASE + 0x24)&0x02)!=0x02){} // polling until mutex lock complete
OUTREG32(DISPSYS_BASE + 0xC08, 0x01);//select DPI pin
OUTREG32(DISPSYS_BASE + 0x60, 0x8);// DPI src clock
//RDMA0 setting
OUTREG32(RDMA0_BASE + 0x10, 0); //stop rdma0
// width, height and format
OUTREG32(RDMA0_BASE + 0x14, lcm_params->width);
OUTREG32(RDMA0_BASE + 0x18, lcm_params->height);
OUTREG32(RDMA0_BASE + 0x24, 0x40);//input format ARGB888
#ifndef BUILD_UBOOT
OUTREG32(RDMA0_BASE + 0x28, FB_Addr);//input addr
#else
OUTREG32(RDMA0_BASE + 0x28, mt65xx_get_fb_addr());//input addr
#endif
OUTREG32(RDMA0_BASE + 0x2C, lcm_params->width*2);//input pitch
OUTREG32(RDMA0_BASE + 0x30, 0x10101010);
OUTREG32(RDMA0_BASE + 0x40, 0x80f00008);
OUTREG32(RDMA0_BASE + 0x50, 0);
OUTREG32(RDMA0_BASE + 0x54, 0);
OUTREG32(RDMA0_BASE + 0x58, 0);
OUTREG32(RDMA0_BASE + 0x5C, 0);
OUTREG32(RDMA0_BASE + 0x60, 0);
OUTREG32(RDMA0_BASE + 0x64, 0);
OUTREG32(RDMA0_BASE + 0x68, 0);
OUTREG32(RDMA0_BASE + 0x6C, 0);
OUTREG32(RDMA0_BASE + 0x70, 0);
OUTREG32(RDMA0_BASE + 0x74, 0);
OUTREG32(RDMA0_BASE + 0x78, 0);
OUTREG32(RDMA0_BASE + 0x7C, 0);
OUTREG32(RDMA0_BASE + 0x80, 0);
OUTREG32(RDMA0_BASE + 0x84, 0);
OUTREG32(RDMA0_BASE + 0x88, 0);
OUTREG32(RDMA0_BASE + 0x8C, 0);
//start rdma
OUTREG32(RDMA0_BASE + 0x10, 0x03); //start + memory mode
// dump register
//release mutex0
// OUTREG32(MUTEX_BASE + 0x24, 0);
// while((INREG32(MUTEX_BASE + 0x24)&&0x02)!=0){} // polling until mutex lock complete
#endif
#endif
return DPI_STATUS_OK;
}
