void enc_init() {
enc_spi_init();
/* reset */
enc_op_write(ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
_delay_us(80);
/* wait for reset to complete
* XXX is this reliable enough in case of total communication failure?
*/
while (!(enc_reg_read(ESTAT) & ESTAT_CLKRDY)) { }
/* Bank 0 stuff
* Ethernet buffer addresses
*/
packet_next = RXST;
enc_reg_write16(ERXSTL, RXST);
enc_reg_write16(ERXNDL, RXND);
enc_reg_write16(ERXRDPTL, RXND);
/* Bank 2 stuff
* setup MAC, automatic padding, auto CRC
*/
enc_reg_write(MACON1, MACON1_MARXEN|MACON1_TXPAUS|MACON1_RXPAUS);
enc_reg_write(MACON2, 0x00);
enc_op_write(ENC28J60_BIT_FIELD_SET, MACON3, MACON3_PADCFG0 | MACON3_TXCRCEN | MACON3_FRMLNEN);
/* inter-frame gap non-B2B, B2B, maximum packet size */
enc_reg_write16(MAIPGL, 0x0c12);
enc_reg_write(MABBIPG, 0x12);
enc_reg_write16(MAMXFLL, MAX_FRAMELEN);
/* Bank 3 stuff
* MAC address for Unicast packet filtering
*/
enc_reg_write(MAADR5, our_mac[0]);
enc_reg_write(MAADR4, our_mac[1]);
enc_reg_write(MAADR3, our_mac[2]);
enc_reg_write(MAADR2, our_mac[3]);
enc_reg_write(MAADR1, our_mac[4]);
enc_reg_write(MAADR0, our_mac[5]);
/* no loopback of transmitted frames */
enc_phy_write(PHCON2, PHCON2_HDLDIS);
/* Enable interrupts and enable packet reception */
enc_op_write(ENC28J60_BIT_FIELD_SET, EIE, EIE_INTIE|EIE_PKTIE);
enc_op_write(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
/* LEDs
* A: Link status + receive
* B: Transmit
* long stretched
*/
enc_phy_write(PHLCON, 0xc1a);
}
/**
* Initialize the ENC28J60 with the given MAC-address
*/
void enc_init(const uint8_t *mac) {
enc_next_packet = 0x000;
//MAP_GPIOPinWrite(ENC_RESET_PORT, ENC_RESET, ENC_RESET);
enc_reset();
uint8_t reg;
do {
reg = READ_REG(ENC_ESTAT);
delayMs(200);
printf("ENC_ESTAT: %x\n", reg);
} while ((reg & ENC_ESTAT_CLKRDY) == 0);
enc_switch_bank(0);
printf("Econ: %x\n", READ_REG(ENC_ECON1));
#if 1
printf("Silicon Revision: %d\n", READ_REG(ENC_EREVID));
#endif
//SET_REG_BITS(ENC_ECON1, ENC_ECON1_TXRST | ENC_ECON1_RXRST);
SET_REG_BITS(ENC_ECON1, ENC_ECON1_TXRST);
CLEAR_REG_BITS(ENC_ECON1, ENC_ECON1_RXEN);
SET_REG_BITS(ENC_ECON2, ENC_ECON2_AUTOINC);
enc_set_rx_area(0x000, RX_END);
uint16_t phyreg = enc_phy_read(ENC_PHSTAT2);
phyreg &= ~ENC_PHSTAT2_DPXSTAT;
enc_phy_write(ENC_PHSTAT2, phyreg);
phyreg = enc_phy_read(ENC_PHCON1);
phyreg &= ~ENC_PHCON_PDPXMD;
enc_phy_write(ENC_PHCON1, phyreg);
/* Setup receive filter to receive
* broadcast, multicast and unicast to the given MAC */
enc_set_mac_addr(mac);
WRITE_REG(
ENC_ERXFCON,
ENC_ERXFCON_UCEN | ENC_ERXFCON_CRCEN |ENC_ERXFCON_MCEN | ENC_ERXFCON_BCEN);
/* Initialize MAC */
WRITE_REG(ENC_MACON1,
ENC_MACON1_TXPAUS | ENC_MACON1_RXPAUS | ENC_MACON1_MARXEN);
WRITE_REG(
ENC_MACON3,
(0x1 << ENC_MACON3_PADCFG_SHIFT) | ENC_MACON3_TXRCEN |
/*ENC_MACON3_FULDPX |*/ENC_MACON3_FRMLNEN);
WRITE_REG(ENC_MAMXFLL, 1518 & 0xFF);
WRITE_REG(ENC_MAMXFLH, (1518 >> 8) & 0xFF);
WRITE_REG(ENC_MABBIPG, 0x12);
WRITE_REG(ENC_MAIPGL, 0x12);
WRITE_REG(ENC_MAIPGH, 0x0C);
SET_REG_BITS(ENC_EIE, ENC_EIE_INTIE | ENC_EIE_PKTIE);
CLEAR_REG_BITS(ENC_ECON1, ENC_ECON1_TXRST | ENC_ECON1_RXRST);
SET_REG_BITS(ENC_ECON1, ENC_ECON1_RXEN);
}
