static void enx_sdram_ctrl_init(void)
{
enx_reg_32(SCSC) = 0x00000000; // Set sd-ram start address
enx_reg_set(RSTR0, SDCT, 0); // Get sd-ram controller out of reset state
enx_reg_32(MC) = 0x00001011; // Write memory configuration
//enx_reg_32n(0x88) |= 0x3E << 4; <- Mhhhh????
}
void avia_gt_enx_init(void)
{
printk("avia_gt_enx: $Id: avia_gt_enx.c,v 1.13 2002/09/02 19:25:37 Jolt Exp $\n");
gt_info = avia_gt_get_info();
if (!avia_gt_chip(ENX)) {
printk("avia_gt_enx: Unsupported chip type\n");
return;
}
enx_reset();
enx_sdram_ctrl_init();
enx_dac_init();
enx_video_init();
enx_irq_enable();
memset(gt_info->mem_addr, 0xF, 1024 * 1024 /*ENX_MEM_SIZE*/);
//bring out of reset state
enx_reg_32(RSTR0) &= ~(1 << 27); // AV - Decoder
enx_reg_32(RSTR0) &= ~(1 << 13); // Queue Manager
enx_reg_32(RSTR0) &= ~(1 << 6); // Blitter / Color expander
enx_reg_32(CFGR0) &= ~(1 << 1); // disable clip mode audio
enx_reg_32(CFGR0) &= ~(1 << 0); // disable clip mode video
}
void enx_irq_enable(void)
{
enx_reg_32(EHIDR) = 0x00000000; // IRQs an Hostprozessor weiterreichen
enx_reg_32(IPR4) = 0x55555555; // alles auf HIRQ0
enx_reg_32(IPR5) = 0x55555555; // das auch noch
enx_reg_16(ISR0) = 0xFFFE; // Clear all irq states
enx_reg_16(ISR1) = 0xFFFE; // Clear all irq states
enx_reg_16(ISR2) = 0xFFFE; // Clear all irq states
enx_reg_16(ISR3) = 0xFFFE; // Clear all irq states
enx_reg_16(ISR4) = 0xFFFE; // Clear all irq states
enx_reg_16(ISR5) = 0xFFFE; // Clear all irq states
enx_reg_16(IMR0) = 0x0001; // mask all IRQ's (=disable them)
enx_reg_16(IMR1) = 0x0001;
enx_reg_16(IMR2) = 0x0001;
enx_reg_16(IMR3) = 0x0001;
enx_reg_16(IMR4) = 0x0001;
enx_reg_16(IMR5) = 0x0001;
enx_reg_32(IDR) = 0x00000000;
}
static void enx_reset(void)
{
enx_reg_32(RSTR0) = 0xFCF6BEFF; // Reset all modules
}
