void ETH_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
if (ETH_GetITStatus(ETH_INT_TX_COMPLETE_FRAME))
{
rt_sem_release(&cme_eth_device.tx_buf_free);
ETH_ClearITPendingBit(ETH_INT_TX_COMPLETE_FRAME);
}
if (ETH_GetITStatus(ETH_INT_RX_STOP))
{
CME_ETH_PRINTF("ETH_INT_RX_STOP\n");
ETH_ClearITPendingBit(ETH_INT_RX_STOP);
}
if ((ETH_GetITStatus(ETH_INT_RX_BUF_UNAVAI)) ||
(ETH_GetITStatus(ETH_INT_RX_COMPLETE_FRAME)))
{
/* a frame has been received */
eth_device_ready(&(cme_eth_device.parent));
ETH_ITConfig(ETH_INT_RX_COMPLETE_FRAME, FALSE);
ETH_ITConfig(ETH_INT_RX_BUF_UNAVAI, FALSE);
ETH_ClearITPendingBit(ETH_INT_RX_BUF_UNAVAI);
ETH_ClearITPendingBit(ETH_INT_RX_COMPLETE_FRAME);
}
/* leave interrupt */
rt_interrupt_leave();
}
/*********************************************************************************************************
** 函数名称: nic_isr_handler
** 函数名称: nic_isr_handler
**
** 功能描述： interrupt service routine
**
** 输 入: int vector
**
** 输 出: void
**
** 全局变量:
** 调用模块: 无
**
** 作 者: LiJin
** 日 期: 2009年8月11日
** 备 注:
**-------------------------------------------------------------------------------------------------------
** 修改人:
** 日 期:
** 备 注:
**------------------------------------------------------------------------------------------------------
********************************************************************************************************/
void nic_isr_handler( int vector )
{
rt_uint32_t status = (MAC_INTSTATUS & MAC_INTENABLE);
if (status & INT_RX_DONE) // if receive packet
{
rt_err_t result;
MAC_INTCLEAR = status;
/* a frame has been received */
result = eth_device_ready(&(lpc24xx_device.parent));
RT_ASSERT(result == RT_EOK);
// MAC_INTCLEAR = (INT_RX_DONE); /* Clear the interrupt flags */
}
if ((status & (INT_RX_OVERRUN)) > 0)
{ /* If a fator Overrun error has occured */
MAC_INTCLEAR = (INT_RX_OVERRUN); /* Clear the overrun interrupt flag */
MAC_COMMAND |= CR_RX_RES; /* Soft reset the Rx datapath, this disables the receiver */
MAC_COMMAND |= CR_RX_EN; /* Re-enable the reciever */
MAC_MAC1 |= MAC1_REC_EN; /* Re-enable the reciever */
}
//???????????
VICVectAddr = 0; //interrupt close 通知中断控制器中断结束
}
/* interrupt service routine */
void rt_dm9000_isr()
{
rt_uint16_t int_status;
rt_uint16_t last_io;
last_io = DM9000_IO;
/* Disable all interrupts */
// dm9000_io_write(DM9000_IMR, IMR_PAR);
/* Got DM9000 interrupt status */
int_status = dm9000_io_read(DM9000_ISR); /* Got ISR */
dm9000_io_write(DM9000_ISR, int_status); /* Clear ISR status */
DM9000_TRACE("dm9000 isr: int status %04x\n", int_status);
/* receive overflow */
if (int_status & ISR_ROS)
{
rt_kprintf("overflow\n");
}
if (int_status & ISR_ROOS)
{
rt_kprintf("overflow counter overflow\n");
}
/* Received the coming packet */
if (int_status & ISR_PRS)
{
/* disable receive interrupt */
dm9000_io_write(DM9000_IMR, IMR_PAR);
dm9000_device.imr_all = IMR_PAR | IMR_PTM;
dm9000_io_write(DM9000_IMR, dm9000_device.imr_all);
/* a frame has been received */
eth_device_ready(&(dm9000_device.parent));
}
/* Transmit Interrupt check */
if (int_status & ISR_PTS)
{
/* transmit done */
int tx_status = dm9000_io_read(DM9000_NSR); /* Got TX status */
if (tx_status & (NSR_TX2END | NSR_TX1END))
{
dm9000_device.packet_cnt --;
if (dm9000_device.packet_cnt > 0)
{
DM9000_TRACE("dm9000 isr: tx second packet\n");
/* transmit packet II */
/* Set TX length to DM9000 */
dm9000_io_write(DM9000_TXPLL, dm9000_device.queue_packet_len & 0xff);
dm9000_io_write(DM9000_TXPLH, (dm9000_device.queue_packet_len >> 8) & 0xff);
/* Issue TX polling command */
dm9000_io_write(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
}
/* interrupt service routine */
void ETH_IRQHandler(void)
{
rt_uint32_t status;
status = ETH->DMASR;
/* Frame received */
if ( ETH_GetDMAFlagStatus(ETH_DMA_FLAG_R) == SET)
{
rt_err_t result;
//rt_kprintf("Frame comming\n");
/* Clear the interrupt flags. */
/* Clear the Eth DMA Rx IT pending bits */
ETH_DMAClearITPendingBit(ETH_DMA_IT_R);
/* a frame has been received */
result = eth_device_ready(&(stm32_eth_device.parent));
if( result != RT_EOK ) rt_kprintf("RX err =%d\n", result );
//RT_ASSERT(result == RT_EOK);
}
if (ETH_GetDMAITStatus(ETH_DMA_IT_T) == SET) /* packet transmission */
{
ETH_DMAClearITPendingBit(ETH_DMA_IT_T);
}
ETH_DMAClearITPendingBit(ETH_DMA_IT_NIS);
//
}
static void pcap_thread_entry(void* parameter)
{
pcap_if_t *netif;
pcap_t *tap;
char errbuf[PCAP_ERRBUF_SIZE];
struct pcap_pkthdr *header;
const u_char *pkt_data;
int res;
netif = (pcap_if_t *) parameter;
/* Open the adapter */
if ((tap = pcap_open_live(netif->name,
65536, // portion of the packet to capture.
1, // promiscuous mode (nonzero means promiscuous)
1, // read timeout, 0 blocked, -1 no timeout
errbuf )) == NULL)
{
rt_kprintf("Unable to open the adapter. %s is not supported by WinPcap\n", netif->name);
return;
}
NETIF_PCAP(&pcap_netif_device) = tap;
/* Read the packets */
while (1)
{
struct eth_device* eth;
struct pbuf *p;
rt_enter_critical();
res = pcap_next_ex(tap, &header, &pkt_data);
rt_exit_critical();
if (res == 0) continue;
eth = (struct eth_device*) &pcap_netif_device;
p = pbuf_alloc(PBUF_LINK, header->len, PBUF_RAM);
pbuf_take(p, pkt_data, header->len);
/* send to packet mailbox */
rt_mb_send_wait(packet_mb, (rt_uint32_t)p, RT_WAITING_FOREVER);
/* notify eth rx thread to receive packet */
eth_device_ready(eth);
}
}
void ENET_IRQHandler(void)
{
rt_uint32_t status;
/* enter interrupt */
rt_interrupt_enter();
status = LPC_EMAC->IntStatus;
if (status & INT_RX_DONE)
{
/* Disable EMAC RxDone interrupts. */
LPC_EMAC->IntEnable = INT_TX_DONE;
/* a frame has been received */
eth_device_ready(&(lpc17xx_emac_device.parent));
}
else if (status & INT_TX_DONE)
{
/* set event */
rt_event_send(&tx_event, 0x01);
}
if (status & INT_RX_OVERRUN)
{
rt_kprintf("rx overrun\n");
}
if (status & INT_TX_UNDERRUN)
{
rt_kprintf("tx underrun\n");
}
if (status & INT_SOFT_INT){
rt_kprintf("!!!!!!!!!!!!!!eth soft int\n");
}
if(status & INT_WAKEUP){
rt_kprintf("!!!!!!!!!!!!!1eth wakeup\n");
}
/* Clear the interrupt. */
LPC_EMAC->IntClear = status;
/* leave interrupt */
rt_interrupt_leave();
}
/* interrupt service routine */
void rt_dm9000_isr(int irqno)
{
rt_uint32_t status;
if (status) // if receive packet
{
rt_err_t result;
/* a frame has been received */
result = eth_device_ready(&(dm9000_device.parent));
RT_ASSERT(result == RT_EOK);
}
if (status) // if finished packet transmission
{
}
}
/* interrupt service routine */
void rt_dm9161_isr(int irqno)
{
unsigned long intstatus;
rt_uint32_t address;
mask_irq(INTSRC_MAC);
intstatus = sep_emac_read(MAC_INTSRC);
sep_emac_write(MAC_INTSRC,intstatus);
/*Receive complete*/
if(intstatus & 0x04)
{
eth_device_ready(&(dm9161_device.parent));
}
/*Receive error*/
else if(intstatus & 0x08)
{
rt_kprintf("Receive error\n");
}
/*Transmit complete*/
else if(intstatus & 0x03)
{
if(dm9161_device.tx_index == 0)
address = (MAC_TX_BD +(MAX_TX_DESCR-2)*8);
else if(dm9161_device.tx_index == 1)
address = (MAC_TX_BD +(MAX_TX_DESCR-1)*8);
else
address = (MAC_TX_BD + dm9161_device.tx_index*8-16);
//printk("free tx skb 0x%x in inter!!\n",lp->txBuffIndex);
sep_emac_write(address,0x0);
}
else if (intstatus & 0x10)
{
rt_kprintf("ROVER ERROR\n");
}
while(intstatus)
{
sep_emac_write(MAC_INTSRC,intstatus);
intstatus = sep_emac_read(MAC_INTSRC);
}
unmask_irq(INTSRC_MAC);
}
/* interrupt service routine */
void nic_isr_handler(int irqno)
{
rt_uint32_t status = MAC_INTSTATUS;
rt_uint32_t nRsv = MAC_RSV;
rt_uint32_t nSta = MAC_STATUS;
if (status & INT_RX_DONE) // if receive packet
{
rt_uint8_t result;
MAC_INTCLEAR = status;
/* a frame has been received */
result = eth_device_ready(&(lpc24xx_device.parent));
RT_ASSERT(result == RT_EOK);
if (result != RT_EOK)
{//如果发送失败,那么说明队列满了,处理不过来,那么就把这封信扔掉
rxpkt_discard();
}
MAC_INTCLEAR = (INT_RX_DONE); /* Clear the interrupt flags */
}
/* check for receive overrun */
if (status & INT_RX_OVERRUN)
{
MAC_INTCLEAR = INT_RX_OVERRUN;
// eth->rx_overrun++;
MAC_COMMAND |= CR_RX_RES;
/* usleep(?); */
MAC_COMMAND |= CR_RX_EN;
MAC_MAC1 |= MAC1_REC_EN;
}
/* check for transmit underrun */
if (status & INT_TX_UNDERRUN)
{
MAC_INTCLEAR = INT_TX_UNDERRUN;
// eth->tx_underrun++;
MAC_COMMAND |= CR_TX_RES;;
/* usleep(?); */
MAC_COMMAND |= CR_TX_EN;
}
//???????????
VICVectAddr = 0; //interrupt close 通知中断控制器中断结束
}
void rt_skeleton_isr(int irqno)
{
rt_uint32_t status;
/* read status */
/* Received the coming packet */
if (status)
{
/* disable receive interrupt */
/* a frame has been received */
eth_device_ready(&(_skeleton_device.parent));
}
/* Transmit Interrupt check */
if (status)
{
}
}
void luminaryif_isr(void)
{
unsigned long ulTemp;
//
// Read and Clear the interrupt.
//
ulTemp = EthernetIntStatus(ETH_BASE, false);
EthernetIntClear(ETH_BASE, ulTemp);
//
// Check to see if an RX Interrupt has occured.
//
if(ulTemp & ETH_INT_RX)
{
//
// Indicate that a packet has been received.
//
rt_err_t result;
/* a frame has been received */
result = eth_device_ready((struct eth_device*)&(luminaryif_dev->parent));
if(result != RT_EOK) rt_set_errno(-RT_ERROR);
//
// Disable Ethernet RX Interrupt.
//
EthernetIntDisable(ETH_BASE, ETH_INT_RX);
}
if(ulTemp & ETH_INT_TX)
{
/* A frame has been transmitted. */
rt_sem_release(&tx_sem);
}
}
void eth_rx_irq(int irqno,void *param)
{
struct rt_eth_dev *dev = ð_dev;
struct synopGMACNetworkAdapter *adapter = dev->priv;
//DEBUG_MES("in irq!!\n");
#ifdef RT_USING_GMAC_INT_MODE
int i ;
for(i = 0; i < 7200; i++)
;
#endif /*RT_USING_GMAC_INT_MODE*/
synopGMACdevice * gmacdev = (synopGMACdevice *)adapter->synopGMACdev;
u32 interrupt,dma_status_reg;
s32 status;
u32 dma_addr;
//rt_kprintf("irq i = %d\n", i++);
dma_status_reg = synopGMACReadReg(gmacdev->DmaBase, DmaStatus);
if(dma_status_reg == 0)
{
rt_kprintf("dma_status ==0 \n");
return;
}
//rt_kprintf("dma_status_reg is 0x%x\n", dma_status_reg);
u32 gmacstatus;
synopGMAC_disable_interrupt_all(gmacdev);
gmacstatus = synopGMACReadReg(gmacdev->MacBase,GmacStatus);
if(dma_status_reg & GmacPmtIntr){
rt_kprintf("%s:: Interrupt due to PMT module\n",__FUNCTION__);
//synopGMAC_linux_powerup_mac(gmacdev);
}
if(dma_status_reg & GmacMmcIntr){
rt_kprintf("%s:: Interrupt due to MMC module\n",__FUNCTION__);
DEBUG_MES("%s:: synopGMAC_rx_int_status = %08x\n",__FUNCTION__,synopGMAC_read_mmc_rx_int_status(gmacdev));
DEBUG_MES("%s:: synopGMAC_tx_int_status = %08x\n",__FUNCTION__,synopGMAC_read_mmc_tx_int_status(gmacdev));
}
if(dma_status_reg & GmacLineIntfIntr){
rt_kprintf("%s:: Interrupt due to GMAC LINE module\n",__FUNCTION__);
}
interrupt = synopGMAC_get_interrupt_type(gmacdev);
//rt_kprintf("%s:Interrupts to be handled: 0x%08x\n",__FUNCTION__,interrupt);
if(interrupt & synopGMACDmaError){
u8 mac_addr0[6];
rt_kprintf("%s::Fatal Bus Error Inetrrupt Seen\n",__FUNCTION__);
memcpy(mac_addr0,dev->dev_addr,6);
synopGMAC_disable_dma_tx(gmacdev);
synopGMAC_disable_dma_rx(gmacdev);
synopGMAC_take_desc_ownership_tx(gmacdev);
synopGMAC_take_desc_ownership_rx(gmacdev);
synopGMAC_init_tx_rx_desc_queue(gmacdev);
synopGMAC_reset(gmacdev);
synopGMAC_set_mac_addr(gmacdev,GmacAddr0High,GmacAddr0Low, mac_addr0);
synopGMAC_dma_bus_mode_init(gmacdev,DmaFixedBurstEnable| DmaBurstLength8 | DmaDescriptorSkip2 );
synopGMAC_dma_control_init(gmacdev,DmaStoreAndForward);
synopGMAC_init_rx_desc_base(gmacdev);
synopGMAC_init_tx_desc_base(gmacdev);
synopGMAC_mac_init(gmacdev);
synopGMAC_enable_dma_rx(gmacdev);
synopGMAC_enable_dma_tx(gmacdev);
}
if(interrupt & synopGMACDmaRxNormal){
//DEBUG_MES("%s:: Rx Normal \n", __FUNCTION__);
//synop_handle_received_data(netdev);
eth_device_ready(ð_dev.parent);
}
if(interrupt & synopGMACDmaRxAbnormal){
//rt_kprintf("%s::Abnormal Rx Interrupt Seen\n",__FUNCTION__);
if(GMAC_Power_down == 0){
adapter->synopGMACNetStats.rx_over_errors++;
synopGMACWriteReg(gmacdev->DmaBase, DmaStatus ,0x80);
synopGMAC_resume_dma_rx(gmacdev);
}
}
if(interrupt & synopGMACDmaRxStopped){
rt_kprintf("%s::Receiver stopped seeing Rx interrupts\n",__FUNCTION__); //Receiver gone in to stopped state
}
if(interrupt & synopGMACDmaTxNormal){
DEBUG_MES("%s::Finished Normal Transmission \n",__FUNCTION__);
// synop_handle_transmit_over(netdev);
}
if(interrupt & synopGMACDmaTxAbnormal){
rt_kprintf("%s::Abnormal Tx Interrupt Seen\n",__FUNCTION__);
}
if(interrupt & synopGMACDmaTxStopped){
TR("%s::Transmitter stopped sending the packets\n",__FUNCTION__);
if(GMAC_Power_down == 0){ // If Mac is not in powerdown
synopGMAC_disable_dma_tx(gmacdev);
synopGMAC_take_desc_ownership_tx(gmacdev);
synopGMAC_enable_dma_tx(gmacdev);
// netif_wake_queue(netdev);
TR("%s::Transmission Resumed\n",__FUNCTION__);
}
}
/* Enable the interrrupt before returning from ISR*/
synopGMAC_enable_interrupt(gmacdev,DmaIntEnable);
return;
}