Beispiel #1
0
static NyLPC_TBool start(const struct NyLPC_TEthAddr* i_eth_addr,NyLPC_TiEthernetDevice_onEvent i_handler,void* i_param)
{
	int i;
	//ISRw割り込み設定
	NyLPC_cIsr_setEnetISR(emacIsrHandler);
	_event_handler=i_handler;
	_event_param=i_param;
	/* Set the Ethernet MAC Address registers */
	LPC_EMAC->SA0 = (((uint32_t)(i_eth_addr->addr[0])) << 8 ) | i_eth_addr->addr[1];
	LPC_EMAC->SA1 = (((uint32_t)(i_eth_addr->addr[2])) << 8 ) | i_eth_addr->addr[3];
	LPC_EMAC->SA2 = (((uint32_t)(i_eth_addr->addr[4])) << 8 ) | i_eth_addr->addr[5];

	//TXメモリマネージャの準備
	NyLPC_cEthernetMM_initialize(ETH_TX_BUF_BASE);
	/* Initialize Tx and Rx DMA Descriptors */
	prevRxDescriptor();
	prevTxDescriptor();
	//wait for link up 
	for(i=0;i<5;i++){
		if(ethernet_link()!=0){
			break;
		}
		NyLPC_cThread_sleep(emacWAIT_FOR_LINK_TO_ESTABLISH_MS);
	}

	//setup Link
	ethernet_set_link(-1, 0);

	LPC_EMAC->RxFilterCtrl = RFC_UCAST_EN | RFC_MCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;
	/* Receive Broadcast, Perfect Match Packets */

	//Ethernetの割込み開始設定
	NyLPC_cIsr_enterCritical();
	{
		LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE; /* Enable EMAC interrupts. */
		LPC_EMAC->IntClear = 0xFFFF; /* Reset all interrupts */
	  
		LPC_EMAC->Command |= (CR_RX_EN | CR_TX_EN); /* Enable receive and transmit mode of MAC Ethernet core */
		LPC_EMAC->MAC1 |= MAC1_REC_EN;

        NVIC_SetPriority( ENET_IRQn, configEMAC_INTERRUPT_PRIORITY );
        NVIC_EnableIRQ( ENET_IRQn );
	}
	NyLPC_cIsr_exitCritical();

	return NyLPC_TBool_TRUE;
}
Beispiel #2
0
/*----------------------------------------------------------------------------
  Ethernet Device initialize
 *----------------------------------------------------------------------------*/
int ethernet_init() {
  int regv, tout;
  char mac[ETHERNET_ADDR_SIZE];
  unsigned int clock = clockselect();
  
  LPC_SC->PCONP |= 0x40000000;                       /* Power Up the EMAC controller. */
  
  LPC_PINCON->PINSEL2 = 0x50150105;                  /* Enable P1 Ethernet Pins. */
  LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000005;
  
   /* Reset all EMAC internal modules. */
  LPC_EMAC->MAC1    = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX |
                      MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;
  LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM;

  for(tout = 100; tout; tout--) __NOP();             /* A short delay after reset. */

  LPC_EMAC->MAC1 = MAC1_PASS_ALL;                    /* Initialize MAC control registers. */
  LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
  LPC_EMAC->MAXF = ETH_MAX_FLEN;
  LPC_EMAC->CLRT = CLRT_DEF;
  LPC_EMAC->IPGR = IPGR_DEF;

  LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;    /* Enable Reduced MII interface. */

  LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL;    /* Set clock */
  LPC_EMAC->MCFG |= MCFG_RES_MII;                    /* and reset */

  for(tout = 100; tout; tout--) __NOP();             /* A short delay */

  LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL;
  LPC_EMAC->MCMD = 0;

  LPC_EMAC->SUPP = SUPP_RES_RMII;                    /* Reset Reduced MII Logic. */

  for (tout = 100; tout; tout--) __NOP();            /* A short delay */

  LPC_EMAC->SUPP = 0;

  phy_write(PHY_REG_BMCR, PHY_BMCR_RESET);           /* perform PHY reset */
  for(tout = 0x20000; ; tout--) {                    /* Wait for hardware reset to end. */
    regv = phy_read(PHY_REG_BMCR);
    if(regv < 0 || tout == 0) {
       return -1;                                    /* Error */
    }
    if(!(regv & PHY_BMCR_RESET)) {
       break;                                        /* Reset complete. */
    }
  }

  phy_id =  (phy_read(PHY_REG_IDR1) << 16);
  phy_id |= (phy_read(PHY_REG_IDR2) & 0XFFF0);

  if (phy_id != DP83848C_ID && phy_id != LAN8720_ID) {
      error("Unknown Ethernet PHY (%x)", (unsigned int)phy_id);
  }

  ethernet_set_link(-1, 0);

  /* Set the Ethernet MAC Address registers */
  ethernet_address(mac);
  LPC_EMAC->SA0 = ((uint32_t)mac[5] << 8) | (uint32_t)mac[4];
  LPC_EMAC->SA1 = ((uint32_t)mac[3] << 8) | (uint32_t)mac[2];
  LPC_EMAC->SA2 = ((uint32_t)mac[1] << 8) | (uint32_t)mac[0];

  txdscr_init();                                      /* initialize DMA TX Descriptor */
  rxdscr_init();                                      /* initialize DMA RX Descriptor */

  LPC_EMAC->RxFilterCtrl = RFC_UCAST_EN | RFC_MCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;
                                                      /* Receive Broadcast, Perfect Match Packets */

  LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE;    /* Enable EMAC interrupts. */
  LPC_EMAC->IntClear  = 0xFFFF;                       /* Reset all interrupts */


  LPC_EMAC->Command  |= (CR_RX_EN | CR_TX_EN);        /* Enable receive and transmit mode of MAC Ethernet core */
  LPC_EMAC->MAC1     |= MAC1_REC_EN;

#if NEW_LOGIC
  rx_consume_offset = -1;
  tx_produce_offset = -1;
#else
  send_doff =  0;
  send_idx  = -1;
  send_size =  0;

  receive_soff =  0;
  receive_idx  = -1;
#endif

  return 0;
}