void exynos_sys_powerdown_conf(enum sys_powerdown mode) { unsigned int i; if (soc_is_exynos5250()) exynos5_init_pmu(); else if (soc_is_exynos5410()) exynos5410_init_pmu(); /* Setting SEQ_OPTION register */ if (soc_is_exynos5410()) exynos_set_core_flag(); for (i = 0; (exynos_pmu_config[i].reg != PMU_TABLE_END) ; i++) __raw_writel(exynos_pmu_config[i].val[mode], exynos_pmu_config[i].reg); }
static int __init exynos_pmu_init(void) { unsigned int value, i, j; if (soc_is_exynos4210()) { exynos_pmu_config = exynos4210_pmu_config; pr_info("EXYNOS4210 PMU Initialize\n"); } else if (soc_is_exynos4212()) { exynos_pmu_config = exynos4212_pmu_config; pr_info("EXYNOS4212 PMU Initialize\n"); } else if (soc_is_exynos4412()) { /* Follow registers should be set with 0x0 */ for (i = 0; i < ARRAY_SIZE(exynos4_list_disable_pmu_reg); i++) __raw_writel(0x0, exynos4_list_disable_pmu_reg[i]); exynos_pmu_config = exynos4412_pmu_config; pr_info("EXYNOS4412 PMU Initialize\n"); } else if (soc_is_exynos5250()) { /* Initialize for using delay reset assertion */ exynos_reset_assert_ctrl(true); /* * Set logic reset duration */ value = __raw_readl(EXYNOS5_LOGIC_RESET_DURATION3); value &= ~EXYNOS5_DUR_WAIT_RESET_MASK; value |= EXYNOS5_DUR_WAIT_RESET_MIN; __raw_writel(value, EXYNOS5_LOGIC_RESET_DURATION3); /* * Follow registers should be set with 0x0 */ for (i = 0; i < ARRAY_SIZE(exynos5_list_disable_pmu_reg); i++) __raw_writel(0x0, exynos5_list_disable_pmu_reg[i]); exynos_pmu_config = exynos5250_pmu_config; pr_info("EXYNOS5250 PMU Initialize\n"); } else if (soc_is_exynos5410()) { /* Set Stable counter */ __raw_writel(0x3a98, EXYNOS5_XXTI_DURATION3); __raw_writel(0x3fff, EXYNOS5_EXT_REGULATOR_DURATION3); /* Enable USE_STANDBY_WFI for all CORE */ __raw_writel(EXYNOS5410_USE_STANDBY_WFI_ALL, EXYNOS_CENTRAL_SEQ_OPTION); value = __raw_readl(EXYNOS_L2_OPTION(0)); value &= ~EXYNOS5_USE_RETENTION; __raw_writel(value, EXYNOS_L2_OPTION(0)); value = __raw_readl(EXYNOS_L2_OPTION(1)); value &= ~EXYNOS5_USE_RETENTION; __raw_writel(value, EXYNOS_L2_OPTION(1)); /* * If turn L2_COMMON off, clocks relating ATB async bridge is gated. * So when ISP power is gated, LPI is stucked. */ value = __raw_readl(EXYNOS5410_LPI_MASK0); value |= (ATB_ISP_ARM | ATB_KFC | ATB_NOC); __raw_writel(value, EXYNOS5410_LPI_MASK0); /* * To prevent form issuing new bus request form L2 memory system * If core status is power down, should be set '1' to L2 power down */ value = __raw_readl(EXYNOS5410_ARM_COMMON_OPTION); value |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN; __raw_writel(value, EXYNOS5410_ARM_COMMON_OPTION); /* * DUR_WAIT_RESET : 0xF * This setting is to reduce suspend/resume time. */ __raw_writel(DUR_WAIT_RESET, EXYNOS5410_LOGIC_RESET_DURATION3); /* Serialized CPU wakeup of Eagle */ __raw_writel(SPREAD_ENABLE, EXYNOS5410_ARM_INTR_SPREAD_ENABLE); __raw_writel(SPREAD_USE_STANDWFI, EXYNOS5410_ARM_INTR_SPREAD_USE_STANDBYWFI); __raw_writel(0x1, EXYNOS5410_UP_SCHEDULER); /* * Set measure power on/off duration * Use SC_USE_FEEDBACK */ exynos5410_init_pmu(); exynos_reset_assert_ctrl(true); if (samsung_rev() < EXYNOS5410_REV_2_3) { for (i = 0, j = 0; (exynos5410_pmu_config[i].reg != PMU_TABLE_END); i++) { if (exynos5410_pmu_config[i].reg == exynos5410_rev21_pmu_config[j].reg) { exynos5410_pmu_config[i].val[SYS_AFTR] = exynos5410_rev21_pmu_config[j].val[SYS_AFTR]; exynos5410_pmu_config[i].val[SYS_LPA] = exynos5410_rev21_pmu_config[j].val[SYS_LPA]; exynos5410_pmu_config[i].val[SYS_SLEEP] = exynos5410_rev21_pmu_config[j].val[SYS_SLEEP]; if (exynos5410_rev21_pmu_config[++j].reg == PMU_TABLE_END) break; } } } /* Follow registers should be set with 0x0 */ for (i = 0; i < ARRAY_SIZE(exynos5_list_disable_pmu_reg); i++) __raw_writel(0x0, exynos5_list_disable_pmu_reg[i]); exynos_pmu_config = exynos5410_pmu_config; pr_info("EXYNOS5410 PMU Initialize\n"); } else { pr_info("EXYNOS: PMU not supported\n"); } return 0; }