/* this sucks, but for now, fb size/location are hardcoded.
* Will break if we get 2. Sigh.
* We assume it's all multiples of MiB for MMUs sake.
*/
static void soc_enable(device_t dev)
{
u32 lcdbase = fb_base_mb();
unsigned long fb_size = FB_SIZE_MB;
ram_resource(dev, 0, (uintptr_t)_dram/KiB,
(sdram_max_addressable_mb() - fb_size)*KiB -
(uintptr_t)_dram/KiB);
mmio_resource(dev, 1, lcdbase*KiB, fb_size*KiB);
u32 sdram_end_mb = sdram_size_mb() + (uintptr_t)_dram/MiB;
if (sdram_end_mb > sdram_max_addressable_mb())
ram_resource(dev, 2, sdram_max_addressable_mb()*KiB,
(sdram_end_mb - sdram_max_addressable_mb())*KiB);
}
/* this sucks, but for now, fb size/location are hardcoded.
* Will break if we get 2. Sigh.
* We assume it's all multiples of MiB for MMUs sake.
*/
static void soc_enable(device_t dev)
{
u32 lcdbase = fb_base_mb();
unsigned long fb_size = FB_SIZE_MB;
ram_resource(dev, 0, CONFIG_SYS_SDRAM_BASE/KiB,
(sdram_max_addressable_mb() - fb_size)*KiB -
CONFIG_SYS_SDRAM_BASE/KiB);
mmio_resource(dev, 1, lcdbase*KiB, fb_size*KiB);
u32 sdram_end_mb = sdram_size_mb() + CONFIG_SYS_SDRAM_BASE/MiB;
if (sdram_end_mb > sdram_max_addressable_mb())
ram_resource(dev, 2, sdram_max_addressable_mb()*KiB,
(sdram_end_mb - sdram_max_addressable_mb())*KiB);
}
/* this is really aimed at the lcd panel. That said, there are two display
* devices on this part and we may someday want to extend it for other boards.
*/
void display_startup(device_t dev)
{
struct soc_nvidia_tegra124_config *config = dev->chip_info;
struct display_controller *disp_ctrl = (void *)config->display_controller;
struct pwm_controller *pwm = (void *)TEGRA_PWM_BASE;
struct tegra_dc *dc = &dc_data;
u32 plld_rate;
/* init dc */
dc->base = (void *)TEGRA_ARM_DISPLAYA;
dc->config = config;
config->dc_data = dc;
/* Note dp_init may read EDID and change some config values. */
dp_init(config);
/* should probably just make it all MiB ... in future */
u32 framebuffer_size_mb = config->framebuffer_size / MiB;
u32 framebuffer_base_mb= config->framebuffer_base / MiB;
/* light it all up */
/* This one may have been done in romstage but that's ok for now. */
if (config->panel_vdd_gpio){
gpio_output(config->panel_vdd_gpio, 1);
printk(BIOS_SPEW,"%s: panel_vdd setting gpio %08x to %d\n",
__func__, config->panel_vdd_gpio, 1);
}
udelay(config->vdd_delay_ms * 1000);
if (config->backlight_vdd_gpio){
gpio_output(config->backlight_vdd_gpio, 1);
printk(BIOS_SPEW,"%s: backlight vdd setting gpio %08x to %d\n",
__func__, config->backlight_vdd_gpio, 1);
}
if (config->lvds_shutdown_gpio){
gpio_output(config->lvds_shutdown_gpio, 0);
printk(BIOS_SPEW,"%s: lvds shutdown setting gpio %08x to %d\n",
__func__, config->lvds_shutdown_gpio, 0);
}
if (framebuffer_size_mb == 0){
framebuffer_size_mb = ALIGN_UP(config->xres * config->yres *
(config->framebuffer_bits_per_pixel / 8), MiB)/MiB;
}
if (! framebuffer_base_mb)
framebuffer_base_mb = fb_base_mb();
config->framebuffer_size = framebuffer_size_mb * MiB;
config->framebuffer_base = framebuffer_base_mb * MiB;
mmu_config_range(framebuffer_base_mb, framebuffer_size_mb,
config->cache_policy);
printk(BIOS_SPEW, "LCD frame buffer at %dMiB to %dMiB\n", framebuffer_base_mb,
framebuffer_base_mb + framebuffer_size_mb);
/* GPIO magic here if needed to start powering up things. You
* really only want to enable vdd, wait a bit, and then enable
* the panel. However ... the timings in the tegra20 dts make
* no sense to me. I'm pretty sure they're wrong.
* The panel_vdd is done in the romstage, so we need only
* light things up here once we're sure it's all working.
*/
/* The plld is programmed with the assumption of the SHIFT_CLK_DIVIDER
* and PIXEL_CLK_DIVIDER are zero (divide by 1). See the
* update_display_mode() for detail.
*/
plld_rate = clock_display(config->pixel_clock * 2);
if (plld_rate == 0) {
printk(BIOS_ERR, "dc: clock init failed\n");
return;
} else if (plld_rate != config->pixel_clock * 2) {
printk(BIOS_WARNING, "dc: plld rounded to %u\n", plld_rate);
config->pixel_clock = plld_rate / 2;
}
/* Init dc */
if (tegra_dc_init(disp_ctrl)) {
printk(BIOS_ERR, "dc: init failed\n");
return;
}
/* Configure dc mode */
if (update_display_mode(disp_ctrl, config)) {
printk(BIOS_ERR, "dc: failed to configure display mode.\n");
return;
}
/* Enable dp */
dp_enable(dc->out);
/* Init frame buffer */
memset((void *)(framebuffer_base_mb*MiB), 0x00,
framebuffer_size_mb*MiB);
update_window(disp_ctrl, config);
/* Set up Tegra PWM n (where n is specified in config->pwm) to drive the
* panel backlight.
*/
printk(BIOS_SPEW, "%s: enable panel backlight pwm\n", __func__);
WRITEL(((1 << NV_PWM_CSR_ENABLE_SHIFT) |
(220 << NV_PWM_CSR_PULSE_WIDTH_SHIFT) | /* 220/256 */
0x02e), /* frequency divider */
&pwm->pwm[config->pwm].csr);
udelay(config->pwm_to_bl_delay_ms * 1000);
if (config->backlight_en_gpio){
gpio_output(config->backlight_en_gpio, 1);
printk(BIOS_SPEW,"%s: backlight enable setting gpio %08x to %d\n",
__func__, config->backlight_en_gpio, 1);
}
printk(BIOS_INFO, "%s: display init done.\n", __func__);
/* tell depthcharge ...
*/
struct edid edid;
edid.bytes_per_line = ((config->xres * config->framebuffer_bits_per_pixel / 8 + 31) /
32 * 32);
edid.x_resolution = edid.bytes_per_line / (config->framebuffer_bits_per_pixel / 8);
edid.y_resolution = config->yres;
edid.framebuffer_bits_per_pixel = config->framebuffer_bits_per_pixel;
set_vbe_mode_info_valid(&edid, (uintptr_t)(framebuffer_base_mb*MiB));
}
