Beispiel #1
0
static void
draw_impl(struct fd_context *ctx, struct fd_ringbuffer *ring,
		struct fd3_emit *emit, unsigned index_offset)
{
	const struct pipe_draw_info *info = emit->info;
	enum pc_di_primtype primtype = ctx->primtypes[info->mode];

	fd3_emit_state(ctx, ring, emit);

	if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE))
		fd3_emit_vertex_bufs(ring, emit);

	OUT_PKT0(ring, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL, 1);
	OUT_RING(ring, 0x0000000b);             /* PC_VERTEX_REUSE_BLOCK_CNTL */

	OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
	OUT_RING(ring, add_sat(info->min_index, info->index_bias)); /* VFD_INDEX_MIN */
	OUT_RING(ring, add_sat(info->max_index, info->index_bias)); /* VFD_INDEX_MAX */
	OUT_RING(ring, info->start_instance);   /* VFD_INSTANCEID_OFFSET */
	OUT_RING(ring, info->index_size ? info->index_bias : info->start); /* VFD_INDEX_OFFSET */

	OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
	OUT_RING(ring, info->primitive_restart ? /* PC_RESTART_INDEX */
			info->restart_index : 0xffffffff);

	/* points + psize -> spritelist: */
	if (ctx->rasterizer->point_size_per_vertex &&
			fd3_emit_get_vp(emit)->writes_psize &&
			(info->mode == PIPE_PRIM_POINTS))
		primtype = DI_PT_POINTLIST_PSIZE;

	fd_draw_emit(ctx->batch, ring, primtype,
			emit->key.binning_pass ? IGNORE_VISIBILITY : USE_VISIBILITY,
			info, index_offset);
}
Beispiel #2
0
static bool
fd3_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
             unsigned index_offset)
{
	struct fd3_context *fd3_ctx = fd3_context(ctx);
	struct fd3_emit emit = {
		.debug = &ctx->debug,
		.vtx  = &ctx->vtx,
		.prog = &ctx->prog,
		.info = info,
		.key = {
			.color_two_side = ctx->rasterizer->light_twoside,
			.vclamp_color = ctx->rasterizer->clamp_vertex_color,
			.fclamp_color = ctx->rasterizer->clamp_fragment_color,
			.half_precision = ctx->in_blit &&
					fd_half_precision(&ctx->batch->framebuffer),
			.has_per_samp = (fd3_ctx->fsaturate || fd3_ctx->vsaturate),
			.vsaturate_s = fd3_ctx->vsaturate_s,
			.vsaturate_t = fd3_ctx->vsaturate_t,
			.vsaturate_r = fd3_ctx->vsaturate_r,
			.fsaturate_s = fd3_ctx->fsaturate_s,
			.fsaturate_t = fd3_ctx->fsaturate_t,
			.fsaturate_r = fd3_ctx->fsaturate_r,
		},
		.rasterflat = ctx->rasterizer->flatshade,
		.sprite_coord_enable = ctx->rasterizer->sprite_coord_enable,
		.sprite_coord_mode = ctx->rasterizer->sprite_coord_mode,
	};

	if (fd3_needs_manual_clipping(ctx->prog.vp, ctx->rasterizer))
		emit.key.ucp_enables = ctx->rasterizer->clip_plane_enable;

	fixup_shader_state(ctx, &emit.key);

	unsigned dirty = ctx->dirty;

	/* do regular pass first, since that is more likely to fail compiling: */

	if (!(fd3_emit_get_vp(&emit) && fd3_emit_get_fp(&emit)))
		return false;

	emit.key.binning_pass = false;
	emit.dirty = dirty;
	draw_impl(ctx, ctx->batch->draw, &emit, index_offset);

	/* and now binning pass: */
	emit.key.binning_pass = true;
	emit.dirty = dirty & ~(FD_DIRTY_BLEND);
	emit.vp = NULL;   /* we changed key so need to refetch vp */
	emit.fp = NULL;
	draw_impl(ctx, ctx->batch->binning, &emit, index_offset);

	fd_context_all_clean(ctx);

	return true;
}
Beispiel #3
0
void
fd3_program_emit(struct fd_ringbuffer *ring, struct fd3_emit *emit,
				 int nr, struct pipe_surface **bufs)
{
	const struct ir3_shader_variant *vp, *fp;
	const struct ir3_info *vsi, *fsi;
	enum a3xx_instrbuffermode fpbuffer, vpbuffer;
	uint32_t fpbuffersz, vpbuffersz, fsoff;
	uint32_t pos_regid, posz_regid, psize_regid, color_regid[4] = {0};
	int constmode;
	int i, j, k;

	debug_assert(nr <= ARRAY_SIZE(color_regid));

	vp = fd3_emit_get_vp(emit);
	fp = fd3_emit_get_fp(emit);

	vsi = &vp->info;
	fsi = &fp->info;

	fpbuffer = BUFFER;
	vpbuffer = BUFFER;
	fpbuffersz = fp->instrlen;
	vpbuffersz = vp->instrlen;

	/*
	 * Decide whether to use BUFFER or CACHE mode for VS and FS.  It
	 * appears like 256 is the hard limit, but when the combined size
	 * exceeds 128 then blob will try to keep FS in BUFFER mode and
	 * switch to CACHE for VS until VS is too large.  The blob seems
	 * to switch FS out of BUFFER mode at slightly under 128.  But
	 * a bit fuzzy on the decision tree, so use slightly conservative
	 * limits.
	 *
	 * TODO check if these thresholds for BUFFER vs CACHE mode are the
	 *      same for all a3xx or whether we need to consider the gpuid
	 */

	if ((fpbuffersz + vpbuffersz) > 128) {
		if (fpbuffersz < 112) {
			/* FP:BUFFER   VP:CACHE  */
			vpbuffer = CACHE;
			vpbuffersz = 256 - fpbuffersz;
		} else if (vpbuffersz < 112) {
			/* FP:CACHE    VP:BUFFER */
			fpbuffer = CACHE;
			fpbuffersz = 256 - vpbuffersz;
		} else {
			/* FP:CACHE    VP:CACHE  */
			vpbuffer = fpbuffer = CACHE;
			vpbuffersz = fpbuffersz = 192;
		}
	}

	if (fpbuffer == BUFFER) {
		fsoff = 128 - fpbuffersz;
	} else {
		fsoff = 256 - fpbuffersz;
	}

	/* seems like vs->constlen + fs->constlen > 256, then CONSTMODE=1 */
	constmode = ((vp->constlen + fp->constlen) > 256) ? 1 : 0;

	pos_regid = ir3_find_output_regid(vp, VARYING_SLOT_POS);
	posz_regid = ir3_find_output_regid(fp, FRAG_RESULT_DEPTH);
	psize_regid = ir3_find_output_regid(vp, VARYING_SLOT_PSIZ);
	if (fp->color0_mrt) {
		color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
			ir3_find_output_regid(fp, FRAG_RESULT_COLOR);
	} else {
		color_regid[0] = ir3_find_output_regid(fp, FRAG_RESULT_DATA0);
		color_regid[1] = ir3_find_output_regid(fp, FRAG_RESULT_DATA1);
		color_regid[2] = ir3_find_output_regid(fp, FRAG_RESULT_DATA2);
		color_regid[3] = ir3_find_output_regid(fp, FRAG_RESULT_DATA3);
	}

	/* adjust regids for alpha output formats. there is no alpha render
	 * format, so it's just treated like red
	 */
	for (i = 0; i < nr; i++)
		if (util_format_is_alpha(pipe_surface_format(bufs[i])))
			color_regid[i] += 3;

	/* we could probably divide this up into things that need to be
	 * emitted if frag-prog is dirty vs if vert-prog is dirty..
	 */

	OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 6);
	OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS) |
			A3XX_HLSQ_CONTROL_0_REG_CONSTMODE(constmode) |
			/* NOTE:  I guess SHADERRESTART and CONSTFULLUPDATE maybe
			 * flush some caches? I think we only need to set those
			 * bits if we have updated const or shader..
			 */
			A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART |
			A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE);
	OUT_RING(ring, A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
			A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE |
			COND(fp->frag_coord, A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID(regid(0,0)) |
					A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID(regid(0,2))));
	OUT_RING(ring, A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31));
	OUT_RING(ring, A3XX_HLSQ_CONTROL_3_REG_REGID(fp->pos_regid));
	OUT_RING(ring, A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(vp->constlen) |
			A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(0) |
			A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(vpbuffersz));
	OUT_RING(ring, A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(fp->constlen) |
			A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(128) |
			A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(fpbuffersz));

	OUT_PKT0(ring, REG_A3XX_SP_SP_CTRL_REG, 1);
	OUT_RING(ring, A3XX_SP_SP_CTRL_REG_CONSTMODE(constmode) |
			COND(emit->key.binning_pass, A3XX_SP_SP_CTRL_REG_BINNING) |
			A3XX_SP_SP_CTRL_REG_SLEEPMODE(1) |
			A3XX_SP_SP_CTRL_REG_L0MODE(0));

	OUT_PKT0(ring, REG_A3XX_SP_VS_LENGTH_REG, 1);
	OUT_RING(ring, A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(vp->instrlen));

	OUT_PKT0(ring, REG_A3XX_SP_VS_CTRL_REG0, 3);
	OUT_RING(ring, A3XX_SP_VS_CTRL_REG0_THREADMODE(MULTI) |
			A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(vpbuffer) |
			COND(vpbuffer == CACHE, A3XX_SP_VS_CTRL_REG0_CACHEINVALID) |
			A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(vsi->max_half_reg + 1) |
			A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vsi->max_reg + 1) |
			A3XX_SP_VS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
			A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE |
			A3XX_SP_VS_CTRL_REG0_LENGTH(vpbuffersz));
	OUT_RING(ring, A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(vp->constlen) |
			A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(vp->total_in) |
			A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(MAX2(vp->constlen + 1, 0)));
	OUT_RING(ring, A3XX_SP_VS_PARAM_REG_POSREGID(pos_regid) |
			A3XX_SP_VS_PARAM_REG_PSIZEREGID(psize_regid) |
			A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(fp->varying_in));

	for (i = 0, j = -1; (i < 8) && (j < (int)fp->inputs_count); i++) {
		uint32_t reg = 0;

		OUT_PKT0(ring, REG_A3XX_SP_VS_OUT_REG(i), 1);

		j = ir3_next_varying(fp, j);
		if (j < fp->inputs_count) {
			k = ir3_find_output(vp, fp->inputs[j].slot);
			reg |= A3XX_SP_VS_OUT_REG_A_REGID(vp->outputs[k].regid);
			reg |= A3XX_SP_VS_OUT_REG_A_COMPMASK(fp->inputs[j].compmask);
		}

		j = ir3_next_varying(fp, j);
		if (j < fp->inputs_count) {
			k = ir3_find_output(vp, fp->inputs[j].slot);
			reg |= A3XX_SP_VS_OUT_REG_B_REGID(vp->outputs[k].regid);
			reg |= A3XX_SP_VS_OUT_REG_B_COMPMASK(fp->inputs[j].compmask);
		}

		OUT_RING(ring, reg);
	}

	for (i = 0, j = -1; (i < 4) && (j < (int)fp->inputs_count); i++) {
		uint32_t reg = 0;

		OUT_PKT0(ring, REG_A3XX_SP_VS_VPC_DST_REG(i), 1);

		j = ir3_next_varying(fp, j);
		if (j < fp->inputs_count)
			reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC0(fp->inputs[j].inloc);
		j = ir3_next_varying(fp, j);
		if (j < fp->inputs_count)
			reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC1(fp->inputs[j].inloc);
		j = ir3_next_varying(fp, j);
		if (j < fp->inputs_count)
			reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC2(fp->inputs[j].inloc);
		j = ir3_next_varying(fp, j);
		if (j < fp->inputs_count)
			reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC3(fp->inputs[j].inloc);

		OUT_RING(ring, reg);
	}

	OUT_PKT0(ring, REG_A3XX_SP_VS_OBJ_OFFSET_REG, 2);
	OUT_RING(ring, A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(0) |
			A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
	OUT_RELOC(ring, vp->bo, 0, 0, 0);  /* SP_VS_OBJ_START_REG */

	if (emit->key.binning_pass) {
		OUT_PKT0(ring, REG_A3XX_SP_FS_LENGTH_REG, 1);
		OUT_RING(ring, 0x00000000);

		OUT_PKT0(ring, REG_A3XX_SP_FS_CTRL_REG0, 2);
		OUT_RING(ring, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
				A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(BUFFER));
		OUT_RING(ring, 0x00000000);

		OUT_PKT0(ring, REG_A3XX_SP_FS_OBJ_OFFSET_REG, 1);
		OUT_RING(ring, A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(128) |
				A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
	} else {
		OUT_PKT0(ring, REG_A3XX_SP_FS_LENGTH_REG, 1);
		OUT_RING(ring, A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(fp->instrlen));

		OUT_PKT0(ring, REG_A3XX_SP_FS_CTRL_REG0, 2);
		OUT_RING(ring, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
				A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(fpbuffer) |
				COND(fpbuffer == CACHE, A3XX_SP_FS_CTRL_REG0_CACHEINVALID) |
				A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(fsi->max_half_reg + 1) |
				A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fsi->max_reg + 1) |
				A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP |
				A3XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
				A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE |
				COND(fp->has_samp > 0, A3XX_SP_FS_CTRL_REG0_PIXLODENABLE) |
				A3XX_SP_FS_CTRL_REG0_LENGTH(fpbuffersz));
		OUT_RING(ring, A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(fp->constlen) |
				A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(fp->total_in) |
				A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(MAX2(fp->constlen + 1, 0)) |
				A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(63));

		OUT_PKT0(ring, REG_A3XX_SP_FS_OBJ_OFFSET_REG, 2);
		OUT_RING(ring, A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(
					MAX2(128, vp->constlen)) |
				A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(fsoff));
		OUT_RELOC(ring, fp->bo, 0, 0, 0);  /* SP_FS_OBJ_START_REG */
	}

	OUT_PKT0(ring, REG_A3XX_SP_FS_OUTPUT_REG, 1);
	OUT_RING(ring,
			 COND(fp->writes_pos, A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE) |
			 A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(posz_regid) |
			 A3XX_SP_FS_OUTPUT_REG_MRT(MAX2(1, nr) - 1));

	OUT_PKT0(ring, REG_A3XX_SP_FS_MRT_REG(0), 4);
	for (i = 0; i < 4; i++) {
		uint32_t mrt_reg = A3XX_SP_FS_MRT_REG_REGID(color_regid[i]) |
			COND(fp->key.half_precision, A3XX_SP_FS_MRT_REG_HALF_PRECISION);

		if (i < nr) {
			enum pipe_format fmt = pipe_surface_format(bufs[i]);
			mrt_reg |= COND(util_format_is_pure_uint(fmt), A3XX_SP_FS_MRT_REG_UINT) |
				COND(util_format_is_pure_sint(fmt), A3XX_SP_FS_MRT_REG_SINT);
		}
		OUT_RING(ring, mrt_reg);
	}

	if (emit->key.binning_pass) {
		OUT_PKT0(ring, REG_A3XX_VPC_ATTR, 2);
		OUT_RING(ring, A3XX_VPC_ATTR_THRDASSIGN(1) |
				A3XX_VPC_ATTR_LMSIZE(1) |
				COND(vp->writes_psize, A3XX_VPC_ATTR_PSIZE));
		OUT_RING(ring, 0x00000000);
	} else {
		uint32_t vinterp[4], flatshade[2], vpsrepl[4];

		memset(vinterp, 0, sizeof(vinterp));
		memset(flatshade, 0, sizeof(flatshade));
		memset(vpsrepl, 0, sizeof(vpsrepl));

		/* figure out VARYING_INTERP / FLAT_SHAD register values: */
		for (j = -1; (j = ir3_next_varying(fp, j)) < (int)fp->inputs_count; ) {
			/* NOTE: varyings are packed, so if compmask is 0xb
			 * then first, third, and fourth component occupy
			 * three consecutive varying slots:
			 */
			unsigned compmask = fp->inputs[j].compmask;

			/* TODO might be cleaner to just +8 in SP_VS_VPC_DST_REG
			 * instead.. rather than -8 everywhere else..
			 */
			uint32_t inloc = fp->inputs[j].inloc - 8;

			if ((fp->inputs[j].interpolate == INTERP_QUALIFIER_FLAT) ||
					(fp->inputs[j].rasterflat && emit->rasterflat)) {
				uint32_t loc = inloc;

				for (i = 0; i < 4; i++) {
					if (compmask & (1 << i)) {
						vinterp[loc / 16] |= FLAT << ((loc % 16) * 2);
						flatshade[loc / 32] |= 1 << (loc % 32);
						loc++;
					}
				}
			}

			gl_varying_slot slot = fp->inputs[j].slot;

			/* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
			if (slot >= VARYING_SLOT_VAR0) {
				unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
				/* Replace the .xy coordinates with S/T from the point sprite. Set
				 * interpolation bits for .zw such that they become .01
				 */
				if (emit->sprite_coord_enable & texmask) {
					/* mask is two 2-bit fields, where:
					 *   '01' -> S
					 *   '10' -> T
					 *   '11' -> 1 - T  (flip mode)
					 */
					unsigned mask = emit->sprite_coord_mode ? 0b1101 : 0b1001;
					uint32_t loc = inloc;
					if (compmask & 0x1) {
						vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
						loc++;
					}
					if (compmask & 0x2) {
						vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
						loc++;
					}
					if (compmask & 0x4) {
						/* .z <- 0.0f */
						vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
						loc++;
					}
					if (compmask & 0x8) {
						/* .w <- 1.0f */
						vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
						loc++;
					}
				}
Beispiel #4
0
void
fd3_program_emit(struct fd_ringbuffer *ring, struct fd3_emit *emit,
                 int nr, struct pipe_surface **bufs)
{
    const struct ir3_shader_variant *vp, *fp;
    const struct ir3_info *vsi, *fsi;
    enum a3xx_instrbuffermode fpbuffer, vpbuffer;
    uint32_t fpbuffersz, vpbuffersz, fsoff;
    uint32_t pos_regid, posz_regid, psize_regid, color_regid[4] = {0};
    int constmode;
    int i, j, k;

    debug_assert(nr <= ARRAY_SIZE(color_regid));

    vp = fd3_emit_get_vp(emit);

    if (emit->key.binning_pass) {
        /* use dummy stateobj to simplify binning vs non-binning: */
        static const struct ir3_shader_variant binning_fp = {};
        fp = &binning_fp;
    } else {
        fp = fd3_emit_get_fp(emit);
    }

    vsi = &vp->info;
    fsi = &fp->info;

    fpbuffer = BUFFER;
    vpbuffer = BUFFER;
    fpbuffersz = fp->instrlen;
    vpbuffersz = vp->instrlen;

    /*
     * Decide whether to use BUFFER or CACHE mode for VS and FS.  It
     * appears like 256 is the hard limit, but when the combined size
     * exceeds 128 then blob will try to keep FS in BUFFER mode and
     * switch to CACHE for VS until VS is too large.  The blob seems
     * to switch FS out of BUFFER mode at slightly under 128.  But
     * a bit fuzzy on the decision tree, so use slightly conservative
     * limits.
     *
     * TODO check if these thresholds for BUFFER vs CACHE mode are the
     *      same for all a3xx or whether we need to consider the gpuid
     */

    if ((fpbuffersz + vpbuffersz) > 128) {
        if (fpbuffersz < 112) {
            /* FP:BUFFER   VP:CACHE  */
            vpbuffer = CACHE;
            vpbuffersz = 256 - fpbuffersz;
        } else if (vpbuffersz < 112) {
            /* FP:CACHE    VP:BUFFER */
            fpbuffer = CACHE;
            fpbuffersz = 256 - vpbuffersz;
        } else {
            /* FP:CACHE    VP:CACHE  */
            vpbuffer = fpbuffer = CACHE;
            vpbuffersz = fpbuffersz = 192;
        }
    }

    if (fpbuffer == BUFFER) {
        fsoff = 128 - fpbuffersz;
    } else {
        fsoff = 256 - fpbuffersz;
    }

    /* seems like vs->constlen + fs->constlen > 256, then CONSTMODE=1 */
    constmode = ((vp->constlen + fp->constlen) > 256) ? 1 : 0;

    pos_regid = ir3_find_output_regid(vp,
                                      ir3_semantic_name(TGSI_SEMANTIC_POSITION, 0));
    posz_regid = ir3_find_output_regid(fp,
                                       ir3_semantic_name(TGSI_SEMANTIC_POSITION, 0));
    psize_regid = ir3_find_output_regid(vp,
                                        ir3_semantic_name(TGSI_SEMANTIC_PSIZE, 0));
    if (fp->color0_mrt) {
        color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
                                              ir3_find_output_regid(fp, ir3_semantic_name(TGSI_SEMANTIC_COLOR, 0));
    } else {
        for (i = 0; i < fp->outputs_count; i++) {
            ir3_semantic sem = fp->outputs[i].semantic;
            unsigned idx = sem2idx(sem);
            if (sem2name(sem) != TGSI_SEMANTIC_COLOR)
                continue;
            debug_assert(idx < ARRAY_SIZE(color_regid));
            color_regid[idx] = fp->outputs[i].regid;
        }
    }

    /* adjust regids for alpha output formats. there is no alpha render
     * format, so it's just treated like red
     */
    for (i = 0; i < nr; i++)
        if (util_format_is_alpha(pipe_surface_format(bufs[i])))
            color_regid[i] += 3;

    /* we could probably divide this up into things that need to be
     * emitted if frag-prog is dirty vs if vert-prog is dirty..
     */

    OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 6);
    OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS) |
             A3XX_HLSQ_CONTROL_0_REG_CONSTMODE(constmode) |
             /* NOTE:  I guess SHADERRESTART and CONSTFULLUPDATE maybe
              * flush some caches? I think we only need to set those
              * bits if we have updated const or shader..
              */
             A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART |
             A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE);
    OUT_RING(ring, A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
             A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE |
             COND(fp->frag_coord, A3XX_HLSQ_CONTROL_1_REG_ZWCOORD));
    OUT_RING(ring, A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31));
    OUT_RING(ring, A3XX_HLSQ_CONTROL_3_REG_REGID(fp->pos_regid));
    OUT_RING(ring, A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(vp->constlen) |
             A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(0) |
             A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(vpbuffersz));
    OUT_RING(ring, A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(fp->constlen) |
             A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(128) |
             A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(fpbuffersz));

    OUT_PKT0(ring, REG_A3XX_SP_SP_CTRL_REG, 1);
    OUT_RING(ring, A3XX_SP_SP_CTRL_REG_CONSTMODE(constmode) |
             COND(emit->key.binning_pass, A3XX_SP_SP_CTRL_REG_BINNING) |
             A3XX_SP_SP_CTRL_REG_SLEEPMODE(1) |
             A3XX_SP_SP_CTRL_REG_L0MODE(0));

    OUT_PKT0(ring, REG_A3XX_SP_VS_LENGTH_REG, 1);
    OUT_RING(ring, A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(vp->instrlen));

    OUT_PKT0(ring, REG_A3XX_SP_VS_CTRL_REG0, 3);
    OUT_RING(ring, A3XX_SP_VS_CTRL_REG0_THREADMODE(MULTI) |
             A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(vpbuffer) |
             COND(vpbuffer == CACHE, A3XX_SP_VS_CTRL_REG0_CACHEINVALID) |
             A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(vsi->max_half_reg + 1) |
             A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vsi->max_reg + 1) |
             A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(0) |
             A3XX_SP_VS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
             A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE |
             COND(vp->has_samp, A3XX_SP_VS_CTRL_REG0_PIXLODENABLE) |
             A3XX_SP_VS_CTRL_REG0_LENGTH(vpbuffersz));
    OUT_RING(ring, A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(vp->constlen) |
             A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(vp->total_in) |
             A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(MAX2(vp->constlen + 1, 0)));
    OUT_RING(ring, A3XX_SP_VS_PARAM_REG_POSREGID(pos_regid) |
             A3XX_SP_VS_PARAM_REG_PSIZEREGID(psize_regid) |
             A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(align(fp->total_in, 4) / 4));

    for (i = 0, j = -1; (i < 8) && (j < (int)fp->inputs_count); i++) {
        uint32_t reg = 0;

        OUT_PKT0(ring, REG_A3XX_SP_VS_OUT_REG(i), 1);

        j = ir3_next_varying(fp, j);
        if (j < fp->inputs_count) {
            k = ir3_find_output(vp, fp->inputs[j].semantic);
            reg |= A3XX_SP_VS_OUT_REG_A_REGID(vp->outputs[k].regid);
            reg |= A3XX_SP_VS_OUT_REG_A_COMPMASK(fp->inputs[j].compmask);
        }

        j = ir3_next_varying(fp, j);
        if (j < fp->inputs_count) {
            k = ir3_find_output(vp, fp->inputs[j].semantic);
            reg |= A3XX_SP_VS_OUT_REG_B_REGID(vp->outputs[k].regid);
            reg |= A3XX_SP_VS_OUT_REG_B_COMPMASK(fp->inputs[j].compmask);
        }

        OUT_RING(ring, reg);
    }

    for (i = 0, j = -1; (i < 4) && (j < (int)fp->inputs_count); i++) {
        uint32_t reg = 0;

        OUT_PKT0(ring, REG_A3XX_SP_VS_VPC_DST_REG(i), 1);

        j = ir3_next_varying(fp, j);
        if (j < fp->inputs_count)
            reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC0(fp->inputs[j].inloc);
        j = ir3_next_varying(fp, j);
        if (j < fp->inputs_count)
            reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC1(fp->inputs[j].inloc);
        j = ir3_next_varying(fp, j);
        if (j < fp->inputs_count)
            reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC2(fp->inputs[j].inloc);
        j = ir3_next_varying(fp, j);
        if (j < fp->inputs_count)
            reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC3(fp->inputs[j].inloc);

        OUT_RING(ring, reg);
    }

    OUT_PKT0(ring, REG_A3XX_SP_VS_OBJ_OFFSET_REG, 2);
    OUT_RING(ring, A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(0) |
             A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
    OUT_RELOC(ring, vp->bo, 0, 0, 0);  /* SP_VS_OBJ_START_REG */

    if (emit->key.binning_pass) {
        OUT_PKT0(ring, REG_A3XX_SP_FS_LENGTH_REG, 1);
        OUT_RING(ring, 0x00000000);

        OUT_PKT0(ring, REG_A3XX_SP_FS_CTRL_REG0, 2);
        OUT_RING(ring, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
                 A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(BUFFER));
        OUT_RING(ring, 0x00000000);

        OUT_PKT0(ring, REG_A3XX_SP_FS_OBJ_OFFSET_REG, 1);
        OUT_RING(ring, A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(128) |
                 A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
    } else {
        OUT_PKT0(ring, REG_A3XX_SP_FS_LENGTH_REG, 1);
        OUT_RING(ring, A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(fp->instrlen));

        OUT_PKT0(ring, REG_A3XX_SP_FS_CTRL_REG0, 2);
        OUT_RING(ring, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
                 A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(fpbuffer) |
                 COND(fpbuffer == CACHE, A3XX_SP_FS_CTRL_REG0_CACHEINVALID) |
                 A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(fsi->max_half_reg + 1) |
                 A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fsi->max_reg + 1) |
                 A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(1) |
                 A3XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
                 A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE |
                 COND(fp->has_samp > 0, A3XX_SP_FS_CTRL_REG0_PIXLODENABLE) |
                 A3XX_SP_FS_CTRL_REG0_LENGTH(fpbuffersz));
        OUT_RING(ring, A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(fp->constlen) |
                 A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(fp->total_in) |
                 A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(MAX2(fp->constlen + 1, 0)) |
                 A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(63));

        OUT_PKT0(ring, REG_A3XX_SP_FS_OBJ_OFFSET_REG, 2);
        OUT_RING(ring, A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(
                     MAX2(128, vp->constlen)) |
                 A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(fsoff));
        OUT_RELOC(ring, fp->bo, 0, 0, 0);  /* SP_FS_OBJ_START_REG */
    }

    OUT_PKT0(ring, REG_A3XX_SP_FS_OUTPUT_REG, 1);
    OUT_RING(ring,
             COND(fp->writes_pos, A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE) |
             A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(posz_regid) |
             A3XX_SP_FS_OUTPUT_REG_MRT(MAX2(1, nr) - 1));

    OUT_PKT0(ring, REG_A3XX_SP_FS_MRT_REG(0), 4);
    for (i = 0; i < 4; i++) {
        uint32_t mrt_reg = A3XX_SP_FS_MRT_REG_REGID(color_regid[i]) |
                           COND(fp->key.half_precision, A3XX_SP_FS_MRT_REG_HALF_PRECISION);

        if (i < nr) {
            enum pipe_format fmt = pipe_surface_format(bufs[i]);
            mrt_reg |= COND(util_format_is_pure_uint(fmt), A3XX_SP_FS_MRT_REG_UINT) |
                       COND(util_format_is_pure_sint(fmt), A3XX_SP_FS_MRT_REG_SINT);
        }
        OUT_RING(ring, mrt_reg);
    }

    if (emit->key.binning_pass) {
        OUT_PKT0(ring, REG_A3XX_VPC_ATTR, 2);
        OUT_RING(ring, A3XX_VPC_ATTR_THRDASSIGN(1) |
                 A3XX_VPC_ATTR_LMSIZE(1) |
                 COND(vp->writes_psize, A3XX_VPC_ATTR_PSIZE));
        OUT_RING(ring, 0x00000000);
    } else {
        uint32_t vinterp[4], flatshade[2], vpsrepl[4];

        memset(vinterp, 0, sizeof(vinterp));
        memset(flatshade, 0, sizeof(flatshade));
        memset(vpsrepl, 0, sizeof(vpsrepl));

        /* figure out VARYING_INTERP / FLAT_SHAD register values: */
        for (j = -1; (j = ir3_next_varying(fp, j)) < (int)fp->inputs_count; ) {
            uint32_t interp = fp->inputs[j].interpolate;

            /* TODO might be cleaner to just +8 in SP_VS_VPC_DST_REG
             * instead.. rather than -8 everywhere else..
             */
            uint32_t inloc = fp->inputs[j].inloc - 8;

            /* currently assuming varyings aligned to 4 (not
             * packed):
             */
            debug_assert((inloc % 4) == 0);

            if ((interp == TGSI_INTERPOLATE_CONSTANT) ||
                    ((interp == TGSI_INTERPOLATE_COLOR) && emit->rasterflat)) {
                uint32_t loc = inloc;
                for (i = 0; i < 4; i++, loc++) {
                    vinterp[loc / 16] |= FLAT << ((loc % 16) * 2);
                    flatshade[loc / 32] |= 1 << (loc % 32);
                }
            }

            /* Replace the .xy coordinates with S/T from the point sprite. Set
             * interpolation bits for .zw such that they become .01
             */
            if (emit->sprite_coord_enable & (1 << sem2idx(fp->inputs[j].semantic))) {
                vpsrepl[inloc / 16] |= (emit->sprite_coord_mode ? 0x0d : 0x09)
                                       << ((inloc % 16) * 2);
                vinterp[(inloc + 2) / 16] |= 2 << (((inloc + 2) % 16) * 2);
                vinterp[(inloc + 3) / 16] |= 3 << (((inloc + 3) % 16) * 2);
            }
        }

        OUT_PKT0(ring, REG_A3XX_VPC_ATTR, 2);
        OUT_RING(ring, A3XX_VPC_ATTR_TOTALATTR(fp->total_in) |
                 A3XX_VPC_ATTR_THRDASSIGN(1) |
                 A3XX_VPC_ATTR_LMSIZE(1) |
                 COND(vp->writes_psize, A3XX_VPC_ATTR_PSIZE));
        OUT_RING(ring, A3XX_VPC_PACK_NUMFPNONPOSVAR(fp->total_in) |
                 A3XX_VPC_PACK_NUMNONPOSVSVAR(fp->total_in));

        OUT_PKT0(ring, REG_A3XX_VPC_VARYING_INTERP_MODE(0), 4);
        OUT_RING(ring, vinterp[0]);    /* VPC_VARYING_INTERP[0].MODE */
        OUT_RING(ring, vinterp[1]);    /* VPC_VARYING_INTERP[1].MODE */
        OUT_RING(ring, vinterp[2]);    /* VPC_VARYING_INTERP[2].MODE */
        OUT_RING(ring, vinterp[3]);    /* VPC_VARYING_INTERP[3].MODE */

        OUT_PKT0(ring, REG_A3XX_VPC_VARYING_PS_REPL_MODE(0), 4);
        OUT_RING(ring, vpsrepl[0]);    /* VPC_VARYING_PS_REPL[0].MODE */
        OUT_RING(ring, vpsrepl[1]);    /* VPC_VARYING_PS_REPL[1].MODE */
        OUT_RING(ring, vpsrepl[2]);    /* VPC_VARYING_PS_REPL[2].MODE */
        OUT_RING(ring, vpsrepl[3]);    /* VPC_VARYING_PS_REPL[3].MODE */

        OUT_PKT0(ring, REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0, 2);
        OUT_RING(ring, flatshade[0]);        /* SP_FS_FLAT_SHAD_MODE_REG_0 */
        OUT_RING(ring, flatshade[1]);        /* SP_FS_FLAT_SHAD_MODE_REG_1 */
    }

    if (vpbuffer == BUFFER)
        emit_shader(ring, vp);

    OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
    OUT_RING(ring, 0x00000000);        /* VFD_PERFCOUNTER0_SELECT */

    if (!emit->key.binning_pass) {
        if (fpbuffer == BUFFER)
            emit_shader(ring, fp);

        OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
        OUT_RING(ring, 0x00000000);        /* VFD_PERFCOUNTER0_SELECT */
    }
}