void EXTI1_IRQHandler(void)
{
if(EXTI_GetITStatus(DIO1_IRQ) != RESET)
{
EXTI_ClearITPendingBit(DIO1_IRQ);
if(g_fsk.states == RF_STATE_TX_RUNNING)
{
fill_fifo();
}
if(g_fsk.states == RF_STATE_RX_SYNC)
{
read_fifo(false);
}
}
}
static void audio_isr (int irq, void *dev_id, struct pt_regs *regs)
{
int used;
used = (audio_state.tail - audio_state.head + AUDIO_FRAMES) %
AUDIO_FRAMES;
if (used >= 2 * sizeof(u16))
fill_fifo(used);
else {
DBG(3, "%s: Empty buffer.\n", __FUNCTION__);
}
/* We have to clear the int request _after_ filling the fifo as
* half-full int requests are generated as the fifo is filled as
* well as being emptied...
*/
ATU_Registers->ETU_int_clear = (ETU_INT_WR_CH1L_HALF |
ETU_INT_WR_CH1L_EMPTY);
wake_up_interruptible (&audio_state.wq);
}
void SX1276Fsk_Send_Packet(u8 *PBuffer,u8 length)
{
SX1276FskSetOpMode( RF_OPMODE_STANDBY );
// PacketSent, FifoLevel, FifoFull, TxReady
SX1276->RegDioMapping1 = packet_DIO0_packetSend | packet_DIO1_fifoLevel | packet_DIO2_fifoFull | packet_DIO3_TxReady;
// LowBat, Data
SX1276->RegDioMapping2 = packet_DIO4_TimeOut | packet_DIO5_Data ;
SX1276WriteBuffer( REG_DIOMAPPING1, &SX1276->RegDioMapping1, 2 );
SX1276->RegFifoThresh = RF_FIFOTHRESH_TXSTARTCONDITION_FIFONOTEMPTY | TX_FIFO_THRESHOLD; // 24 bytes of data
SX1276Write( REG_FIFOTHRESH, SX1276->RegFifoThresh );
packet_tx_data(PBuffer, length);
hal_DIOx_ITConfig(0,ENABLE);
hal_fsk_eit_failing(1,ENABLE);
fill_fifo();
g_fsk.states = RF_STATE_TX_RUNNING;
SX1276FskSetOpMode( RF_OPMODE_TRANSMITTER );
}
