static int
malo_hal_fwload_helper(struct malo_hal *mh, char *helper)
{
const struct firmware *fw;
int error;
fw = firmware_get(helper);
if (fw == NULL) {
device_printf(mh->mh_dev, "could not read microcode %s!\n",
helper);
return (EIO);
}
device_printf(mh->mh_dev, "load %s firmware image (%zu bytes)\n",
helper, fw->datasize);
error = malo_hal_send_helper(mh, fw->datasize, fw->data, fw->datasize,
MALO_WAITOK);
if (error != 0)
goto fail;
/* tell the card we're done and... */
error = malo_hal_send_helper(mh, 0, NULL, 0, MALO_NOWAIT);
fail:
firmware_put(fw, FIRMWARE_UNLOAD);
return (error);
}
static int
fw_consumer_modevent(module_t mod, int type, void *unused)
{
switch (type) {
case MOD_LOAD:
fp = firmware_get("beastie");
if (fp == NULL)
return (ENOENT);
if (((const char *)fp->data)[fp->datasize - 1] != '\0') {
firmware_put(fp, FIRMWARE_UNLOAD);
return (EINVAL);
}
printf("%s", (const char *)fp->data);
return (0);
case MOD_UNLOAD:
printf("Bye!\n");
if (fp != NULL) {
printf("%s", (const char *)fp->data);
firmware_put(fp, FIRMWARE_UNLOAD);
}
return (0);
}
return (EINVAL);
}
static int
malo_hal_fwload_main(struct malo_hal *mh, char *firmware)
{
const struct firmware *fw;
const uint8_t *fp;
int error;
size_t count;
uint16_t seqnum;
uint32_t blocksize;
error = 0;
fw = firmware_get(firmware);
if (fw == NULL) {
device_printf(mh->mh_dev, "could not read firmware %s!\n",
firmware);
return (EIO);
}
device_printf(mh->mh_dev, "load %s firmware image (%zu bytes)\n",
firmware, fw->datasize);
seqnum = 1;
for (count = 0; count < fw->datasize; count += blocksize) {
blocksize = MIN(256, fw->datasize - count);
fp = (const uint8_t *)fw->data + count;
error = malo_hal_send_main(mh, fp, blocksize, seqnum++,
MALO_NOWAIT);
if (error != 0)
goto fail;
DELAY(500);
}
/*
* send a command with size 0 to tell that the firmware has been
* uploaded
*/
error = malo_hal_send_main(mh, NULL, 0, seqnum++, MALO_NOWAIT);
DELAY(100);
fail:
firmware_put(fw, FIRMWARE_UNLOAD);
return (error);
}
static int
oce_sys_fwupgrade(SYSCTL_HANDLER_ARGS)
{
char ufiname[256] = {0};
uint32_t status = 1;
struct oce_softc *sc = (struct oce_softc *)arg1;
const struct firmware *fw;
status = sysctl_handle_string(oidp, ufiname, sizeof(ufiname), req);
if (status || !req->newptr)
return status;
fw = firmware_get(ufiname);
if (fw == NULL) {
device_printf(sc->dev, "Unable to get Firmware. "
"Make sure %s is copied to /boot/modules\n", ufiname);
return ENOENT;
}
if (IS_BE(sc)) {
if ((sc->flags & OCE_FLAGS_BE2)) {
device_printf(sc->dev,
"Flashing not supported for BE2 yet.\n");
status = 1;
goto done;
}
status = oce_be3_fwupgrade(sc, fw);
} else if (IS_SH(sc)) {
status = oce_skyhawk_fwupgrade(sc,fw);
} else
status = oce_lancer_fwupgrade(sc, fw);
done:
if (status) {
device_printf(sc->dev, "Firmware Upgrade failed\n");
} else {
device_printf(sc->dev, "Firmware Flashed successfully\n");
}
/* Release Firmware*/
firmware_put(fw, FIRMWARE_UNLOAD);
return status;
}
int base_handle_setup(const USB_Setup_TypeDef *setup)
{
switch (setup->wValue) {
case BASE_CMD_NOOP:
__asm("nop");
return USB_STATUS_OK;
case BASE_CMD_SERIAL_GET:
//serial_get(setup);
case BASE_CMD_FIRMWARE_GET:
return firmware_get(setup);
case BASE_CMD_LED_SET:
return led_set(setup);
case BASE_CMD_RESET:
NVIC_SystemReset();
return USB_STATUS_OK;
}
return USB_STATUS_REQ_UNHANDLED;
}
static int
load_fw(struct tegra_xhci_softc *sc)
{
const struct firmware *fw;
const struct tegra_xusb_fw_hdr *fw_hdr;
vm_paddr_t fw_paddr, fw_base;
vm_offset_t fw_vaddr;
vm_size_t fw_size;
uint32_t code_tags, code_size;
struct clocktime fw_clock;
struct timespec fw_timespec;
int i;
/* Reset ARU */
FPCI_WR4(sc, XUSB_CFG_ARU_RST, ARU_RST_RESET);
DELAY(3000);
/* Check if FALCON already runs */
if (CSB_RD4(sc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO) != 0) {
device_printf(sc->dev,
"XUSB CPU is already loaded, CPUCTL: 0x%08X\n",
CSB_RD4(sc, XUSB_FALCON_CPUCTL));
return (0);
}
fw = firmware_get(sc->fw_name);
if (fw == NULL) {
device_printf(sc->dev, "Cannot read xusb firmware\n");
return (ENOENT);
}
/* Allocate uncached memory and copy firmware into. */
fw_hdr = (const struct tegra_xusb_fw_hdr *)fw->data;
fw_size = fw_hdr->fwimg_len;
fw_vaddr = kmem_alloc_contig(kernel_arena, fw_size,
M_WAITOK, 0, -1UL, PAGE_SIZE, 0, VM_MEMATTR_UNCACHEABLE);
fw_paddr = vtophys(fw_vaddr);
fw_hdr = (const struct tegra_xusb_fw_hdr *)fw_vaddr;
memcpy((void *)fw_vaddr, fw->data, fw_size);
firmware_put(fw, FIRMWARE_UNLOAD);
sc->fw_vaddr = fw_vaddr;
sc->fw_size = fw_size;
/* Setup firmware physical address and size. */
fw_base = fw_paddr + sizeof(*fw_hdr);
CSB_WR4(sc, XUSB_CSB_MEMPOOL_ILOAD_ATTR, fw_size);
CSB_WR4(sc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO, fw_base & 0xFFFFFFFF);
CSB_WR4(sc, XUSB_CSB_MEMPOOL_ILOAD_BASE_HI, (uint64_t)fw_base >> 32);
CSB_WR4(sc, XUSB_CSB_MEMPOOL_APMAP, APMAP_BOOTPATH);
/* Invalidate full L2IMEM context. */
CSB_WR4(sc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG,
L2IMEMOP_INVALIDATE_ALL);
/* Program load of L2IMEM by boot code. */
code_tags = howmany(fw_hdr->boot_codetag, XUSB_CSB_IMEM_BLOCK_SIZE);
code_size = howmany(fw_hdr->boot_codesize, XUSB_CSB_IMEM_BLOCK_SIZE);
CSB_WR4(sc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE,
L2IMEMOP_SIZE_OFFSET(code_tags) |
L2IMEMOP_SIZE_SIZE(code_size));
/* Execute L2IMEM boot code fetch. */
CSB_WR4(sc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG,
L2IMEMOP_LOAD_LOCKED_RESULT);
/* Program FALCON auto-fill range and block count */
CSB_WR4(sc, XUSB_FALCON_IMFILLCTL, code_size);
CSB_WR4(sc, XUSB_FALCON_IMFILLRNG1,
IMFILLRNG1_TAG_LO(code_tags) |
IMFILLRNG1_TAG_HI(code_tags + code_size));
CSB_WR4(sc, XUSB_FALCON_DMACTL, 0);
/* Wait for CPU */
for (i = 500; i > 0; i--) {
if (CSB_RD4(sc, XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT) &
L2IMEMOP_RESULT_VLD)
break;
DELAY(100);
}
if (i <= 0) {
device_printf(sc->dev, "Timedout while wating for DMA, "
"state: 0x%08X\n",
CSB_RD4(sc, XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT));
return (ETIMEDOUT);
}
/* Boot FALCON cpu */
CSB_WR4(sc, XUSB_FALCON_BOOTVEC, fw_hdr->boot_codetag);
CSB_WR4(sc, XUSB_FALCON_CPUCTL, CPUCTL_STARTCPU);
/* Wait for CPU */
for (i = 50; i > 0; i--) {
if (CSB_RD4(sc, XUSB_FALCON_CPUCTL) == CPUCTL_STOPPED)
break;
DELAY(100);
}
if (i <= 0) {
device_printf(sc->dev, "Timedout while wating for FALCON cpu, "
"state: 0x%08X\n", CSB_RD4(sc, XUSB_FALCON_CPUCTL));
return (ETIMEDOUT);
}
fw_timespec.tv_sec = fw_hdr->fwimg_created_time;
fw_timespec.tv_nsec = 0;
clock_ts_to_ct(&fw_timespec, &fw_clock);
device_printf(sc->dev,
" Falcon firmware version: %02X.%02X.%04X,"
" (%d/%d/%d %d:%02d:%02d UTC)\n",
(fw_hdr->version_id >> 24) & 0xFF,(fw_hdr->version_id >> 15) & 0xFF,
fw_hdr->version_id & 0xFFFF,
fw_clock.day, fw_clock.mon, fw_clock.year,
fw_clock.hour, fw_clock.min, fw_clock.sec);
return (0);
}
static int
ath_pci_attach(device_t dev)
{
struct ath_pci_softc *psc = device_get_softc(dev);
struct ath_softc *sc = &psc->sc_sc;
int error = ENXIO;
int rid;
#ifdef ATH_EEPROM_FIRMWARE
const struct firmware *fw = NULL;
const char *buf;
#endif
const struct pci_device_id *pd;
sc->sc_dev = dev;
/* Do this lookup anyway; figure out what to do with it later */
pd = ath_pci_probe_device(dev, ath_pci_id_table, nitems(ath_pci_id_table));
if (pd)
sc->sc_pci_devinfo = pd->driver_data;
/*
* Enable bus mastering.
*/
pci_enable_busmaster(dev);
/*
* Setup other PCI bus configuration parameters.
*/
ath_pci_setup(dev);
/*
* Setup memory-mapping of PCI registers.
*/
rid = BS_BAR;
psc->sc_sr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
RF_ACTIVE);
if (psc->sc_sr == NULL) {
device_printf(dev, "cannot map register space\n");
goto bad;
}
sc->sc_st = (HAL_BUS_TAG) rman_get_bustag(psc->sc_sr);
sc->sc_sh = (HAL_BUS_HANDLE) rman_get_bushandle(psc->sc_sr);
/*
* Mark device invalid so any interrupts (shared or otherwise)
* that arrive before the HAL is setup are discarded.
*/
sc->sc_invalid = 1;
ATH_LOCK_INIT(sc);
ATH_PCU_LOCK_INIT(sc);
ATH_RX_LOCK_INIT(sc);
ATH_TX_LOCK_INIT(sc);
ATH_TXSTATUS_LOCK_INIT(sc);
/*
* Arrange interrupt line.
*/
rid = 0;
psc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
RF_SHAREABLE|RF_ACTIVE);
if (psc->sc_irq == NULL) {
device_printf(dev, "could not map interrupt\n");
goto bad1;
}
if (bus_setup_intr(dev, psc->sc_irq,
INTR_TYPE_NET | INTR_MPSAFE,
NULL, ath_intr, sc, &psc->sc_ih)) {
device_printf(dev, "could not establish interrupt\n");
goto bad2;
}
/*
* Setup DMA descriptor area.
*/
if (bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1, 0, /* alignment, bounds */
BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
BUS_SPACE_MAXADDR, /* highaddr */
NULL, NULL, /* filter, filterarg */
0x3ffff, /* maxsize XXX */
ATH_MAX_SCATTER, /* nsegments */
0x3ffff, /* maxsegsize XXX */
BUS_DMA_ALLOCNOW, /* flags */
NULL, /* lockfunc */
NULL, /* lockarg */
&sc->sc_dmat)) {
device_printf(dev, "cannot allocate DMA tag\n");
goto bad3;
}
#ifdef ATH_EEPROM_FIRMWARE
/*
* If there's an EEPROM firmware image, load that in.
*/
if (resource_string_value(device_get_name(dev), device_get_unit(dev),
"eeprom_firmware", &buf) == 0) {
if (bootverbose)
device_printf(dev, "%s: looking up firmware @ '%s'\n",
__func__, buf);
fw = firmware_get(buf);
if (fw == NULL) {
device_printf(dev, "%s: couldn't find firmware\n",
__func__);
goto bad4;
}
device_printf(dev, "%s: EEPROM firmware @ %p\n",
__func__, fw->data);
sc->sc_eepromdata =
malloc(fw->datasize, M_TEMP, M_WAITOK | M_ZERO);
if (! sc->sc_eepromdata) {
device_printf(dev, "%s: can't malloc eepromdata\n",
__func__);
goto bad4;
}
memcpy(sc->sc_eepromdata, fw->data, fw->datasize);
firmware_put(fw, 0);
}
#endif /* ATH_EEPROM_FIRMWARE */
error = ath_attach(pci_get_device(dev), sc);
if (error == 0) /* success */
return 0;
#ifdef ATH_EEPROM_FIRMWARE
bad4:
#endif
bus_dma_tag_destroy(sc->sc_dmat);
bad3:
bus_teardown_intr(dev, psc->sc_irq, psc->sc_ih);
bad2:
bus_release_resource(dev, SYS_RES_IRQ, 0, psc->sc_irq);
bad1:
bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, psc->sc_sr);
ATH_TXSTATUS_LOCK_DESTROY(sc);
ATH_PCU_LOCK_DESTROY(sc);
ATH_RX_LOCK_DESTROY(sc);
ATH_TX_LOCK_DESTROY(sc);
ATH_LOCK_DESTROY(sc);
bad:
return (error);
}
