static void brcm_intc_dispatch(struct pt_regs *regs, unsigned long base)
{
u32 pend, shift;
pend = L1_RD_W0(base, STATUS) & ~L1_RD_W0(base, MASK_STATUS);
while((shift = ffs(pend)) != 0) {
pend ^= (1 << (shift - 1));
do_IRQ(shift);
flip_tp(shift);
}
pend = L1_RD_W1(base, STATUS) & ~L1_RD_W1(base, MASK_STATUS);
while((shift = ffs(pend)) != 0) {
pend ^= (1 << (shift - 1));
shift += 32;
do_IRQ(shift);
flip_tp(shift);
}
pend = L1_RD_W2(base, STATUS) & ~L1_RD_W2(base, MASK_STATUS);
while((shift = ffs(pend)) != 0) {
pend ^= (1 << (shift - 1));
shift += 64;
do_IRQ(shift);
flip_tp(shift);
}
}
static void brcm_intc_dispatch(struct pt_regs *regs, volatile Int1Control *l1)
{
unsigned int __attribute_unused__
pendingIrqs0, pendingIrqs1, pendingIrqs2;
unsigned int shift,irq;
pendingIrqs0 = l1->IntrW0Status & ~(l1->IntrW0MaskStatus);
pendingIrqs1 = l1->IntrW1Status & ~(l1->IntrW1MaskStatus);
#if L1_IRQS > 64
pendingIrqs2 = l1->IntrW2Status & ~(l1->IntrW2MaskStatus);
#endif
for (irq=1; irq<=32; irq++)
{
shift = irq - 1;
if ((0x1 << shift) & pendingIrqs0) {
do_IRQ(irq, regs);
flip_tp(irq);
}
}
for (irq = 32+1; irq <= 32+32; irq++)
{
shift = irq - 32 - 1;
if ((0x1 << shift) & pendingIrqs1) {
do_IRQ(irq, regs);
flip_tp(irq);
}
}
#if L1_IRQS > 64
for (irq = 64+1; irq <= 64+32; irq++)
{
shift = irq - 64 - 1;
if ((0x1 << shift) & pendingIrqs2) {
do_IRQ(irq, regs);
flip_tp(irq);
}
}
#endif
}
