void flite_hw_set_dma_addr(u32 __iomem *base_reg, u32 number, bool use, u32 addr)
{
/* dma addr set */
if (use) {
flite_hw_set_start_addr(base_reg, number, addr);
flite_hw_set_use_buffer(base_reg, number);
flite_hw_set_output_dma(base_reg, true);
} else {
/* dma addr set */
flite_hw_set_unuse_buffer(base_reg, number);
flite_hw_set_start_addr(base_reg, number, 0);
flite_hw_set_output_dma(base_reg, false);
}
}
static int fimc_lite_hw_init(struct fimc_lite *fimc)
{
struct fimc_pipeline *pipeline = &fimc->pipeline;
struct fimc_sensor_info *sensor;
unsigned long flags;
if (pipeline->subdevs[IDX_SENSOR] == NULL)
return -ENXIO;
if (fimc->fmt == NULL)
return -EINVAL;
sensor = v4l2_get_subdev_hostdata(pipeline->subdevs[IDX_SENSOR]);
spin_lock_irqsave(&fimc->slock, flags);
flite_hw_set_camera_bus(fimc, &sensor->pdata);
flite_hw_set_source_format(fimc, &fimc->inp_frame);
flite_hw_set_window_offset(fimc, &fimc->inp_frame);
flite_hw_set_output_dma(fimc, &fimc->out_frame, true);
flite_hw_set_interrupt_mask(fimc);
flite_hw_set_test_pattern(fimc, fimc->test_pattern->val);
if (debug > 0)
flite_hw_dump_regs(fimc, __func__);
spin_unlock_irqrestore(&fimc->slock, flags);
return 0;
}
static int fimc_lite_hw_init(struct fimc_lite *fimc, bool isp_output)
{
struct fimc_source_info *si;
unsigned long flags;
if (fimc->sensor == NULL)
return -ENXIO;
if (fimc->inp_frame.fmt == NULL || fimc->out_frame.fmt == NULL)
return -EINVAL;
/* Get sensor configuration data from the sensor subdev */
si = v4l2_get_subdev_hostdata(fimc->sensor);
if (!si)
return -EINVAL;
spin_lock_irqsave(&fimc->slock, flags);
flite_hw_set_camera_bus(fimc, si);
flite_hw_set_source_format(fimc, &fimc->inp_frame);
flite_hw_set_window_offset(fimc, &fimc->inp_frame);
flite_hw_set_dma_buf_mask(fimc, 0);
flite_hw_set_output_dma(fimc, &fimc->out_frame, !isp_output);
flite_hw_set_interrupt_mask(fimc);
flite_hw_set_test_pattern(fimc, fimc->test_pattern->val);
if (debug > 0)
flite_hw_dump_regs(fimc, __func__);
spin_unlock_irqrestore(&fimc->slock, flags);
return 0;
}
static int flite_s_stream(struct v4l2_subdev *sd, int enable)
{
struct flite_dev *flite = to_flite_dev(sd);
u32 index = flite->pdata->active_cam_index;
struct s3c_platform_camera *cam = flite->pdata->cam[index];
u32 int_src = FLITE_REG_CIGCTRL_IRQ_LASTEN0_ENABLE;
unsigned long flags;
int ret = 0;
if (enable)
flite_hw_reset(flite);
spin_lock_irqsave(&flite->slock, flags);
if (test_bit(FLITE_ST_SUSPENDED, &flite->state))
goto s_stream_unlock;
if (enable) {
flite_hw_set_cam_channel(flite);
flite_hw_set_cam_source_size(flite);
flite_hw_set_camera_type(flite, cam);
ret = flite_hw_set_source_format(flite);
if (unlikely(ret < 0))
goto s_stream_unlock;
if (cam->use_isp)
flite_hw_set_output_dma(flite, false);
flite_hw_set_interrupt_source(flite, int_src);
flite_hw_set_config_irq(flite, cam);
flite_hw_set_window_offset(flite);
flite_hw_set_capture_start(flite);
set_bit(FLITE_ST_STREAMING, &flite->state);
} else {
if (test_bit(FLITE_ST_STREAMING, &flite->state)) {
flite_hw_set_capture_stop(flite);
spin_unlock_irqrestore(&flite->slock, flags);
ret = wait_event_timeout(flite->irq_queue,
!test_bit(FLITE_ST_STREAMING, &flite->state), HZ/20); /* 50 ms */
if (unlikely(!ret)) {
v4l2_err(sd, "wait timeout\n");
ret = -EBUSY;
}
}
return ret;
}
s_stream_unlock:
spin_unlock_irqrestore(&flite->slock, flags);
return ret;
}