void HELPER(gvec_fcmlas_idx)(void *vd, void *vn, void *vm,
void *vfpst, uint32_t desc)
{
uintptr_t opr_sz = simd_oprsz(desc);
float32 *d = vd;
float32 *n = vn;
float32 *m = vm;
float_status *fpst = vfpst;
intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
uint32_t neg_real = flip ^ neg_imag;
uintptr_t i;
float32 e1 = m[H4(flip)];
float32 e3 = m[H4(1 - flip)];
/* Shift boolean to the sign bit so we can xor to negate. */
neg_real <<= 31;
neg_imag <<= 31;
e1 ^= neg_real;
e3 ^= neg_imag;
for (i = 0; i < opr_sz / 4; i += 2) {
float32 e2 = n[H4(i + flip)];
float32 e4 = e2;
d[H4(i)] = float32_muladd(e2, e1, d[H4(i)], 0, fpst);
d[H4(i + 1)] = float32_muladd(e4, e3, d[H4(i + 1)], 0, fpst);
}
clear_tail(d, opr_sz, simd_maxsz(desc));
}
float32 helper_fmac_FT(CPUSH4State *env, float32 t0, float32 t1, float32 t2)
{
set_float_exception_flags(0, &env->fp_status);
t0 = float32_muladd(t0, t1, t2, 0, &env->fp_status);
update_fpscr(env, GETPC());
return t0;
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VFNMADD231SS_VpsHssWssR(bxInstruction_c *i)
{
float32 op1 = BX_READ_XMM_REG_LO_DWORD(i->nnn());
float32 op2 = BX_READ_XMM_REG_LO_DWORD(i->vvv());
float32 op3 = BX_READ_XMM_REG_LO_DWORD(i->rm());
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
op1 = float32_muladd(op2, op3, op1, float_muladd_negate_product, status);
check_exceptionsSSE(status.float_exception_flags);
BX_WRITE_XMM_REG_LO_DWORD(i->nnn(), op1);
BX_CLEAR_AVX_HIGH(i->nnn());
BX_NEXT_INSTR(i);
}
float32 HELPER(msub_s)(CPUXtensaState *env, float32 a, float32 b, float32 c)
{
return float32_muladd(b, c, a, float_muladd_negate_product,
&env->fp_status);
}
float32 HELPER(madd_s)(CPUXtensaState *env, float32 a, float32 b, float32 c)
{
return float32_muladd(b, c, a, 0, &env->fp_status);
}
