Beispiel #1
0
static int __init ppc4xx_pci_find_bridges(void)
{
	struct device_node *np;

#ifdef CONFIG_PPC4xx_PCI_EXPRESS
	for_each_compatible_node(np, NULL, "ibm,plb-pciex")
		ppc4xx_probe_pciex_bridge(np);
#endif
	for_each_compatible_node(np, NULL, "ibm,plb-pcix")
		ppc4xx_probe_pcix_bridge(np);
	for_each_compatible_node(np, NULL, "ibm,plb-pci")
		ppc4xx_probe_pci_bridge(np);

	return 0;
}
static int __init mpc8xxx_add_gpiochips(void)
{
	struct device_node *np;

	for_each_compatible_node(np, NULL, "fsl,mpc8349-gpio")
		mpc8xxx_add_controller(np);

	for_each_compatible_node(np, NULL, "fsl,mpc8572-gpio")
		mpc8xxx_add_controller(np);

	for_each_compatible_node(np, NULL, "fsl,mpc8610-gpio")
		mpc8xxx_add_controller(np);

	return 0;
}
Beispiel #3
0
void __init mv64x60_pci_init(void)
{
	struct device_node *np;

	for_each_compatible_node(np, "pci", "marvell,mv64360-pci")
		mv64x60_add_bridge(np);
}
Beispiel #4
0
/* ************************************************************************
 *
 * Setup the architecture
 *
 */
static void __init mpc832x_rdb_setup_arch(void)
{
	struct device_node *np;

	if (ppc_md.progress)
		ppc_md.progress("mpc832x_rdb_setup_arch()", 0);

#ifdef CONFIG_PCI
	for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
		mpc83xx_add_bridge(np);

	ppc_md.pci_exclude_device = mpc83xx_exclude_device;
#endif

#ifdef CONFIG_QUICC_ENGINE
	qe_reset();

	if ((np = of_find_node_by_name(np, "par_io")) != NULL) {
		par_io_init(np);
		of_node_put(np);

		for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
			par_io_of_config(np);
	}
#endif				/* CONFIG_QUICC_ENGINE */
}
Beispiel #5
0
static void opal_i2c_create_devs(void)
{
	struct device_node *np;

	for_each_compatible_node(np, NULL, "ibm,opal-i2c")
		of_platform_device_create(np, NULL, NULL);
}
Beispiel #6
0
/* ************************************************************************
 *
 * Setup the architecture
 *
 */
static void __init mpc834x_itx_setup_arch(void)
{
	struct device_node *np;

	if (ppc_md.progress)
		ppc_md.progress("mpc834x_itx_setup_arch()", 0);

	np = of_find_node_by_type(NULL, "cpu");
	if (np != 0) {
		const unsigned int *fp =
			get_property(np, "clock-frequency", NULL);
		if (fp != 0)
			loops_per_jiffy = *fp / HZ;
		else
			loops_per_jiffy = 50000000 / HZ;
		of_node_put(np);
	}
#ifdef CONFIG_PCI
	for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
		mpc83xx_add_bridge(np);

	ppc_md.pci_exclude_device = mpc83xx_exclude_device;
#endif

#ifdef  CONFIG_ROOT_NFS
	ROOT_DEV = Root_NFS;
#else
	ROOT_DEV = Root_HDA1;
#endif
}
Beispiel #7
0
static int cpm_init_par_io(void)
{
	struct device_node *np;

	for_each_compatible_node(np, NULL, "fsl,cpm2-pario-bank")
		cpm2_gpiochip_add32(np);
	return 0;
}
static void __init mpc831x_rdb_setup_arch(void)
{
#ifdef CONFIG_PCI
	struct device_node *np;
#endif

	if (ppc_md.progress)
		ppc_md.progress("mpc831x_rdb_setup_arch()", 0);

#ifdef CONFIG_PCI
	for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
		mpc83xx_add_bridge(np);
	for_each_compatible_node(np, "pci", "fsl,mpc8314-pcie")
		mpc83xx_add_bridge(np);
#endif
	mpc831x_usb_cfg();
}
static int __init ppc4xx_pci_find_bridges(void)
{
	struct device_node *np;

	ppc_pci_flags |= PPC_PCI_ENABLE_PROC_DOMAINS | PPC_PCI_COMPAT_DOMAIN_0;

#ifdef CONFIG_PPC4xx_PCI_EXPRESS
	for_each_compatible_node(np, NULL, "ibm,plb-pciex")
		ppc4xx_probe_pciex_bridge(np);
#endif
	for_each_compatible_node(np, NULL, "ibm,plb-pcix")
		ppc4xx_probe_pcix_bridge(np);
	for_each_compatible_node(np, NULL, "ibm,plb-pci")
		ppc4xx_probe_pci_bridge(np);

	return 0;
}
void __init pq2_init_pci(void)
{
	struct device_node *np;

	ppc_md.pci_exclude_device = pq2_pci_exclude_device;

	for_each_compatible_node(np, NULL, "fsl,pq2-pci")
		pq2_pci_add_bridge(np);
}
Beispiel #11
0
static void __init storcenter_setup_arch(void)
{
	struct device_node *np;

	/* Lookup PCI host bridges */
	for_each_compatible_node(np, "pci", "mpc10x-pci")
		storcenter_add_bridge(np);

	printk(KERN_INFO "IOMEGA StorCenter\n");
}
Beispiel #12
0
static void __init linkstation_setup_arch(void)
{
	struct device_node *np;

	/* Lookup PCI host bridges */
	for_each_compatible_node(np, "pci", "mpc10x-pci")
		linkstation_add_bridge(np);

	printk(KERN_INFO "BUFFALO Network Attached Storage Series\n");
	printk(KERN_INFO "(C) 2002-2005 BUFFALO INC.\n");
}
Beispiel #13
0
/*
 * Setup the architecture
 */
static void __init mvme5100_setup_arch(void)
{
	struct device_node *np;

	if (ppc_md.progress)
		ppc_md.progress("mvme5100_setup_arch()", 0);

	for_each_compatible_node(np, "pci", "hawk-pci")
		mvme5100_add_bridge(np);

	restart = ioremap(BOARD_MODRST_REG, 4);
}
Beispiel #14
0
static int cpm_init_par_io(void)
{
	struct device_node *np;

	for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-a")
		cpm1_gpiochip_add16(np);

	for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-b")
		cpm1_gpiochip_add32(np);

	for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-c")
		cpm1_gpiochip_add16(np);

	for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-d")
		cpm1_gpiochip_add16(np);

	/* Port E uses CPM2 layout */
	for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-e")
		cpm2_gpiochip_add32(np);
	return 0;
}
Beispiel #15
0
static int __init machine_setup(void)
{
	struct device_node *serial;
	struct device_node *eth = NULL;

	for_each_compatible_node(serial, NULL, "ns16550a")
		update_clock_frequency(serial);

	if ((eth = of_find_compatible_node(eth, NULL, "opencores,ethoc")))
		update_local_mac(eth);
	return 0;
}
Beispiel #16
0
void __init amigaone_setup_arch(void)
{
	struct device_node *np;
	int phb = -ENODEV;

	/* Lookup PCI host bridges. */
	for_each_compatible_node(np, "pci", "mai-logic,articia-s")
		phb = amigaone_add_bridge(np);

	BUG_ON(phb != 0);

	if (ppc_md.progress)
		ppc_md.progress("Linux/PPC "UTS_RELEASE"\n", 0);
}
Beispiel #17
0
/*
 * Setup the architecture
 */
static void __init socrates_setup_arch(void)
{
#ifdef CONFIG_PCI
	struct device_node *np;
#endif

	if (ppc_md.progress)
		ppc_md.progress("socrates_setup_arch()", 0);

#ifdef CONFIG_PCI
	for_each_compatible_node(np, "pci", "fsl,mpc8540-pci")
		fsl_add_bridge(np, 1);
#endif
}
Beispiel #18
0
/* ************************************************************************
 *
 * Setup the architecture
 *
 */
static void __init sbc834x_setup_arch(void)
{
#ifdef CONFIG_PCI
	struct device_node *np;
#endif

	if (ppc_md.progress)
		ppc_md.progress("sbc834x_setup_arch()", 0);

#ifdef CONFIG_PCI
	for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
		mpc83xx_add_bridge(np);
#endif

}
Beispiel #19
0
static void __init mpc5121_ads_setup_arch(void)
{
#ifdef CONFIG_PCI
	struct device_node *np;
#endif
	printk(KERN_INFO "MPC5121 ADS board from Freescale Semiconductor\n");
	/*
	 * cpld regs are needed early
	 */
	mpc5121_ads_cpld_map();

#ifdef CONFIG_PCI
	for_each_compatible_node(np, "pci", "fsl,mpc5121-pci")
		mpc83xx_add_bridge(np);
#endif
}
/* ************************************************************************
 *
 * Setup the architecture
 *
 */
static void __init mpc85xx_rds_setup_arch(void)
{
	struct device_node *np;

	if (ppc_md.progress)
		ppc_md.progress("p1023_rds_setup_arch()", 0);

	/* Map BCSR area */
	np = of_find_node_by_name(NULL, "bcsr");
	if (np != NULL) {
		static u8 __iomem *bcsr_regs;

		bcsr_regs = of_iomap(np, 0);
		of_node_put(np);

		if (!bcsr_regs) {
			printk(KERN_ERR
			       "BCSR: Failed to map bcsr register space\n");
			return;
		} else {
#define BCSR15_I2C_BUS0_SEG_CLR		0x07
#define BCSR15_I2C_BUS0_SEG2		0x02
/*
 * Note: Accessing exclusively i2c devices.
 *
 * The i2c controller selects initially ID EEPROM in the u-boot;
 * but if menu configuration selects RTC support in the kernel,
 * the i2c controller switches to select RTC chip in the kernel.
 */
#ifdef CONFIG_RTC_CLASS
			/* Enable RTC chip on the segment #2 of i2c */
			clrbits8(&bcsr_regs[15], BCSR15_I2C_BUS0_SEG_CLR);
			setbits8(&bcsr_regs[15], BCSR15_I2C_BUS0_SEG2);
#endif

			iounmap(bcsr_regs);
		}
	}

#ifdef CONFIG_PCI
	for_each_compatible_node(np, "pci", "fsl,p1023-pcie")
		fsl_add_bridge(np, 0);
#endif

	mpc85xx_smp_init();
}
static void __init mpc85xx_rds_setup_arch(void)
{
	struct device_node *np;

	if (ppc_md.progress)
		ppc_md.progress("p1023_rds_setup_arch()", 0);

	/*               */
	np = of_find_node_by_name(NULL, "bcsr");
	if (np != NULL) {
		static u8 __iomem *bcsr_regs;

		bcsr_regs = of_iomap(np, 0);
		of_node_put(np);

		if (!bcsr_regs) {
			printk(KERN_ERR
			       "BCSR: Failed to map bcsr register space\n");
			return;
		} else {
#define BCSR15_I2C_BUS0_SEG_CLR		0x07
#define BCSR15_I2C_BUS0_SEG2		0x02
/*
                                           
  
                                                                
                                                               
                                                                
 */
#ifdef CONFIG_RTC_CLASS
			/*                                          */
			clrbits8(&bcsr_regs[15], BCSR15_I2C_BUS0_SEG_CLR);
			setbits8(&bcsr_regs[15], BCSR15_I2C_BUS0_SEG2);
#endif

			iounmap(bcsr_regs);
		}
	}

#ifdef CONFIG_PCI
	for_each_compatible_node(np, "pci", "fsl,p1023-pcie")
		fsl_add_bridge(np, 0);
#endif

	mpc85xx_smp_init();
}
Beispiel #22
0
/* ************************************************************************
 *
 * Setup the architecture
 *
 */
static void __init mpc832x_sys_setup_arch(void)
{
    struct device_node *np;
    u8 __iomem *bcsr_regs = NULL;

    if (ppc_md.progress)
        ppc_md.progress("mpc832x_sys_setup_arch()", 0);

    /* Map BCSR area */
    np = of_find_node_by_name(NULL, "bcsr");
    if (np) {
        struct resource res;

        of_address_to_resource(np, 0, &res);
        bcsr_regs = ioremap(res.start, res.end - res.start +1);
        of_node_put(np);
    }

#ifdef CONFIG_PCI
    for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
    mpc83xx_add_bridge(np);
#endif

#ifdef CONFIG_QUICC_ENGINE
    qe_reset();

    if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
        par_io_init(np);
        of_node_put(np);

        for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
            par_io_of_config(np);
    }

    if ((np = of_find_compatible_node(NULL, "network", "ucc_geth"))
            != NULL) {
        /* Reset the Ethernet PHYs */
#define BCSR8_FETH_RST 0x50
        clrbits8(&bcsr_regs[8], BCSR8_FETH_RST);
        udelay(1000);
        setbits8(&bcsr_regs[8], BCSR8_FETH_RST);
        iounmap(bcsr_regs);
        of_node_put(np);
    }
#endif				/* CONFIG_QUICC_ENGINE */
}
Beispiel #23
0
static void __init sbc8560_setup_arch(void)
{
#ifdef CONFIG_PCI
	struct device_node *np;
#endif

	if (ppc_md.progress)
		ppc_md.progress("sbc8560_setup_arch()", 0);

#ifdef CONFIG_CPM2
	cpm2_reset();
	init_ioports();
#endif

#ifdef CONFIG_PCI
	for_each_compatible_node(np, "pci", "fsl,mpc8540-pci")
		fsl_add_bridge(np, 1);
#endif
}
Beispiel #24
0
static void __init
sbc8641_setup_arch(void)
{
#ifdef CONFIG_PCI
	struct device_node *np;
#endif

	if (ppc_md.progress)
		ppc_md.progress("sbc8641_setup_arch()", 0);

#ifdef CONFIG_PCI
	for_each_compatible_node(np, "pci", "fsl,mpc8641-pcie")
		fsl_add_bridge(np, 0);
#endif

	printk("SBC8641 board from Wind River\n");

#ifdef CONFIG_SMP
	mpc86xx_smp_init();
#endif
}
static void __init mpc7448_hpc2_setup_arch(void)
{
	struct device_node *np;
	if (ppc_md.progress)
		ppc_md.progress("mpc7448_hpc2_setup_arch():set_bridge", 0);

	tsi108_csr_vir_base = get_vir_csrbase();

	/* setup PCI host bridge */
#ifdef CONFIG_PCI
	for_each_compatible_node(np, "pci", "tsi108-pci")
		tsi108_setup_pci(np, MPC7448HPC2_PCI_CFG_PHYS, 0);

	ppc_md.pci_exclude_device = mpc7448_hpc2_exclude_device;
	if (ppc_md.progress)
		ppc_md.progress("tsi108: resources set", 0x100);
#endif

	printk(KERN_INFO "MPC7448HPC2 (TAIGA) Platform\n");
	printk(KERN_INFO
	       "Jointly ported by Freescale and Tundra Semiconductor\n");
	printk(KERN_INFO
	       "Enabling L2 cache then enabling the HID0 prefetch engine.\n");
}
Beispiel #26
0
/* ************************************************************************
 *
 * Setup the architecture
 *
 */
static void __init mpc836x_mds_setup_arch(void)
{
	struct device_node *np;
	u8 __iomem *bcsr_regs = NULL;

	if (ppc_md.progress)
		ppc_md.progress("mpc836x_mds_setup_arch()", 0);

	/* Map BCSR area */
	np = of_find_node_by_name(NULL, "bcsr");
	if (np) {
		struct resource res;

		of_address_to_resource(np, 0, &res);
		bcsr_regs = ioremap(res.start, resource_size(&res));
		of_node_put(np);
	}

#ifdef CONFIG_PCI
	for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
		mpc83xx_add_bridge(np);
#endif

#ifdef CONFIG_QUICC_ENGINE
	qe_reset();

	if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
		par_io_init(np);
		of_node_put(np);

		for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
			par_io_of_config(np);
#ifdef CONFIG_QE_USB
		/* Must fixup Par IO before QE GPIO chips are registered. */
		par_io_config_pin(1,  2, 1, 0, 3, 0); /* USBOE  */
		par_io_config_pin(1,  3, 1, 0, 3, 0); /* USBTP  */
		par_io_config_pin(1,  8, 1, 0, 1, 0); /* USBTN  */
		par_io_config_pin(1, 10, 2, 0, 3, 0); /* USBRXD */
		par_io_config_pin(1,  9, 2, 1, 3, 0); /* USBRP  */
		par_io_config_pin(1, 11, 2, 1, 3, 0); /* USBRN  */
		par_io_config_pin(2, 20, 2, 0, 1, 0); /* CLK21  */
#endif /* CONFIG_QE_USB */
	}

	if ((np = of_find_compatible_node(NULL, "network", "ucc_geth"))
			!= NULL){
		uint svid;

		/* Reset the Ethernet PHY */
#define BCSR9_GETHRST 0x20
		clrbits8(&bcsr_regs[9], BCSR9_GETHRST);
		udelay(1000);
		setbits8(&bcsr_regs[9], BCSR9_GETHRST);

		/* handle mpc8360ea rev.2.1 erratum 2: RGMII Timing */
		svid = mfspr(SPRN_SVR);
		if (svid == 0x80480021) {
			void __iomem *immap;

			immap = ioremap(get_immrbase() + 0x14a8, 8);

			/*
			 * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
			 * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
			 */
			setbits32(immap, 0x0c003000);

			/*
			 * IMMR + 0x14AC[20:27] = 10101010
			 * (data delay for both UCC's)
			 */
			clrsetbits_be32(immap + 4, 0xff0, 0xaa0);

			iounmap(immap);
		}

		iounmap(bcsr_regs);
		of_node_put(np);
	}
#endif				/* CONFIG_QUICC_ENGINE */
}
Beispiel #27
0
/*
 * Setup the architecture
 */
static void __init mpc8309_som_setup_arch(void)
{
	void __iomem *immap;
#ifdef CONFIG_PCI
	struct device_node *np;
#endif
	if (ppc_md.progress)
		ppc_md.progress("mpc8309_som_setup_arch()", 0);

#ifdef CONFIG_PCI
	for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
		mpc83xx_add_bridge(np);
#endif
#ifdef CONFIG_USB_SUPPORT
	mpc8309_usb_cfg();
#endif

	immap = ioremap(get_immrbase(), 0x1000);

	/* set the I/O configuration for I2C2 */
	clrsetbits_be32(immap + MPC83XX_SICRL_OFFS, MPC8309_SICRL_I2C2_MASK,
			MPC8309_SICRL_I2C2);

#ifdef CONFIG_FLEXCAN_MPC830X
	/* Set I/O configuration for FlexCAN - CAN1 */
	clrsetbits_be32(immap + MPC83XX_SICRL_OFFS, MPC8309_SICRL_CAN1_MASK,
			MPC8309_SICRL_CAN1);
#if 1
	clrsetbits_be32(immap + MPC83XX_SICRL_OFFS, MPC8309_SICRL_CAN2_MASK,
			MPC8309_SICRL_CAN2);
	clrsetbits_be32(immap + MPC83XX_SICRL_OFFS, MPC8309_SICRL_CAN3_MASK,
			MPC8309_SICRL_CAN3);
	clrsetbits_be32(immap + MPC83XX_SICRL_OFFS, MPC8309_SICRL_CAN4_MASK,
			MPC8309_SICRL_CAN4);   
#endif

	/* Set CAN access control register for normal supervisor mode */
	clrsetbits_be32(immap + MPC830X_CAN_CTRL_OFFS, MPC830X_CAN1_CTRL_MASK,
			MPC830X_CAN1_SUPV_MODE);
#if 1
	clrsetbits_be32(immap + MPC830X_CAN_CTRL_OFFS, MPC830X_CAN2_CTRL_MASK,
			MPC830X_CAN2_SUPV_MODE);
	clrsetbits_be32(immap + MPC830X_CAN_CTRL_OFFS, MPC830X_CAN3_CTRL_MASK,
			MPC830X_CAN3_SUPV_MODE);
	clrsetbits_be32(immap + MPC830X_CAN_CTRL_OFFS, MPC830X_CAN4_CTRL_MASK,
			MPC830X_CAN4_SUPV_MODE);
#endif
#endif

#ifdef CONFIG_QUICC_ENGINE

#ifdef CONFIG_UCC_TDM_IO
	/* set the I/O configuration for TDM2 for SLIC */
	clrsetbits_be32(immap + MPC83XX_SICRH_OFFS, MPC8309_SICRH_TDM2_MASK,
			MPC8309_SICRH_TDM2);
	/* set up BRG3 & BRG9 for SLIC */
	clrsetbits_be32(immap + MPC83XX_SICRH_OFFS, 0x000c0000, 0x000c0000);
#endif
#ifdef CONFIG_UCC_TDM_FRAMER_IO
	/* set the I/O configuration for TDM1 for T1/E1 framer */
	clrsetbits_be32(immap + MPC83XX_SICRH_OFFS, MPC8309_SICRH_TDM1_MASK,
			MPC8309_SICRH_TDM1);
#endif

	qe_reset();
#endif				/* CONFIG_QUICC_ENGINE */

	iounmap(immap);
}
Beispiel #28
0
/**
 * ehv_bc_init - ePAPR hypervisor byte channel driver initialization
 *
 * This function is called when this module is loaded.
 */
static int __init ehv_bc_init(void)
{
	struct device_node *np;
	unsigned int count = 0; /* Number of elements in bcs[] */
	int ret;

	pr_info("ePAPR hypervisor byte channel driver\n");

	/* Count the number of byte channels */
	for_each_compatible_node(np, NULL, "epapr,hv-byte-channel")
		count++;

	if (!count)
		return -ENODEV;

	/* The array index of an element in bcs[] is the same as the tty index
	 * for that element.  If you know the address of an element in the
	 * array, then you can use pointer math (e.g. "bc - bcs") to get its
	 * tty index.
	 */
	bcs = kzalloc(count * sizeof(struct ehv_bc_data), GFP_KERNEL);
	if (!bcs)
		return -ENOMEM;

	ehv_bc_driver = alloc_tty_driver(count);
	if (!ehv_bc_driver) {
		ret = -ENOMEM;
		goto error;
	}

	ehv_bc_driver->driver_name = "ehv-bc";
	ehv_bc_driver->name = ehv_bc_console.name;
	ehv_bc_driver->type = TTY_DRIVER_TYPE_CONSOLE;
	ehv_bc_driver->subtype = SYSTEM_TYPE_CONSOLE;
	ehv_bc_driver->init_termios = tty_std_termios;
	ehv_bc_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
	tty_set_operations(ehv_bc_driver, &ehv_bc_ops);

	ret = tty_register_driver(ehv_bc_driver);
	if (ret) {
		pr_err("ehv-bc: could not register tty driver (ret=%i)\n", ret);
		goto error;
	}

	ret = platform_driver_register(&ehv_bc_tty_driver);
	if (ret) {
		pr_err("ehv-bc: could not register platform driver (ret=%i)\n",
		       ret);
		goto error;
	}

	return 0;

error:
	if (ehv_bc_driver) {
		tty_unregister_driver(ehv_bc_driver);
		put_tty_driver(ehv_bc_driver);
	}

	kfree(bcs);

	return ret;
}

#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/reboot.h>
#include <linux/pci.h>
#include <linux/kdev_t.h>
#include <linux/major.h>
#include <linux/console.h>
#include <linux/delay.h>
#include <linux/seq_file.h>
#include <linux/root_dev.h>
#include <linux/initrd.h>
#include <linux/of_platform.h>
#include <linux/of_device.h>

#include <asm/system.h>
#include <asm/atomic.h>
#include <asm/time.h>
#include <asm/io.h>
#include <asm/machdep.h>
#include <asm/ipic.h>
#include <asm/irq.h>
#include <asm/prom.h>
#include <asm/udbg.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
#include <asm/qe.h>
#include <asm/qe_ic.h>

#include "mpc83xx.h"

#define SVR_REV(svr)    (((svr) >>  0) & 0xFFFF) /* Revision field */
static void __init kmeter1_setup_arch(void)
{
	struct device_node *np;

	if (ppc_md.progress)
		ppc_md.progress("kmeter1_setup_arch()", 0);

#ifdef CONFIG_PCI
	for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
		mpc83xx_add_bridge(np);
#endif

#ifdef CONFIG_QUICC_ENGINE
	qe_reset();

	np = of_find_node_by_name(NULL, "par_io");
	if (np != NULL) {
		par_io_init(np);
		of_node_put(np);

		for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
			par_io_of_config(np);
	}

	np = of_find_compatible_node(NULL, "network", "ucc_geth");
	if (np != NULL) {
		uint svid;

		/* handle mpc8360ea rev.2.1 erratum 2: RGMII Timing */
		svid = mfspr(SPRN_SVR);
		if (SVR_REV(svid) == 0x0021) {
			struct	device_node *np_par;
			struct	resource res;
			void	__iomem *base;
			int	ret;

			np_par = of_find_node_by_name(NULL, "par_io");
			if (np_par == NULL) {
				printk(KERN_WARNING "%s couldn;t find par_io node\n",
					__func__);
				return;
			}
			/* Map Parallel I/O ports registers */
			ret = of_address_to_resource(np_par, 0, &res);
			if (ret) {
				printk(KERN_WARNING "%s couldn;t map par_io registers\n",
					__func__);
				return;
			}
			base = ioremap(res.start, res.end - res.start + 1);

			/*
			 * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
			 * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
			 */
			setbits32((base + 0xa8), 0x0c003000);

			/*
			 * IMMR + 0x14AC[20:27] = 10101010
			 * (data delay for both UCC's)
			 */
			clrsetbits_be32((base + 0xac), 0xff0, 0xaa0);
			iounmap(base);
			of_node_put(np_par);
		}
		of_node_put(np);
	}
#endif				/* CONFIG_QUICC_ENGINE */
}