t_stat fp_unpack_two (uint32 dad, uint32 sad, FPA *dfp, FPA *sfp) { t_stat r; if ((r = fp_unpack (dad, dfp)) != SCPE_OK) /* unpack dst */ return r; if ((r = fp_unpack (sad, sfp)) != SCPE_OK) /* unpack src */ return r; if (sfp->lnt != dfp->lnt) /* lnts must be equal */ return STOP_FPUNL; return SCPE_OK; }
t_stat cpu_signal (uint32 IR, uint32 intrq) { t_stat reason = SCPE_OK; OPS op; OP a,b,c,d,p1,p2,p3,p4,m1,m2,wr,wi; uint32 entry, v, idx1, idx2; int32 exc, exd; entry = IR & 017; /* mask to entry point */ if (op_signal [entry] != OP_N) { reason = cpu_ops (op_signal [entry], op, intrq); /* get instruction operands */ if (reason != SCPE_OK) /* evaluation failed? */ return reason; /* return reason for failure */ } switch (entry) { /* decode IR<3:0> */ case 000: /* BITRV (OP_AAKK) */ /* BITRV * bit reversal for FFT * JSB BITRV * DEF ret(,I) return address * DEF vect,I base address of array * DEF idx,I index bitmap to be reversed (one-based) * DEF nbits,I number of bits of index * * Given a complex*8 vector of nbits (power of 2), this calculates: * swap( vect[idx], vect[rev(idx)]) where rev(i) is the bitreversed value of i */ sig_bitrev(op[1].word, op[1].word+2, op[2].word-1, op[3].word, 4); PR = op[0].word & VAMASK; break; case 001: /* BTRFY (OP_AAFFKK) */ /* BTRFY - butterfly operation * JSB BTRFY * DEF ret(,I) return address * DEF vect(,I) complex*8 vector * DEF wr,I real part of W * DEF wi,I imag part of W * DEF node,I index of 1st op (1 based) * DEF lmax,I offset to 2nd op (0 based) */ sig_btrfy(op[1].word, op[1].word+2, op[2], op[3], 2*(op[4].word-1), 2*op[5].word); PR = op[0].word & VAMASK; break; case 002: /* UNSCR (OP_AAFFKK) */ /* UNSCR unscramble for phasor MPY * JSB UNSCR * DEF ret(,I) * DEF vector,I * DEF WR * DEF WI * DEF idx1,I * DEF idx2,I */ v = op[1].word; idx1 = 2 * (op[4].word - 1); idx2 = 2 * (op[5].word - 1); wr = op[2]; /* read WR */ wi = op[3]; /* read WI */ p1 = ReadOp(RE(v + idx1), fp_f); /* S1 VR[idx1] */ p2 = ReadOp(RE(v + idx2), fp_f); /* S2 VR[idx2] */ p3 = ReadOp(IM(v + idx1), fp_f); /* S9 VI[idx1] */ p4 = ReadOp(IM(v + idx2), fp_f); /* S10 VI[idx2] */ c = sig_scadd(000, TRUE, p3, p4); /* S5,6 0.5*(p3+p4) */ d = sig_scadd(020, TRUE, p2, p1); /* S7,8 0.5*(p2-p1) */ sig_cmul(&m1, &m2, wr, wi, c, d); /* (WR,WI) * (c,d) */ c = sig_scadd(000, TRUE, p1, p2); /* 0.5*(p1+p2) */ d = sig_scadd(020, TRUE, p3, p4); /* 0.5*(p3-p4) */ (void)fp_exec(000, &p1, c, m1); /* VR[idx1] := 0.5*(p1+p2) + real(W*(c,d)) */ WriteOp(RE(v + idx1), p1, fp_f); (void)fp_exec(000, &p2, d, m2); /* VI[idx1] := 0.5*(p3-p4) + imag(W*(c,d)) */ WriteOp(IM(v + idx1), p2, fp_f); (void)fp_exec(020, &p1, c, m1); /* VR[idx2] := 0.5*(p1+p2) - imag(W*(c,d)) */ WriteOp(RE(v + idx2), p1, fp_f); (void)fp_exec(020, &p2, d, m2); /* VI[idx2] := 0.5*(p3-p4) - imag(W*(c,d)) */ WriteOp(IM(v + idx2), p2, fp_f); PR = op[0].word & VAMASK; break; case 003: /* PRSCR (OP_AAFFKK) */ /* PRSCR unscramble for phasor MPY * JSB PRSCR * DEF ret(,I) * DEF vector,I * DEF WR * DEF WI * DEF idx1,I * DEF idx2,I */ v = op[1].word; idx1 = 2 * (op[4].word - 1); idx2 = 2 * (op[5].word - 1); wr = op[2]; /* read WR */ wi = op[3]; /* read WI */ p1 = ReadOp(RE(v + idx1), fp_f); /* VR[idx1] */ p2 = ReadOp(RE(v + idx2), fp_f); /* VR[idx2] */ p3 = ReadOp(IM(v + idx1), fp_f); /* VI[idx1] */ p4 = ReadOp(IM(v + idx2), fp_f); /* VI[idx2] */ c = sig_scadd(020, FALSE, p1, p2); /* p1-p2 */ d = sig_scadd(000, FALSE, p3, p4); /* p3+p4 */ sig_cmul(&m1,&m2, wr, wi, c, d); /* (WR,WI) * (c,d) */ c = sig_scadd(000, FALSE, p1, p2); /* p1+p2 */ d = sig_scadd(020, FALSE, p3,p4); /* p3-p4 */ (void)fp_exec(020, &p1, c, m2); /* VR[idx1] := (p1-p2) - imag(W*(c,d)) */ WriteOp(RE(v + idx1), p1, fp_f); (void)fp_exec(000, &p2, d, m1); /* VI[idx1] := (p3-p4) + real(W*(c,d)) */ WriteOp(IM(v + idx1), p2, fp_f); (void)fp_exec(000, &p1, c, m2); /* VR[idx2] := (p1+p2) + imag(W*(c,d)) */ WriteOp(RE(v + idx2), p1, fp_f); (void)fp_exec(020, &p2, m1, d); /* VI[idx2] := imag(W*(c,d)) - (p3-p4) */ WriteOp(IM(v + idx2), p2, fp_f); PR = op[0].word & VAMASK; break; case 004: /* BITR1 (OP_AAAKK) */ /* BITR1 * bit reversal for FFT, alternative version * JSB BITR1 * DEF ret(,I) return address if already swapped * DEF revect,I base address of real vect * DEF imvect,I base address of imag vect * DEF idx,I index bitmap to be reversed (one-based) * DEF nbits,I number of bits of index * * Given a complex*8 vector of nbits (power of 2), this calculates: * swap( vect[idx], vect[rev(idx)]) where rev(i) is the bitreversed value of i * * difference to BITRV is that BITRV uses complex*8, and BITR1 uses separate real*4 * vectors for Real and Imag parts */ sig_bitrev(op[1].word, op[2].word, op[3].word-1, op[4].word, 2); PR = op[0].word & VAMASK; break; case 005: /* BTRF1 (OP_AAAFFKK) */ /* BTRF1 - butterfly operation with real*4 vectors * JSB BTRF1 * DEF ret(,I) return address * DEF rvect,I real part of vector * DEF ivect,I imag part of vector * DEF wr,I real part of W * DEF wi,I imag part of W * DEF node,I index (1 based) * DEF lmax,I index (0 based) */ sig_btrfy(op[1].word, op[2].word, op[3], op[4], op[5].word-1, op[6].word); PR = op[0].word & VAMASK; break; case 006: /* .CADD (OP_AAA) */ /* .CADD Complex addition * JSB .CADD * DEF result,I * DEF oprd1,I * DEF oprd2,I * complex addition is: (a+bi) + (c+di) => (a+c) + (b+d)i */ sig_caddsub(000,op); break; case 007: /* .CSUB (OP_AAA) */ /* .CSUB Complex subtraction * JSB .CSUB * DEF result,I * DEF oprd1,I * DEF oprd2,I * complex subtraction is: (a+bi) - (c+di) => (a - c) + (b - d)i */ sig_caddsub(020,op); break; case 010: /* .CMUL (OP_AAA) */ /* .CMPY Complex multiplication * call: * JSB .CMPY * DEF result,I * DEF oprd1,I * DEF oprd2,I * complex multiply is: (a+bi)*(c+di) => (ac-bd) + (ad+bc)i */ a = ReadOp(RE(op[1].word), fp_f); /* read 1st op */ b = ReadOp(IM(op[1].word), fp_f); c = ReadOp(RE(op[2].word), fp_f); /* read 2nd op */ d = ReadOp(IM(op[2].word), fp_f); sig_cmul(&p1, &p2, a, b, c, d); WriteOp(RE(op[0].word), p1, fp_f); /* write real result */ WriteOp(IM(op[0].word), p2, fp_f); /* write imag result */ break; case 011: /* .CDIV (OP_AAA) */ /* .CDIV Complex division * call: * JSB .CDIV * DEF result,I * DEF oprd1,I * DEF oprd2,I * complex division is: (a+bi)/(c+di) => ((ac+bd) + (bc-ad)i)/(c^2+d^2) */ a = ReadOp(RE(op[1].word), fp_f); /* read 1st op */ b = ReadOp(IM(op[1].word), fp_f); c = ReadOp(RE(op[2].word), fp_f); /* read 2nd op */ d = ReadOp(IM(op[2].word), fp_f); (void)fp_unpack (NULL, &exc, c, fp_f); /* get exponents */ (void)fp_unpack (NULL, &exd, d, fp_f); if (exc < exd) { /* ensure c/d < 1 */ p1 = a; a = c; c = p1; /* swap dividend and divisor */ p1 = b; b = d; d = p1; } (void)fp_exec(060, &p1, d, c); /* p1,accu := d/c */ (void)fp_exec(044, ACCUM, d, NOP); /* ACCUM := dd/c */ (void)fp_exec(004, &p2, c, NOP); /* p2 := c + dd/c */ (void)fp_exec(040, ACCUM, b, p1); /* ACCUM := bd/c */ (void)fp_exec(004, ACCUM, a, NOP); /* ACCUM := a + bd/c */ (void)fp_exec(070, &p3, NOP, p2); /* p3 := (a+bd/c)/(c+dd/c) == (ac+bd)/(cc+dd) */ WriteOp(RE(op[0].word), p3, fp_f); /* Write real result */ (void)fp_exec(040, ACCUM, a, p1); /* ACCUM := ad/c */ (void)fp_exec(030, ACCUM, NOP, b); /* ACCUM := ad/c - b */ if (exd < exc) { /* was not swapped? */ (void)fp_exec(024, ACCUM, zero, NOP); /* ACCUM := -ACCUM */ } (void)fp_exec(070, &p3, NOP, p2); /* p3 := (b-ad/c)/(c+dd/c) == (bc-ad)/cc+dd) */ WriteOp(IM(op[0].word), p3, fp_f); /* Write imag result */ break; case 012: /* CONJG (OP_AAA) */ /* CONJG build A-Bi from A+Bi * call: * JSB CONJG * DEF RTN * DEF res,I result * DEF arg,I input argument */ a = ReadOp(RE(op[2].word), fp_f); /* read real */ b = ReadOp(IM(op[2].word), fp_f); /* read imag */ (void)fp_pcom(&b, fp_f); /* negate imag */ WriteOp(RE(op[1].word), a, fp_f); /* write real */ WriteOp(IM(op[1].word), b, fp_f); /* write imag */ break; case 013: /* ..CCM (OP_A) */ /* ..CCM complement complex * call * JSB ..CCM * DEF arg * build (-RE,-IM) */ v = op[0].word; a = ReadOp(RE(v), fp_f); /* read real */ b = ReadOp(IM(v), fp_f); /* read imag */ (void)fp_pcom(&a, fp_f); /* negate real */ (void)fp_pcom(&b, fp_f); /* negate imag */ WriteOp(RE(v), a, fp_f); /* write real */ WriteOp(IM(v), b, fp_f); /* write imag */ break; case 014: /* AIMAG (OP_AA) */ /* AIMAG return the imaginary part in AB * JSB AIMAG * DEF *+2 * DEF cplx(,I) * returns: AB imaginary part of complex number */ a = ReadOp(IM(op[1].word), fp_f); /* read imag */ AR = a.fpk[0]; /* move MSB to A */ BR = a.fpk[1]; /* move LSB to B */ break; case 015: /* CMPLX (OP_AFF) */ /* CMPLX form a complex number * JSB CMPLX * DEF *+4 * DEF result,I complex number * DEF repart,I real value * DEF impart,I imaginary value */ WriteOp(RE(op[1].word), op[2], fp_f); /* write real part */ WriteOp(IM(op[1].word), op[3], fp_f); /* write imag part */ break; case 017: /* [slftst] (OP_N) */ XR = 2; /* firmware revision */ SR = 0102077; /* test passed code */ PR = (PR + 1) & VAMASK; /* P+2 return for firmware w/SIGNAL1000 */ break; case 016: /* invalid */ default: /* others unimplemented */ reason = STOP (cpu_ss_unimpl); } return reason; }