int mvsmr_init_fpga(void)
{
fpga_init();
fpga_add(fpga_xilinx, &spartan3);
return 1;
}
int board_init(void)
{
#ifdef CONFIG_FPGA
u32 idcode;
idcode = zynq_slcr_get_idcode();
switch (idcode) {
case XILINX_ZYNQ_7010:
fpga = fpga010;
break;
case XILINX_ZYNQ_7020:
fpga = fpga020;
break;
case XILINX_ZYNQ_7030:
fpga = fpga030;
break;
case XILINX_ZYNQ_7045:
fpga = fpga045;
break;
}
#endif
icache_enable();
#ifdef CONFIG_FPGA
fpga_init();
fpga_add(fpga_xilinx, &fpga);
#endif
return 0;
}
int board_init(void)
{
/* temporary hack to clear pending irqs before Linux as it
will hang Linux */
XIo_Out32(0xe0001014, 0x26d);
/* temporary hack to take USB out of reset til the is fixed
in Linux */
XIo_Out32(0xe000a204, 0x80);
XIo_Out32(0xe000a208, 0x80);
XIo_Out32(0xe000a040, 0x80);
XIo_Out32(0xe000a040, 0x00);
XIo_Out32(0xe000a040, 0x80);
icache_enable();
#ifdef CONFIG_FPGA
fpga_init();
fpga_add(fpga_xilinx, &fpga);
#endif
return 0;
}
/* Add device descriptor to FPGA device table */
void board_fpga_add(void)
{
int i;
fpga_init();
for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
fpga_add(fpga_altera, &altera_fpga[i]);
}
int mergerbox_init_fpga(void)
{
debug("Initialize FPGA interface\n");
fpga_init();
fpga_add(fpga_altera, &cyclone2);
return 1;
}
int mvblm7_init_fpga(void)
{
fpga_debug("Initialize FPGA interface\n");
fpga_init();
fpga_add(fpga_altera, &cyclone2);
fpga_config_fn(0, 1, 0);
udelay(60);
return 1;
}
int qong_fpga_init(void)
{
int i;
fpga_init();
for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
fpga_add(fpga_lattice, &qong_fpga[i]);
}
return 0;
}
int mvblm7_init_fpga(void)
{
fpga_debug("Initialize FPGA interface (reloc 0x%.8lx)\n",
gd->reloc_off);
fpga_init(gd->reloc_off);
fpga_add(fpga_altera, &cyclone2);
fpga_config_fn(0, 1, 0);
udelay(60);
return 1;
}
/* Initialize the FPGA */
static void mt_ventoux_init_fpga(void)
{
fpga_pre_config_fn(0);
/* Setting CS1 for FPGA access */
enable_gpmc_cs_config(gpmc_fpga, &gpmc_cfg->cs[1],
FPGA_BASE_ADDR, GPMC_SIZE_128M);
fpga_init();
fpga_add(fpga_xilinx, &fpga);
}
int board_init(void)
{
printf("EL Level:\tEL%d\n", current_el());
#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
fpga_init();
/* FIXME FPGA size/id will be handled via SMCs */
fpga_add(fpga_xilinx, &zynqmppl);
#endif
return 0;
}
/*
* Initialize the fpga. Return 1 on success, 0 on failure.
*/
int pmc440_init_fpga(void)
{
char *s;
debug("%s:%d: Initialize FPGA interface (relocation offset = 0x%.8lx)\n",
__FUNCTION__, __LINE__, gd->reloc_off);
fpga_init(gd->reloc_off);
fpga_serialslave_init ();
debug("%s:%d: Adding fpga 0\n", __FUNCTION__, __LINE__);
fpga_add (fpga_xilinx, &fpga[0]);
/* NGCC only */
if ((s = getenv("bd_type")) && !strcmp(s, "ngcc")) {
ngcc_fpga_serialslave_init ();
debug("%s:%d: Adding fpga 1\n", __FUNCTION__, __LINE__);
fpga_add (fpga_xilinx, &fpga[1]);
}
return 0;
}
/* return FPGA_SUCCESS on success, else FPGA_FAIL
*/
int mvblx_init_fpga(void)
{
fpga_debug("Initializing FPGA interface\n");
fpga_init();
fpga_add(fpga_altera, &cyclone2);
if (gpio_request(GPIO_DCLK, "dclk") ||
gpio_request(GPIO_nSTATUS, "nStatus") ||
#ifndef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
gpio_request(GPIO_CONF_DONE, "conf_done") ||
#endif
gpio_request(GPIO_nCONFIG, "nConfig") ||
gpio_request(GPIO_DATA0, "data0") ||
gpio_request(GPIO_DATA1, "data1") ||
gpio_request(GPIO_DATA2, "data2") ||
gpio_request(GPIO_DATA3, "data3") ||
gpio_request(GPIO_DATA4, "data4") ||
gpio_request(GPIO_DATA5, "data5") ||
gpio_request(GPIO_DATA6, "data6") ||
gpio_request(GPIO_DATA7, "data7")) {
printf("%s: error requesting GPIOs.", __func__);
return FPGA_FAIL;
}
/* set up outputs */
gpio_direction_output(GPIO_DCLK, 0);
gpio_direction_output(GPIO_nCONFIG, 0);
gpio_direction_output(GPIO_DATA0, 0);
gpio_direction_output(GPIO_DATA1, 0);
gpio_direction_output(GPIO_DATA2, 0);
gpio_direction_output(GPIO_DATA3, 0);
gpio_direction_output(GPIO_DATA4, 0);
gpio_direction_output(GPIO_DATA5, 0);
gpio_direction_output(GPIO_DATA6, 0);
gpio_direction_output(GPIO_DATA7, 0);
/* NB omap_free_gpio() resets to an input, so we can't
* free ie. nCONFIG, or else the FPGA would reset
* Q: presumably gpio_free() has the same effect?
*/
/* set up inputs */
gpio_direction_input(GPIO_nSTATUS);
#ifndef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
gpio_direction_input(GPIO_CONF_DONE);
#endif
fpga_config_fn(0, 1, 0);
udelay(60);
return FPGA_SUCCESS;
}
int board_init(void)
{
#if defined(CONFIG_ENV_IS_IN_EEPROM) && !defined(CONFIG_SPL_BUILD)
unsigned char eepromsel = CONFIG_SYS_I2C_MUX_EEPROM_SEL;
#endif
#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
u32 idcode;
idcode = zynq_slcr_get_idcode();
switch (idcode) {
case XILINX_ZYNQ_7010:
fpga = fpga010;
break;
case XILINX_ZYNQ_7015:
fpga = fpga015;
break;
case XILINX_ZYNQ_7020:
fpga = fpga020;
break;
case XILINX_ZYNQ_7030:
fpga = fpga030;
break;
case XILINX_ZYNQ_7035:
fpga = fpga035;
break;
case XILINX_ZYNQ_7045:
fpga = fpga045;
break;
case XILINX_ZYNQ_7100:
fpga = fpga100;
break;
}
#endif
#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
fpga_init();
fpga_add(fpga_xilinx, &fpga);
#endif
#if defined(CONFIG_ENV_IS_IN_EEPROM) && !defined(CONFIG_SPL_BUILD)
if (eeprom_write(CONFIG_SYS_I2C_MUX_ADDR, 0, &eepromsel, 1))
puts("I2C:EEPROM selection failed\n");
#endif
/* Added by MYIR for MYS-XC7Z010 */
myir_board_init();
return 0;
}
int board_init(void)
{
#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
u32 idcode;
idcode = zynq_slcr_get_idcode();
switch (idcode) {
case XILINX_ZYNQ_7007S:
fpga = fpga007s;
break;
case XILINX_ZYNQ_7010:
fpga = fpga010;
break;
case XILINX_ZYNQ_7012S:
fpga = fpga012s;
break;
case XILINX_ZYNQ_7014S:
fpga = fpga014s;
break;
case XILINX_ZYNQ_7015:
fpga = fpga015;
break;
case XILINX_ZYNQ_7020:
fpga = fpga020;
break;
case XILINX_ZYNQ_7030:
fpga = fpga030;
break;
case XILINX_ZYNQ_7035:
fpga = fpga035;
break;
case XILINX_ZYNQ_7045:
fpga = fpga045;
break;
case XILINX_ZYNQ_7100:
fpga = fpga100;
break;
}
#endif
#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
fpga_init();
fpga_add(fpga_xilinx, &fpga);
#endif
return 0;
}
int board_init(void)
{
#if defined(CONFIG_ENV_IS_IN_EEPROM) && !defined(CONFIG_SPL_BUILD)
unsigned char eepromsel = CONFIG_SYS_I2C_MUX_EEPROM_SEL;
#endif
#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
u32 idcode;
idcode = zynq_slcr_get_idcode();
switch (idcode) {
case XILINX_ZYNQ_7010:
fpga = fpga010;
break;
case XILINX_ZYNQ_7015:
fpga = fpga015;
break;
case XILINX_ZYNQ_7020:
fpga = fpga020;
break;
case XILINX_ZYNQ_7030:
fpga = fpga030;
break;
case XILINX_ZYNQ_7045:
fpga = fpga045;
break;
case XILINX_ZYNQ_7100:
fpga = fpga100;
break;
}
#endif
/*
* temporary hack to clear pending irqs before Linux as it
* will hang Linux
*/
writel(0x26d, 0xe0001014);
#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
fpga_init();
fpga_add(fpga_xilinx, &fpga);
#endif
#if defined(CONFIG_ENV_IS_IN_EEPROM) && !defined(CONFIG_SPL_BUILD)
if (eeprom_write(CONFIG_SYS_I2C_MUX_ADDR, 0, &eepromsel, 1))
puts("I2C:EEPROM selection failed\n");
#endif
return 0;
}
/*
* Initialize the fpga. Return 1 on success, 0 on failure.
*/
void APF27_init_fpga(void)
{
int i;
apf27_fpga_setup();
fpga_init();
for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
debug("%s:%d: Adding fpga %d\n", __func__, __LINE__, i);
fpga_add(fpga_xilinx, &fpga[i]);
}
return;
}
int board_init(void)
{
#ifdef CONFIG_FPGA
u32 idcode;
idcode = zynq_slcr_get_idcode();
switch (idcode) {
case XILINX_ZYNQ_7010:
fpga = fpga010;
break;
case XILINX_ZYNQ_7020:
fpga = fpga020;
break;
case XILINX_ZYNQ_7030:
fpga = fpga030;
break;
case XILINX_ZYNQ_7045:
fpga = fpga045;
break;
case XILINX_ZYNQ_7100:
fpga = fpga100;
break;
}
#endif
/* temporary hack to clear pending irqs before Linux as it
* will hang Linux
*/
writel(0x26d, 0xe0001014);
/* temporary hack to take USB out of reset til the is fixed
* in Linux
*/
writel(0x80, 0xe000a204);
writel(0x80, 0xe000a208);
writel(0x80, 0xe000a040);
writel(0x00, 0xe000a040);
writel(0x80, 0xe000a040);
// icache_enable();
#ifdef CONFIG_FPGA
fpga_init();
fpga_add(fpga_xilinx, &fpga);
#endif
return 0;
}
/* Initialize the FPGA */
void balloon3_init_fpga(void)
{
fpga_init();
fpga_add(fpga_xilinx, &fpga);
}
