PUBLIC void arch_init(void)
{
#ifdef CONFIG_APIC
/*
* this is setting kernel segments to cover most of the phys memory. The
* value is high enough to reach local APIC nad IOAPICs before paging is
* turned on.
*/
prot_set_kern_seg_limit(0xfff00000);
reload_ds();
#endif
idt_init();
tss_init(&tss, &k_boot_stktop, 0);
acpi_init();
#if defined(CONFIG_APIC) && !defined(CONFIG_SMP)
if (config_no_apic) {
BOOT_VERBOSE(printf("APIC disabled, using legacy PIC\n"));
}
else if (!apic_single_cpu_init()) {
BOOT_VERBOSE(printf("APIC not present, using legacy PIC\n"));
}
#endif
fpu_init();
}
void fpu_handler(void)
{
task_t* task = per_core(current_task);
uint32_t core_id = CORE_ID;
task->flags |= TASK_FPU_USED;
if (!(task->flags & TASK_FPU_INIT)) {
// use the FPU at the first time => Initialize FPU
fpu_init(&task->fpu);
task->flags |= TASK_FPU_INIT;
}
if (readyqueues[core_id].fpu_owner == task->id)
return;
spinlock_irqsave_lock(&readyqueues[core_id].lock);
// did another already use the the FPU? => save FPU state
if (readyqueues[core_id].fpu_owner) {
save_fpu_state(&(task_table[readyqueues[core_id].fpu_owner].fpu));
task_table[readyqueues[core_id].fpu_owner].flags &= ~TASK_FPU_USED;
}
readyqueues[core_id].fpu_owner = task->id;
spinlock_irqsave_unlock(&readyqueues[core_id].lock);
restore_fpu_state(&task->fpu);
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void)
{
#ifndef __CODE_RED
#ifdef CORE_M4
fpu_init();
#endif
#endif
#if (CLOCK_SETUP) /* Clock Setup */
LPC_SC->SCS = SCS_Val;
if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */
while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */
}
LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for sysclk/PLL0*/
#if (PLL0_SETUP)
LPC_SC->PLL0CFG = PLL0CFG_Val;
LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */
LPC_SC->PLL0FEED = 0xAA;
LPC_SC->PLL0FEED = 0x55;
while (!(LPC_SC->PLL0STAT & (1<<10)));/* Wait for PLOCK0 */
#endif
#if (PLL1_SETUP)
LPC_SC->PLL1CFG = PLL1CFG_Val;
LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */
LPC_SC->PLL1FEED = 0xAA;
LPC_SC->PLL1FEED = 0x55;
while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */
#endif
LPC_SC->CCLKSEL = CCLKSEL_Val; /* Setup Clock Divider */
LPC_SC->USBCLKSEL = USBCLKSEL_Val; /* Setup USB Clock Divider */
LPC_SC->EMCCLKSEL = EMCCLKSEL_Val; /* EMC Clock Selection */
LPC_SC->SPIFICLKSEL = SPIFICLKSEL_Val; /* SPIFI Clock Selection */
LPC_SC->PCLKSEL = PCLKSEL_Val; /* Peripheral Clock Selection */
LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */
#endif
LPC_SC->PBOOST |= 0x03; /* Power Boost control */
#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */
LPC_SC->FLASHCFG = FLASHCFG_Val|0x03A;
#endif
#ifndef __CODE_RED
#ifdef __RAM_MODE__
SCB->VTOR = 0x10000000 & 0x3FFFFF80;
#else
SCB->VTOR = 0x00000000 & 0x3FFFFF80;
#endif
#endif
SystemCoreClockUpdate();
}
int32_t kernel_main(multiboot_t *mboot_ptr)
{
textmode_init();
printf(" _____ _ _ ____ _____ \n / ____(_) | | / __ \\ / ____|\n | (___ _ _ __ ___ _ __ | | ___| | | | (___ \n \\___ \\| | '_ ` _ \\| '_ \\| |/ _ \\ | | |\\___ \\ \n ____) | | | | | | | |_) | | __/ |__| |____) |\n |_____/|_|_| |_| |_| .__/|_|\\___|\\____/|_____/ \n | | \n |_| \n");
textmode_set_colors(COLOR_RED, COLOR_BLACK);
textmode_move_cursor(19, 6);
printf("Version %i.%i.%i", VERSION_MAJOR, VERSION_MINOR, VERSION_BUILD);
textmode_move_cursor(19, 7);
printf("Built %s", VERSION_DATE);
textmode_set_colors(COLOR_GREEN, COLOR_BLACK);
textmode_move_cursor(41, 6);
printf("Written by Joe Biellik");
textmode_set_colors(COLOR_LTGRAY, COLOR_BLACK);
textmode_move_cursor(0, 9);
fpu_init();
gdt_init();
idt_init();
__asm __volatile__("sti"); // Start interrupts
pit_init();
serial_init();
// Test serial
int8_t buffer[50];
sprintf(buffer, "SimpleOS %i.%i.%i (%s)\n", VERSION_MAJOR, VERSION_MINOR, VERSION_BUILD, VERSION_DATE);
serial_write(SERIAL_PORT_A, buffer);
// Test RTC
datetime_t *dt = 0;
rtc_get(dt);
printf("Started at %02i-%02i-%02i %02i:%02i:%02i\n\n", dt->year, dt->month, dt->day, dt->hour, dt->min, dt->sec);
// Test CPU
cpu_detect();
printf("\n");
// Test PCI
pci_scan();
for (;;);
return 0x12345678;
}
void
ia32_initreg(void)
{
int i;
CPU_STATSAVE.cpu_inst_default.seg_base = (UINT32)-1;
CPU_EDX = (CPU_FAMILY << 8) | (CPU_MODEL << 4) | CPU_STEPPING;
CPU_EFLAG = 2;
CPU_CR0 = CPU_CR0_CD | CPU_CR0_NW;
#if defined(USE_FPU)
CPU_CR0 &= ~CPU_CR0_EM;
CPU_CR0 |= CPU_CR0_ET;
#else
CPU_CR0 |= CPU_CR0_EM | CPU_CR0_NE;
CPU_CR0 &= ~(CPU_CR0_MP | CPU_CR0_ET);
#endif
CPU_MXCSR = 0x1f80;
CPU_GDTR_BASE = 0x0;
CPU_GDTR_LIMIT = 0xffff;
CPU_IDTR_BASE = 0x0;
CPU_IDTR_LIMIT = 0xffff;
CPU_LDTR_BASE = 0x0;
CPU_LDTR_LIMIT = 0xffff;
CPU_TR_BASE = 0x0;
CPU_TR_LIMIT = 0xffff;
CPU_STATSAVE.cpu_regs.dr[6] = 0xffff1ff0;
for (i = 0; i < CPU_SEGREG_NUM; ++i) {
segdesc_init(i, 0, &CPU_STAT_SREG(i));
}
LOAD_SEGREG(CPU_CS_INDEX, 0xf000);
CPU_STAT_CS_BASE = 0xffff0000;
CPU_EIP = 0xfff0;
CPU_ADRSMASK = 0x000fffff;
tlb_init();
#if defined(USE_FPU)
fpu_init();
#endif
}
void
ia32_initreg(void)
{
int i;
CPU_STATSAVE.cpu_inst_default.seg_base = (UINT32)-1;
CPU_EDX = (CPU_FAMILY << 8) | (CPU_MODEL << 4) | CPU_STEPPING;
CPU_EFLAG = 2;
CPU_CR0 = CPU_CR0_CD | CPU_CR0_NW | CPU_CR0_ET;
#if defined(USE_FPU)
CPU_CR0 |= CPU_CR0_EM | CPU_CR0_NE;
CPU_CR0 &= ~CPU_CR0_MP;
#else
CPU_CR0 |= CPU_CR0_ET;
#endif
CPU_MXCSR = 0x1f80;
CPU_GDTR_LIMIT = 0xffff;
CPU_IDTR_LIMIT = 0xffff;
#if CPU_FAMILY == 4
CPU_STATSAVE.cpu_regs.dr[6] = 0xffff1ff0;
#elif CPU_FAMILY >= 5
CPU_STATSAVE.cpu_regs.dr[6] = 0xffff0ff0;
CPU_STATSAVE.cpu_regs.dr[7] = 0x00000400;
#endif
for (i = 0; i < CPU_SEGREG_NUM; ++i) {
CPU_STAT_SREG_INIT(i);
}
CPU_LDTR_LIMIT = 0xffff;
CPU_TR_LIMIT = 0xffff;
CPU_SET_SEGREG(CPU_CS_INDEX, 0xf000);
CPU_EIP = 0xfff0;
CPU_ADRSMASK = 0x000fffff;
tlb_init();
#if defined(USE_FPU)
fpu_init();
#endif
}
void bsp_finish_booting(void)
{
int i;
#if SPROFILE
sprofiling = 0; /* we're not profiling until instructed to */
#endif /* SPROFILE */
cprof_procs_no = 0; /* init nr of hash table slots used */
cpu_identify();
vm_running = 0;
krandom.random_sources = RANDOM_SOURCES;
krandom.random_elements = RANDOM_ELEMENTS;
/* MINIX is now ready. All boot image processes are on the ready queue.
* Return to the assembly code to start running the current process.
*/
/* it should point somewhere */
get_cpulocal_var(bill_ptr) = get_cpulocal_var_ptr(idle_proc);
get_cpulocal_var(proc_ptr) = get_cpulocal_var_ptr(idle_proc);
announce(); /* print MINIX startup banner */
/*
* we have access to the cpu local run queue, only now schedule the processes.
* We ignore the slots for the former kernel tasks
*/
for (i=0; i < NR_BOOT_PROCS - NR_TASKS; i++) {
RTS_UNSET(proc_addr(i), RTS_PROC_STOP);
}
/*
* enable timer interrupts and clock task on the boot CPU
*/
if (boot_cpu_init_timer(system_hz)) {
panic("FATAL : failed to initialize timer interrupts, "
"cannot continue without any clock source!");
}
fpu_init();
/* Warnings for sanity checks that take time. These warnings are printed
* so it's a clear warning no full release should be done with them
* enabled.
*/
#if DEBUG_SCHED_CHECK
FIXME("DEBUG_SCHED_CHECK enabled");
#endif
#if DEBUG_VMASSERT
FIXME("DEBUG_VMASSERT enabled");
#endif
#if DEBUG_PROC_CHECK
FIXME("PROC check enabled");
#endif
DEBUGEXTRA(("cycles_accounting_init()... "));
cycles_accounting_init();
DEBUGEXTRA(("done\n"));
#ifdef CONFIG_SMP
cpu_set_flag(bsp_cpu_id, CPU_IS_READY);
machine.processors_count = ncpus;
machine.bsp_id = bsp_cpu_id;
#else
machine.processors_count = 1;
machine.bsp_id = 0;
#endif
/* Kernel may no longer use bits of memory as VM will be running soon */
kernel_may_alloc = 0;
switch_to_user();
NOT_REACHABLE;
}
