/** * gelic_card_get_next_tx_descr - returns the next available tx descriptor * @card: device structure to get descriptor from * * returns the address of the next descriptor, or NULL if not available. */ static struct gelic_descr * gelic_card_get_next_tx_descr(struct gelic_card *card) { if (!card->tx_chain.head) return NULL; /* see if the next descriptor is free */ if (card->tx_chain.tail != card->tx_chain.head->next && gelic_descr_get_status(card->tx_chain.head) == GELIC_DESCR_DMA_NOT_IN_USE) return card->tx_chain.head; else return NULL; }
/** * gelic_descr_prepare_rx - reinitializes a rx descriptor * @card: card structure * @descr: descriptor to re-init * * return 0 on success, <0 on failure * * allocates a new rx skb, iommu-maps it and attaches it to the descriptor. * Activate the descriptor state-wise */ static int gelic_descr_prepare_rx(struct gelic_card *card, struct gelic_descr *descr) { int offset; unsigned int bufsize; if (gelic_descr_get_status(descr) != GELIC_DESCR_DMA_NOT_IN_USE) dev_info(ctodev(card), "%s: ERROR status\n", __func__); /* we need to round up the buffer size to a multiple of 128 */ bufsize = ALIGN(GELIC_NET_MAX_MTU, GELIC_NET_RXBUF_ALIGN); /* and we need to have it 128 byte aligned, therefore we allocate a * bit more */ descr->skb = dev_alloc_skb(bufsize + GELIC_NET_RXBUF_ALIGN - 1); if (!descr->skb) { descr->buf_addr = 0; /* tell DMAC don't touch memory */ dev_info(ctodev(card), "%s:allocate skb failed !!\n", __func__); return -ENOMEM; } descr->buf_size = cpu_to_be32(bufsize); descr->dmac_cmd_status = 0; descr->result_size = 0; descr->valid_size = 0; descr->data_error = 0; offset = ((unsigned long)descr->skb->data) & (GELIC_NET_RXBUF_ALIGN - 1); if (offset) skb_reserve(descr->skb, GELIC_NET_RXBUF_ALIGN - offset); /* io-mmu-map the skb */ descr->buf_addr = cpu_to_be32(dma_map_single(ctodev(card), descr->skb->data, GELIC_NET_MAX_MTU, DMA_FROM_DEVICE)); if (!descr->buf_addr) { dev_kfree_skb_any(descr->skb); descr->skb = NULL; dev_info(ctodev(card), "%s:Could not iommu-map rx buffer\n", __func__); gelic_descr_set_status(descr, GELIC_DESCR_DMA_NOT_IN_USE); return -ENOMEM; } else { gelic_descr_set_status(descr, GELIC_DESCR_DMA_CARDOWNED); return 0; } }
/** * gelic_card_release_tx_chain - processes sent tx descriptors * @card: adapter structure * @stop: net_stop sequence * * releases the tx descriptors that gelic has finished with */ static void gelic_card_release_tx_chain(struct gelic_card *card, int stop) { struct gelic_descr_chain *tx_chain; enum gelic_descr_dma_status status; struct net_device *netdev; int release = 0; for (tx_chain = &card->tx_chain; tx_chain->head != tx_chain->tail && tx_chain->tail; tx_chain->tail = tx_chain->tail->next) { status = gelic_descr_get_status(tx_chain->tail); netdev = tx_chain->tail->skb->dev; switch (status) { case GELIC_DESCR_DMA_RESPONSE_ERROR: case GELIC_DESCR_DMA_PROTECTION_ERROR: case GELIC_DESCR_DMA_FORCE_END: if (printk_ratelimit()) dev_info(ctodev(card), "%s: forcing end of tx descriptor " \ "with status %x\n", __func__, status); netdev->stats.tx_dropped++; break; case GELIC_DESCR_DMA_COMPLETE: if (tx_chain->tail->skb) { netdev->stats.tx_packets++; netdev->stats.tx_bytes += tx_chain->tail->skb->len; } break; case GELIC_DESCR_DMA_CARDOWNED: /* pending tx request */ default: /* any other value (== GELIC_DESCR_DMA_NOT_IN_USE) */ if (!stop) goto out; } gelic_descr_release_tx(card, tx_chain->tail); release ++; } out: if (!stop && release) gelic_card_wake_queues(card); }
/** * gelic_card_kick_txdma - enables TX DMA processing * @card: card structure * @descr: descriptor address to enable TX processing at * */ static int gelic_card_kick_txdma(struct gelic_card *card, struct gelic_descr *descr) { int status = 0; if (card->tx_dma_progress) return 0; if (gelic_descr_get_status(descr) == GELIC_DESCR_DMA_CARDOWNED) { card->tx_dma_progress = 1; status = lv1_net_start_tx_dma(bus_id(card), dev_id(card), descr->bus_addr, 0); if (status) dev_info(ctodev(card), "lv1_net_start_txdma failed," \ "status=%d\n", status); } return status; }
/** * gelic_card_enable_rxdmac - enables the receive DMA controller * @card: card structure * * gelic_card_enable_rxdmac enables the DMA controller by setting RX_DMA_EN * in the GDADMACCNTR register */ static void gelic_card_enable_rxdmac(struct gelic_card *card) { int status; #ifdef DEBUG if (gelic_descr_get_status(card->rx_chain.head) != GELIC_DESCR_DMA_CARDOWNED) { printk(KERN_ERR "%s: status=%x\n", __func__, be32_to_cpu(card->rx_chain.head->dmac_cmd_status)); printk(KERN_ERR "%s: nextphy=%x\n", __func__, be32_to_cpu(card->rx_chain.head->next_descr_addr)); printk(KERN_ERR "%s: head=%p\n", __func__, card->rx_chain.head); } #endif status = lv1_net_start_rx_dma(bus_id(card), dev_id(card), card->rx_chain.head->bus_addr, 0); if (status) dev_info(ctodev(card), "lv1_net_start_rx_dma failed, status=%d\n", status); }
/** * gelic_card_decode_one_descr - processes an rx descriptor * @card: card structure * * returns 1 if a packet has been sent to the stack, otherwise 0 * * processes an rx descriptor by iommu-unmapping the data buffer and passing * the packet up to the stack */ static int gelic_card_decode_one_descr(struct gelic_card *card) { enum gelic_descr_dma_status status; struct gelic_descr_chain *chain = &card->rx_chain; struct gelic_descr *descr = chain->head; struct net_device *netdev = NULL; int dmac_chain_ended; status = gelic_descr_get_status(descr); /* is this descriptor terminated with next_descr == NULL? */ dmac_chain_ended = be32_to_cpu(descr->dmac_cmd_status) & GELIC_DESCR_RX_DMA_CHAIN_END; if (status == GELIC_DESCR_DMA_CARDOWNED) return 0; if (status == GELIC_DESCR_DMA_NOT_IN_USE) { dev_dbg(ctodev(card), "dormant descr? %p\n", descr); return 0; } /* netdevice select */ if (card->vlan_required) { unsigned int i; u16 vid; vid = *(u16 *)(descr->skb->data) & VLAN_VID_MASK; for (i = 0; i < GELIC_PORT_MAX; i++) { if (card->vlan[i].rx == vid) { netdev = card->netdev[i]; break; } }; if (GELIC_PORT_MAX <= i) { pr_info("%s: unknown packet vid=%x\n", __func__, vid); goto refill; } } else netdev = card->netdev[GELIC_PORT_ETHERNET]; if ((status == GELIC_DESCR_DMA_RESPONSE_ERROR) || (status == GELIC_DESCR_DMA_PROTECTION_ERROR) || (status == GELIC_DESCR_DMA_FORCE_END)) { dev_info(ctodev(card), "dropping RX descriptor with state %x\n", status); netdev->stats.rx_dropped++; goto refill; } if (status == GELIC_DESCR_DMA_BUFFER_FULL) { /* * Buffer full would occur if and only if * the frame length was longer than the size of this * descriptor's buffer. If the frame length was equal * to or shorter than buffer'size, FRAME_END condition * would occur. * Anyway this frame was longer than the MTU, * just drop it. */ dev_info(ctodev(card), "overlength frame\n"); goto refill; } /* * descriptoers any other than FRAME_END here should * be treated as error. */ if (status != GELIC_DESCR_DMA_FRAME_END) { dev_dbg(ctodev(card), "RX descriptor with state %x\n", status); goto refill; } /* ok, we've got a packet in descr */ gelic_net_pass_skb_up(descr, card, netdev); refill: /* * So that always DMAC can see the end * of the descriptor chain to avoid * from unwanted DMAC overrun. */ descr->next_descr_addr = 0; /* change the descriptor state: */ gelic_descr_set_status(descr, GELIC_DESCR_DMA_NOT_IN_USE); /* * this call can fail, but for now, just leave this * decriptor without skb */ gelic_descr_prepare_rx(card, descr); chain->tail = descr; chain->head = descr->next; /* * Set this descriptor the end of the chain. */ descr->prev->next_descr_addr = cpu_to_be32(descr->bus_addr); /* * If dmac chain was met, DMAC stopped. * thus re-enable it */ if (dmac_chain_ended) { card->rx_dma_restart_required = 1; dev_dbg(ctodev(card), "reenable rx dma scheduled\n"); } return 1; }