gen8_instruction *
gen8_generator::next_inst(unsigned opcode)
{
gen8_instruction *inst;
if (nr_inst + 1 > unsigned(store_size)) {
store_size <<= 1;
store = reralloc(mem_ctx, store, gen8_instruction, store_size);
assert(store);
}
next_inst_offset += 16;
inst = &store[nr_inst++];
memset(inst, 0, sizeof(gen8_instruction));
gen8_set_opcode(inst, opcode);
gen8_set_exec_size(inst, default_state.exec_size);
gen8_set_access_mode(inst, default_state.access_mode);
gen8_set_mask_control(inst, default_state.mask_control);
gen8_set_qtr_control(inst, default_state.qtr_control);
gen8_set_cond_modifier(inst, default_state.conditional_mod);
gen8_set_pred_control(inst, default_state.predicate);
gen8_set_pred_inv(inst, default_state.predicate_inverse);
gen8_set_saturate(inst, default_state.saturate);
gen8_set_flag_subreg_nr(inst, default_state.flag_subreg_nr);
return inst;
}
void
gen8_vec4_generator::generate_scratch_write(vec4_instruction *ir,
struct brw_reg dst,
struct brw_reg src,
struct brw_reg index)
{
struct brw_reg header = brw_vec8_grf(GEN7_MRF_HACK_START + ir->base_mrf, 0);
MOV_RAW(header, brw_vec8_grf(0, 0));
generate_oword_dual_block_offsets(brw_message_reg(ir->base_mrf + 1), index);
MOV(retype(brw_message_reg(ir->base_mrf + 2), BRW_REGISTER_TYPE_D),
retype(src, BRW_REGISTER_TYPE_D));
/* Each of the 8 channel enables is considered for whether each
* dword is written.
*/
gen8_instruction *send = next_inst(BRW_OPCODE_SEND);
gen8_set_dst(brw, send, dst);
gen8_set_src0(brw, send, header);
gen8_set_pred_control(send, ir->predicate);
gen8_set_dp_message(brw, send, GEN7_SFID_DATAPORT_DATA_CACHE,
255, /* binding table index: stateless access */
GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE,
BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
3, /* mlen */
0, /* rlen */
true, /* header present */
false); /* EOT */
}
