void do_mem_stage() { bool_t read = gen_mem_read(); bool_t mem_ok = TRUE; word_t valm = 0; mem_addr = gen_mem_addr(); mem_data = ex_mem_curr->vala; mem_write = gen_mem_write(); if (read) { mem_ok = get_word_val(mem, mem_addr, &valm); sim_log("Memory: Read 0x%x from 0x%x, instruction = %s\n", valm, mem_addr, iname(HPACK(ex_mem_curr->icode, ex_mem_curr->ifun))); } if (mem_write) { word_t sink; /* Do a read of address just to check validity */ mem_ok = get_word_val(mem, mem_addr, &sink); } mem_wb_next->icode = ex_mem_curr->icode; mem_wb_next->ifun = ex_mem_curr->ifun; mem_wb_next->vale = ex_mem_curr->vale; mem_wb_next->valm = valm; mem_wb_next->deste = ex_mem_curr->deste; mem_wb_next->destm = ex_mem_curr->destm; mem_wb_next->exception = mem_ok ? ex_mem_curr->exception : EXC_ADDR; mem_wb_next->stage_pc = ex_mem_curr->stage_pc; }
void do_mem_stage() { bool_t read = gen_mem_read(); word_t valm = 0; mem_addr = gen_mem_addr(); mem_data = ex_mem_curr->vala; mem_write = gen_mem_write(); mem_test = gen_mem_test(); dmem_error = FALSE; if (read && !mem_test) { dmem_error = dmem_error || !get_word_val(mem, mem_addr, &valm); if (!dmem_error) sim_log("\tMemory: Read 0x%x from 0x%x\n", valm, mem_addr); } if (mem_write && !mem_test) { word_t sink; /* Do a read of address just to check validity */ dmem_error = dmem_error || !get_word_val(mem, mem_addr, &sink); if (dmem_error) sim_log("\tMemory: Invalid address 0x%x\n", mem_addr); } if (mem_test && read){ mem_test_address = mem_addr; int ans = test_memory(mem, mem_test_address); valm = ans; } mem_wb_next->icode = ex_mem_curr->icode; mem_wb_next->ifun = ex_mem_curr->ifun; mem_wb_next->vale = ex_mem_curr->vale; mem_wb_next->valm = valm; mem_wb_next->deste = ex_mem_curr->deste; mem_wb_next->destm = ex_mem_curr->destm; mem_wb_next->status = gen_m_stat(); mem_wb_next->stage_pc = ex_mem_curr->stage_pc; }
void do_mem_stage() { bool_t read = gen_mem_read(); word_t valm = 0; mem_addr = gen_mem_addr(); if(ex_mem_curr->icode == I_MUTEXTEST || ex_mem_curr->icode == I_MUTEXCLEAR) mem_addr = MUTEX_BYTE; mem_data = ex_mem_curr->vala; if(ex_mem_curr->icode == I_MUTEXTEST) mem_data = 1; else if(ex_mem_curr->icode == I_MUTEXCLEAR) mem_data = 0; mem_write = gen_mem_write(); dmem_error = FALSE; if (read) { dmem_error = dmem_error || !get_word_val(mem, mem_addr, &valm); if (!dmem_error) sim_log("\tMemory: Read 0x%x from 0x%x\n", valm, mem_addr); } if (mem_write) { word_t sink; /* Do a read of address just to check validity */ dmem_error = dmem_error || !get_word_val(mem, mem_addr, &sink); if (dmem_error) sim_log("\tMemory: Invalid address 0x%x\n", mem_addr); } mem_wb_next->icode = ex_mem_curr->icode; mem_wb_next->ifun = ex_mem_curr->ifun; mem_wb_next->vale = ex_mem_curr->vale; mem_wb_next->valm = valm; mem_wb_next->deste = ex_mem_curr->deste; mem_wb_next->destm = ex_mem_curr->destm; mem_wb_next->status = gen_m_stat(); mem_wb_next->stage_pc = ex_mem_curr->stage_pc; }
/* Return resulting exception status */ static exc_t sim_step() { word_t aluA; word_t aluB; word_t alufun; exc_t status = update_state(); /* Update state from last cycle */ if (plusmode) { pc = gen_pc(); } valp = pc; if (get_byte_val(mem, valp, &instr)) { icode = HI4(instr); ifun = LO4(instr); } else { instr = HPACK(I_NOP,0); icode = I_NOP; ifun = 0; status = EXC_ADDR; sim_log("Couldn't fetch at address 0x%x\n", valp); } valp++; if (gen_need_regids()) { byte_t regids; if (get_byte_val(mem, valp, ®ids)) { ra = GET_RA(regids); rb = GET_RB(regids); } else { ra = REG_NONE; rb = REG_NONE; status = EXC_ADDR; sim_log("Couldn't fetch at address 0x%x\n", valp); } valp++; } else { ra = REG_NONE; rb = REG_NONE; } if (gen_need_valC()) { if (get_word_val(mem, valp, &valc)) { } else { valc = 0; status = EXC_ADDR; sim_log("Couldn't fetch at address 0x%x\n", valp); } valp+=4; } else { valc = 0; } if (status == EXC_NONE && !gen_instr_valid()) { status = EXC_INSTR; } sim_log("IF: Fetched %s at 0x%x. ra=%s, rb=%s, valC = 0x%x\n", iname(HPACK(icode,ifun)), pc, reg_name(ra), reg_name(rb), valc); if (status == EXC_NONE && icode == I_HALT) { status = EXC_HALT; } srcA = gen_srcA(); if (srcA != REG_NONE) { vala = get_reg_val(reg, srcA); } else { vala = 0; } srcB = gen_srcB(); if (srcB != REG_NONE) { valb = get_reg_val(reg, srcB); } else { valb = 0; } destE = gen_dstE(); destM = gen_dstM(); aluA = gen_aluA(); aluB = gen_aluB(); alufun = gen_alufun(); vale = compute_alu(alufun, aluA, aluB); cc_in = cc; if (gen_set_cc()) cc_in = compute_cc(alufun, aluA, aluB); bcond = (icode == I_JMP) && take_branch(cc, ifun); mem_addr = gen_mem_addr(); mem_data = gen_mem_data(); if (status == EXC_NONE && gen_mem_read()) { if (!get_word_val(mem, mem_addr, &valm)) { sim_log("Couldn't read at address 0x%x\n", mem_addr); return EXC_ADDR; } } else valm = 0; mem_write = status == EXC_NONE && gen_mem_write(); if (plusmode) { prev_icode_in = icode; prev_ifun_in = ifun; prev_valc_in = valc; prev_valm_in = valm; prev_valp_in = valp; prev_bcond_in = bcond; } else { /* Update PC */ pc_in = gen_new_pc(); } sim_report(); return status; }
/* Return resulting status */ static byte_t sim_step() { word_t aluA; word_t aluB; word_t alufun; status = STAT_AOK; imem_error = dmem_error = FALSE; update_state(); /* Update state from last cycle */ if (plusmode) { pc = gen_pc(); } valp = pc; instr = HPACK(I_NOP, F_NONE); imem_error = !get_byte_val(mem, valp, &instr); if (imem_error) { sim_log("Couldn't fetch at address 0x%x\n", valp); } imem_icode = HI4(instr); imem_ifun = LO4(instr); icode = gen_icode(); ifun = gen_ifun(); instr_valid = gen_instr_valid(); valp++; if (gen_need_regids()) { byte_t regids; if (get_byte_val(mem, valp, ®ids)) { ra = GET_RA(regids); rb = GET_RB(regids); } else { ra = REG_NONE; rb = REG_NONE; status = STAT_ADR; sim_log("Couldn't fetch at address 0x%x\n", valp); } valp++; } else { ra = REG_NONE; rb = REG_NONE; } if (gen_need_valC()) { if (get_word_val(mem, valp, &valc)) { } else { valc = 0; status = STAT_ADR; sim_log("Couldn't fetch at address 0x%x\n", valp); } valp+=4; } else { valc = 0; } sim_log("IF: Fetched %s at 0x%x. ra=%s, rb=%s, valC = 0x%x\n", iname(HPACK(icode,ifun)), pc, reg_name(ra), reg_name(rb), valc); if (status == STAT_AOK && icode == I_HALT) { status = STAT_HLT; } srcA = gen_srcA(); if (srcA != REG_NONE) { vala = get_reg_val(reg, srcA); } else { vala = 0; } srcB = gen_srcB(); if (srcB != REG_NONE) { valb = get_reg_val(reg, srcB); } else { valb = 0; } cond = cond_holds(cc, ifun); destE = gen_dstE(); destM = gen_dstM(); aluA = gen_aluA(); aluB = gen_aluB(); alufun = gen_alufun(); vale = compute_alu(alufun, aluA, aluB); cc_in = cc; if (gen_set_cc()) cc_in = compute_cc(alufun, aluA, aluB); bcond = cond && (icode == I_JMP); mem_addr = gen_mem_addr(); mem_data = gen_mem_data(); if (gen_mem_read()) { dmem_error = dmem_error || !get_word_val(mem, mem_addr, &valm); if (dmem_error) { sim_log("Couldn't read at address 0x%x\n", mem_addr); } } else valm = 0; mem_write = gen_mem_write(); if (mem_write) { /* Do a test read of the data memory to make sure address is OK */ word_t junk; dmem_error = dmem_error || !get_word_val(mem, mem_addr, &junk); } status = gen_Stat(); if (plusmode) { prev_icode_in = icode; prev_ifun_in = ifun; prev_valc_in = valc; prev_valm_in = valm; prev_valp_in = valp; prev_bcond_in = bcond; } else { /* Update PC */ pc_in = gen_new_pc(); } sim_report(); return status; }