static void serial_divs (int baudrate, unsigned long *pudiv, unsigned short *pbdiv) { sys_info_t sysinfo; unsigned long div; /* total divisor udiv * bdiv */ unsigned long umin; /* minimum udiv */ unsigned short diff; /* smallest diff */ unsigned long udiv; /* best udiv */ unsigned short idiff; /* current diff */ unsigned short ibdiv; /* current bdiv */ unsigned long i; unsigned long est; /* current estimate */ unsigned long plloutb; unsigned long cpr_pllc; u32 reg; /* check the pll feedback source */ mfcpr(cprpllc, cpr_pllc); get_sys_info(&sysinfo); plloutb = ((CONFIG_SYS_CLK_FREQ * ((cpr_pllc & PLLC_SRC_MASK) ? sysinfo.pllFwdDivB : sysinfo.pllFwdDiv) * sysinfo.pllFbkDiv) / sysinfo.pllFwdDivB); udiv = 256; /* Assume lowest possible serial clk */ div = plloutb / (16 * baudrate); /* total divisor */ umin = (plloutb / get_OPB_freq()) << 1; /* 2 x OPB divisor */ diff = 256; /* highest possible */ /* i is the test udiv value -- start with the largest * possible (256) to minimize serial clock and constrain * search to umin. */ for (i = 256; i > umin; i--) { ibdiv = div / i; est = i * ibdiv; idiff = (est > div) ? (est-div) : (div-est); if (idiff == 0) { udiv = i; break; /* can't do better */ } else if (idiff < diff) { udiv = i; /* best so far */ diff = idiff; /* update lowest diff*/ } } *pudiv = udiv; mfcpr(cprperd0, reg); reg &= ~0x0000ffff; reg |= ((udiv - 0) << 8) | (udiv - 0); mtcpr(cprperd0, reg); *pbdiv = div / udiv; }
int init_board_data(bd_t *bd) { cpu_init_board_data(bd); bd->bi_memstart = 0; /* start of DRAM memory */ // bd->bi_memsize = gd->ram_size; /* size of DRAM memory in bytes */ /* FIXME */ #ifdef CONFIG_IP860 bd->bi_sramstart = SRAM_BASE; /* start of SRAM memory */ bd->bi_sramsize = SRAM_SIZE; /* size of SRAM memory */ #else bd->bi_sramstart = 0; /* FIXME */ /* start of SRAM memory */ bd->bi_sramsize = 0; /* FIXME */ /* size of SRAM memory */ #endif #if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx) || \ defined(CONFIG_E500) || defined(CONFIG_MPC86xx) bd->bi_immr_base = CFG_IMMR; /* base of IMMR register */ #endif #ifdef CONFIG_LYNXOS bd->bi_bootflags = bootflag; /* boot / reboot flag (for LynxOS) */ #endif #if defined(CONFIG_CPM2) bd->bi_cpmfreq = gd->cpm_clk; bd->bi_brgfreq = gd->brg_clk; bd->bi_sccfreq = gd->scc_clk; bd->bi_vco = gd->vco_out; #endif /* CONFIG_CPM2 */ // bd->bi_baudrate = gd->baudrate; /* Console Baudrate */ #ifdef CFG_EXTBDINFO strncpy ((char *)bd->bi_s_version, "1.2", sizeof (bd->bi_s_version)); strncpy ((char *)bd->bi_r_version, BAREBOX_VERSION, sizeof (bd->bi_r_version)); bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */ bd->bi_plb_busfreq = gd->bus_clk; #if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) bd->bi_pci_busfreq = get_PCI_freq (); bd->bi_opbfreq = get_OPB_freq (); #elif defined(CONFIG_XILINX_ML300) bd->bi_pci_busfreq = get_PCI_freq (); #endif #endif return 0; }
static int setup_board_extra(void) { bd_t *bd = gd->bd; strncpy((char *) bd->bi_s_version, "1.2", sizeof(bd->bi_s_version)); strncpy((char *) bd->bi_r_version, U_BOOT_VERSION, sizeof(bd->bi_r_version)); bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */ bd->bi_plb_busfreq = gd->bus_clk; #if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \ defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) bd->bi_pci_busfreq = get_PCI_freq(); bd->bi_opbfreq = get_OPB_freq(); #elif defined(CONFIG_XILINX_405) bd->bi_pci_busfreq = get_PCI_freq(); #endif return 0; }
void board_init_f(ulong bootflag) { bd_t *bd; ulong len, addr, addr_sp; ulong *s; gd_t *id; init_fnc_t **init_fnc_ptr; #ifdef CONFIG_PRAM ulong reg; #endif /* Pointer is writable since we allocated a register for it */ gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); /* compiler optimization barrier needed for GCC >= 3.4 */ __asm__ __volatile__("":::"memory"); #if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC512X) && \ !defined(CONFIG_MPC83xx) && !defined(CONFIG_MPC85xx) && \ !defined(CONFIG_MPC86xx) /* Clear initial global data */ memset((void *) gd, 0, sizeof(gd_t)); #endif gd->flags = bootflag; for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) if ((*init_fnc_ptr) () != 0) hang(); #ifdef CONFIG_POST post_bootmode_init(); post_run(NULL, POST_ROM | post_bootmode_get(NULL)); #endif WATCHDOG_RESET(); /* * Now that we have DRAM mapped and working, we can * relocate the code and continue running from DRAM. * * Reserve memory at end of RAM for (top down in that order): * - area that won't get touched by U-Boot and Linux (optional) * - kernel log buffer * - protected RAM * - LCD framebuffer * - monitor code * - board info struct */ len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE; /* * Subtract specified amount of memory to hide so that it won't * get "touched" at all by U-Boot. By fixing up gd->ram_size * the Linux kernel should now get passed the now "corrected" * memory size and won't touch it either. This should work * for arch/ppc and arch/powerpc. Only Linux board ports in * arch/powerpc with bootwrapper support, that recalculate the * memory size from the SDRAM controller setup will have to * get fixed. */ gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; addr = CONFIG_SYS_SDRAM_BASE + get_effective_memsize(); #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) /* * We need to make sure the location we intend to put secondary core * boot code is reserved and not used by any part of u-boot */ if (addr > determine_mp_bootpg(NULL)) { addr = determine_mp_bootpg(NULL); debug("Reserving MP boot page to %08lx\n", addr); } #endif #ifdef CONFIG_LOGBUFFER #ifndef CONFIG_ALT_LB_ADDR /* reserve kernel log buffer */ addr -= (LOGBUFF_RESERVE); debug("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, addr); #endif #endif #ifdef CONFIG_PRAM /* * reserve protected RAM */ reg = getenv_ulong("pram", 10, CONFIG_PRAM); addr -= (reg << 10); /* size is in kB */ debug("Reserving %ldk for protected RAM at %08lx\n", reg, addr); #endif /* CONFIG_PRAM */ /* round down to next 4 kB limit */ addr &= ~(4096 - 1); debug("Top of RAM usable for U-Boot at: %08lx\n", addr); #ifdef CONFIG_LCD #ifdef CONFIG_FB_ADDR gd->fb_base = CONFIG_FB_ADDR; #else /* reserve memory for LCD display (always full pages) */ addr = lcd_setmem(addr); gd->fb_base = addr; #endif /* CONFIG_FB_ADDR */ #endif /* CONFIG_LCD */ #if defined(CONFIG_VIDEO) && defined(CONFIG_8xx) /* reserve memory for video display (always full pages) */ addr = video_setmem(addr); gd->fb_base = addr; #endif /* CONFIG_VIDEO */ /* * reserve memory for U-Boot code, data & bss * round down to next 4 kB limit */ addr -= len; addr &= ~(4096 - 1); #ifdef CONFIG_E500 /* round down to next 64 kB limit so that IVPR stays aligned */ addr &= ~(65536 - 1); #endif debug("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr); /* * reserve memory for malloc() arena */ addr_sp = addr - TOTAL_MALLOC_LEN; debug("Reserving %dk for malloc() at: %08lx\n", TOTAL_MALLOC_LEN >> 10, addr_sp); /* * (permanently) allocate a Board Info struct * and a permanent copy of the "global" data */ addr_sp -= sizeof(bd_t); bd = (bd_t *) addr_sp; memset(bd, 0, sizeof(bd_t)); gd->bd = bd; debug("Reserving %zu Bytes for Board Info at: %08lx\n", sizeof(bd_t), addr_sp); addr_sp -= sizeof(gd_t); id = (gd_t *) addr_sp; debug("Reserving %zu Bytes for Global Data at: %08lx\n", sizeof(gd_t), addr_sp); /* * Finally, we set up a new (bigger) stack. * * Leave some safety gap for SP, force alignment on 16 byte boundary * Clear initial stack frame */ addr_sp -= 16; addr_sp &= ~0xF; s = (ulong *) addr_sp; *s = 0; /* Terminate back chain */ *++s = 0; /* NULL return address */ debug("Stack Pointer at: %08lx\n", addr_sp); /* * Save local variables to board info struct */ bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */ bd->bi_memsize = gd->ram_size; /* size in bytes */ #ifdef CONFIG_SYS_SRAM_BASE bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */ bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ #endif #if defined(CONFIG_8xx) || defined(CONFIG_MPC8260) || defined(CONFIG_5xx) || \ defined(CONFIG_E500) || defined(CONFIG_MPC86xx) bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */ #endif #if defined(CONFIG_MPC5xxx) bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */ #endif #if defined(CONFIG_MPC83xx) bd->bi_immrbar = CONFIG_SYS_IMMR; #endif WATCHDOG_RESET(); bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ #if defined(CONFIG_CPM2) bd->bi_cpmfreq = gd->arch.cpm_clk; bd->bi_brgfreq = gd->arch.brg_clk; bd->bi_sccfreq = gd->arch.scc_clk; bd->bi_vco = gd->arch.vco_out; #endif /* CONFIG_CPM2 */ #if defined(CONFIG_MPC512X) bd->bi_ipsfreq = gd->arch.ips_clk; #endif /* CONFIG_MPC512X */ #if defined(CONFIG_MPC5xxx) bd->bi_ipbfreq = gd->arch.ipb_clk; bd->bi_pcifreq = gd->pci_clk; #endif /* CONFIG_MPC5xxx */ #ifdef CONFIG_SYS_EXTBDINFO strncpy((char *) bd->bi_s_version, "1.2", sizeof(bd->bi_s_version)); strncpy((char *) bd->bi_r_version, U_BOOT_VERSION, sizeof(bd->bi_r_version)); bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */ bd->bi_plb_busfreq = gd->bus_clk; #if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \ defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) bd->bi_pci_busfreq = get_PCI_freq(); bd->bi_opbfreq = get_OPB_freq(); #elif defined(CONFIG_XILINX_405) bd->bi_pci_busfreq = get_PCI_freq(); #endif #endif debug("New Stack Pointer is: %08lx\n", addr_sp); WATCHDOG_RESET(); gd->relocaddr = addr; /* Store relocation addr, useful for debug */ memcpy(id, (void *) gd, sizeof(gd_t)); relocate_code(addr_sp, id, addr); /* NOTREACHED - relocate_code() does not return */ }
int checkcpu (void) { #if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */ uint pvr = get_pvr(); ulong clock = gd->cpu_clk; char buf[32]; #if !defined(CONFIG_IOP480) char addstr[64] = ""; sys_info_t sys_info; puts ("CPU: "); get_sys_info(&sys_info); puts("AMCC PowerPC 4"); #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ defined(CONFIG_405EX) puts("05"); #endif #if defined(CONFIG_440) puts("40"); #endif switch (pvr) { case PVR_405GP_RB: puts("GP Rev. B"); break; case PVR_405GP_RC: puts("GP Rev. C"); break; case PVR_405GP_RD: puts("GP Rev. D"); break; #ifdef CONFIG_405GP case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */ puts("GP Rev. E"); break; #endif case PVR_405CR_RA: puts("CR Rev. A"); break; case PVR_405CR_RB: puts("CR Rev. B"); break; #ifdef CONFIG_405CR case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */ puts("CR Rev. C"); break; #endif case PVR_405GPR_RB: puts("GPr Rev. B"); break; case PVR_405EP_RB: puts("EP Rev. B"); break; case PVR_405EZ_RA: puts("EZ Rev. A"); break; case PVR_405EX1_RA: puts("EX Rev. A"); strcpy(addstr, "Security support"); break; case PVR_405EX2_RA: puts("EX Rev. A"); strcpy(addstr, "No Security support"); break; case PVR_405EXR1_RA: puts("EXr Rev. A"); strcpy(addstr, "Security support"); break; case PVR_405EXR2_RA: puts("EXr Rev. A"); strcpy(addstr, "No Security support"); break; #if defined(CONFIG_440) case PVR_440GP_RB: puts("GP Rev. B"); /* See errata 1.12: CHIP_4 */ if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) || (mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){ puts ( "\n\t CPC0_SYSx DCRs corrupted. " "Resetting chip ...\n"); udelay( 1000 * 1000 ); /* Give time for serial buf to clear */ do_chip_reset ( mfdcr(cpc0_strp0), mfdcr(cpc0_strp1) ); } break; case PVR_440GP_RC: puts("GP Rev. C"); break; case PVR_440GX_RA: puts("GX Rev. A"); break; case PVR_440GX_RB: puts("GX Rev. B"); break; case PVR_440GX_RC: puts("GX Rev. C"); break; case PVR_440GX_RF: puts("GX Rev. F"); break; case PVR_440EP_RA: puts("EP Rev. A"); break; #ifdef CONFIG_440EP case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */ puts("EP Rev. B"); break; case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */ puts("EP Rev. C"); break; #endif /* CONFIG_440EP */ #ifdef CONFIG_440GR case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */ puts("GR Rev. A"); break; case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */ puts("GR Rev. B"); break; #endif /* CONFIG_440GR */ #endif /* CONFIG_440 */ #ifdef CONFIG_440EPX case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */ puts("EPx Rev. A"); strcpy(addstr, "Security/Kasumi support"); break; case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */ puts("EPx Rev. A"); strcpy(addstr, "No Security/Kasumi support"); break; #endif /* CONFIG_440EPX */ #ifdef CONFIG_440GRX case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */ puts("GRx Rev. A"); strcpy(addstr, "Security/Kasumi support"); break; case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */ puts("GRx Rev. A"); strcpy(addstr, "No Security/Kasumi support"); break; #endif /* CONFIG_440GRX */ case PVR_440SP_6_RAB: puts("SP Rev. A/B"); strcpy(addstr, "RAID 6 support"); break; case PVR_440SP_RAB: puts("SP Rev. A/B"); strcpy(addstr, "No RAID 6 support"); break; case PVR_440SP_6_RC: puts("SP Rev. C"); strcpy(addstr, "RAID 6 support"); break; case PVR_440SP_RC: puts("SP Rev. C"); strcpy(addstr, "No RAID 6 support"); break; case PVR_440SPe_6_RA: puts("SPe Rev. A"); strcpy(addstr, "RAID 6 support"); break; case PVR_440SPe_RA: puts("SPe Rev. A"); strcpy(addstr, "No RAID 6 support"); break; case PVR_440SPe_6_RB: puts("SPe Rev. B"); strcpy(addstr, "RAID 6 support"); break; case PVR_440SPe_RB: puts("SPe Rev. B"); strcpy(addstr, "No RAID 6 support"); break; default: printf (" UNKNOWN (PVR=%08x)", pvr); break; } printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock), sys_info.freqPLB / 1000000, get_OPB_freq() / 1000000, sys_info.freqEBC / 1000000); if (addstr[0] != 0) printf(" %s\n", addstr); #if defined(I2C_BOOTROM) printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis"); #endif /* I2C_BOOTROM */ #if defined(SDR0_PINSTP_SHIFT) printf (" Bootstrap Option %c - ", bootstrap_char[bootstrap_option()]); printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]); #endif /* SDR0_PINSTP_SHIFT */ #if defined(CONFIG_PCI) && !defined(CONFIG_405EX) printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis"); #endif #if defined(PCI_ASYNC) if (pci_async_enabled()) { printf (", PCI async ext clock used"); } else { printf (", PCI sync clock at %lu MHz", sys_info.freqPLB / sys_info.pllPciDiv / 1000000); } #endif #if defined(CONFIG_PCI) && !defined(CONFIG_405EX) putc('\n'); #endif #if defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) printf (" 16 kB I-Cache 16 kB D-Cache"); #elif defined(CONFIG_440) printf (" 32 kB I-Cache 32 kB D-Cache"); #else printf (" 16 kB I-Cache %d kB D-Cache", ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8); #endif #endif /* !defined(CONFIG_IOP480) */ #if defined(CONFIG_IOP480) printf ("PLX IOP480 (PVR=%08x)", pvr); printf (" at %s MHz:", strmhz(buf, clock)); printf (" %u kB I-Cache", 4); printf (" %u kB D-Cache", 2); #endif #endif /* !defined(CONFIG_405) */ putc ('\n'); return 0; }