u32 get_ahb_bus_freq_hz(void)
{
#if defined(__FPGA__)
return 24000000;
#else
return get_core_bus_freq_hz();
#endif
}
static u32 ambarella_nand_get_pll(void)
{
u32 nand_pll;
#if defined(CONFIG_PLAT_AMBARELLA_SUPPORT_HAL)
nand_pll = (get_core_bus_freq_hz() / 1000000);
#else
nand_pll = (clk_get_rate(clk_get(NULL, "gclk_core")) / 1000000);
#endif
#if (FIO_USE_2X_FREQ == 1)
nand_pll <<= 1;
#endif
return nand_pll;
}
void _rct_set_sd_pll(u32 freq_hz)
{
#define DUTY_CYCLE_CONTRL_ENABLE 0x01000000 /* Duty cycle correction */
u32 scaler;
u32 core_freq;
K_ASSERT(freq_hz != 0);
/* Scaler = core_freq *2 / desired_freq */
core_freq = get_core_bus_freq_hz();
scaler = ((core_freq << 1) / freq_hz) + 1;
/* Sdclk = core_freq * 2 / Int_div */
/* For example: Sdclk = 108 * 2 / 5 = 43.2 Mhz */
/* For example: Sdclk = 121.5 * 2 / 5 = 48.6 Mhz */
writel(SCALER_SD48_REG,
(readl(SCALER_SD48_REG) & 0xffff0000) |
(DUTY_CYCLE_CONTRL_ENABLE | scaler));
DEBUG_MSG("SD Freq = %d, Set SCALER_SD48_REG 0x%x", freq_hz, scaler);
}
u32 get_ahb_bus_freq_hz(void)
{
return get_core_bus_freq_hz();
}
u32 get_apb_bus_freq_hz(void)
{
return get_core_bus_freq_hz() >> 1;
}
