static void sh_dmac_disable_dma(struct dma_info *info)
{
int irq = get_dmte_irq(info->chan);
disable_irq(irq);
sh_dmac->channel[info->chan].chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE);
}
static int sh_dmac_request_dma(struct dma_channel *chan)
{
if (unlikely(!(chan->flags & DMA_TEI_CAPABLE)))
return 0;
return request_irq(get_dmte_irq(chan->chan), dma_tei,
IRQF_DISABLED, chan->dev_id, chan);
}
static void sh_dmac_disable_dma(struct dma_channel *chan)
{
int irq = get_dmte_irq(chan->chan);
u32 chcr;
disable_irq(irq);
chcr = ctrl_inl(CHCR[chan->chan]);
chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE);
ctrl_outl(chcr, CHCR[chan->chan]);
}
static void sh_dmac_disable_dma(struct dma_channel *chan)
{
int irq;
u32 chcr;
if (chan->flags & DMA_TEI_CAPABLE) {
irq = get_dmte_irq(chan->chan);
disable_irq(irq);
}
chcr = ctrl_inl(CHCR[chan->chan]);
chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE);
ctrl_outl(chcr, CHCR[chan->chan]);
}
static void sh_dmac_enable_dma(struct dma_channel *chan)
{
int irq;
u32 chcr;
chcr = ctrl_inl(CHCR[chan->chan]);
chcr |= CHCR_DE;
if (chan->flags & DMA_TEI_CAPABLE)
chcr |= CHCR_IE;
ctrl_outl(chcr, CHCR[chan->chan]);
if (chan->flags & DMA_TEI_CAPABLE) {
irq = get_dmte_irq(chan->chan);
enable_irq(irq);
}
}
static int __init sh_dmac_init(void)
{
struct dma_info *info = &sh_dmac_info;
int i;
#ifdef CONFIG_CPU_SH4
make_ipr_irq(DMAE_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY);
i = request_irq(DMAE_IRQ, dma_err, SA_INTERRUPT, "DMAC Address Error", 0);
if (i < 0)
return i;
#endif
for (i = 0; i < info->nr_channels; i++) {
int irq = get_dmte_irq(i);
make_ipr_irq(irq, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY);
}
ctrl_outl(0x8000 | DMAOR_DME, DMAOR);
return register_dmac(info);
}
static int __init sh_dmac_init(void)
{
int i;
#ifdef CONFIG_CPU_SH4
make_ipr_irq(DMAE_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY);
i = request_irq(DMAE_IRQ, dma_err, SA_INTERRUPT, "DMAC Address Error", 0);
if (i < 0)
return i;
#endif
for (i = 0; i < MAX_DMAC_CHANNELS; i++) {
int irq = get_dmte_irq(i);
make_ipr_irq(irq, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY);
dma_info[i].ops = &sh_dmac_ops;
dma_info[i].tei_capable = 1;
}
sh_dmac->dmaor |= 0x8000 | DMAOR_DME;
return register_dmac(&sh_dmac_ops);
}
static void sh_dmac_free_dma(struct dma_channel *chan)
{
free_irq(get_dmte_irq(chan->chan), chan);
}
static int sh_dmac_request_dma(struct dma_channel *chan)
{
return request_irq(get_dmte_irq(chan->chan), dma_tei,
SA_INTERRUPT, "DMAC Transfer End", chan);
}
static void sh_dmac_free_dma(struct dma_info *info)
{
free_irq(get_dmte_irq(info->chan), info);
}
static int sh_dmac_request_dma(struct dma_info *info)
{
return request_irq(get_dmte_irq(info->chan), dma_tei,
SA_INTERRUPT, "DMAC Transfer End", info);
}
