void get_rapl_stuff()
{
struct rapl_limit l1, l2, l3, l4;
get_pkg_rapl_limit(0, &l1, &l2);
fprintf(stdout, "Socket 0 Limit 0\n");
dump_rapl_limit(&l1, stdout);
fprintf(stdout, "Socket 0 Limit 1\n");
dump_rapl_limit(&l2, stdout);
get_pkg_rapl_limit(1, &l1, &l2);
fprintf(stdout, "Socket 1 Limit 0\n");
dump_rapl_limit(&l1, stdout);
fprintf(stdout, "Socket 1 Limit 1\n");
dump_rapl_limit(&l2, stdout);
fprintf(stdout, "Socket 0 DRAM Limit\n");
get_dram_rapl_limit(0, &l3);
dump_rapl_limit(&l3, stdout);
fprintf(stdout, "Socket 1 DRAM Limit\n");
get_dram_rapl_limit(1, &l3);
dump_rapl_limit(&l3, stdout);
fprintf(stdout, "Socket 0 PP0 Limit\n");
get_pp_rapl_limit(0, &l4, NULL);
dump_rapl_limit(&l4, stdout);
fprintf(stdout, "Socket 1 PP0 Limit\n");
get_pp_rapl_limit(1, &l4, NULL);
dump_rapl_limit(&l4, stdout);
}
/// @brief Check lock bit of certain registers to determine if it's writable.
///
/// @return Number of locked registers, else -1 if rapl_storage() fails.
static int check_for_locks(void)
{
static uint64_t *rapl_flags = NULL;
static struct rapl_data *rapl = NULL;
struct rapl_limit rl1, rl2;
#ifndef IS_ARCH_2D
struct turbo_activation_ratio_data tar;
#endif
static uint64_t sockets = 0;
int numlocked = 0;
unsigned i;
const uint64_t lock = 0x80000000;
#ifdef LIBMSR_DEBUG
fprintf(stderr, "DEBUG: CHECKING FOR LOCKS\n");
#endif
if (rapl_flags == NULL || rapl == NULL || sockets == 0)
{
sockets = num_sockets();
if (rapl_storage(&rapl, &rapl_flags))
{
return -1;
}
}
/// @todo Should we flip bits for pkg_limit?
for (i = 0; i < sockets; i++)
{
if (*rapl_flags & PKG_POWER_LIMIT)
{
get_pkg_rapl_limit(i, &rl1, &rl2);
if (rl1.bits & (lock << 32))
{
numlocked++;
fprintf(stderr, "Warning: <libmsr> MSR register locked on this architecture: check_for_locks(): Power limit 1 [0:23] of MSR_PKG_POWER_LIMIT (0x610) is locked, writes will be ignored: %s:%s::%d\n", getenv("HOSTNAME"), __FILE__, __LINE__);
}
}
if (rl2.bits & lock)
{
numlocked++;
fprintf(stderr, "Warning: <libmsr> MSR register locked on this architecture: check_for_locks(): Power limit 2 [32:55] of MSR_PKG_POWER_LIMIT (0x610) is locked, writes will be ignored: %s:%s::%d\n", getenv("HOSTNAME"), __FILE__, __LINE__);
}
if (rl1.bits & lock && rl2.bits & lock)
{
*rapl_flags &= ~PKG_POWER_LIMIT;
}
if (*rapl_flags & DRAM_POWER_LIMIT)
{
get_dram_rapl_limit(i, &rl1);
if (rl1.bits & lock)
{
numlocked++;
fprintf(stderr, "Warning: <libmsr> MSR register locked on this architecture: check_for_locks(): MSR_DRAM_POWER_LIMIT (0x618) is locked, writes will be ignored: %s:%s::%d\n", getenv("HOSTNAME"), __FILE__, __LINE__);
*rapl_flags &= ~DRAM_POWER_LIMIT;
}
}
#ifndef IS_ARCH_2D
if (*rapl_flags & TURBO_ACTIVATION_RATIO)
{
get_max_turbo_activation_ratio(i, &tar);
if (tar.bits & lock)
{
numlocked++;
fprintf(stderr, "Warning: <libmsr> MSR register locked on this architecture: check_for_locks(): MSR_TURBO_ACTIVATION_RATIO (0x64C) is locked, writes will be ignored: %s:%s::%d\n", getenv("HOSTNAME"), __FILE__, __LINE__);
*rapl_flags &= ~TURBO_ACTIVATION_RATIO;
}
}
#endif
}
return numlocked;
}
