void __init mpc834x_sys_init_IRQ(void)
{
u8 senses[8] = {
0, /* EXT 0 */
IRQ_SENSE_LEVEL, /* EXT 1 */
IRQ_SENSE_LEVEL, /* EXT 2 */
0, /* EXT 3 */
#ifdef CONFIG_PCI
IRQ_SENSE_LEVEL, /* EXT 4 */
IRQ_SENSE_LEVEL, /* EXT 5 */
IRQ_SENSE_LEVEL, /* EXT 6 */
IRQ_SENSE_LEVEL, /* EXT 7 */
#else
0, /* EXT 4 */
0, /* EXT 5 */
0, /* EXT 6 */
0, /* EXT 7 */
#endif
};
ipic_init(get_immrbase() + 0x00700, 0, 0, senses, 8);
/* Initialize the default interrupt mapping priorities,
* in case the boot rom changed something on us.
*/
ipic_set_default_priority();
}
static int __init mpc83xx_restart_init(void)
{
/* map reset restart_reg_baseister space */
restart_reg_base = ioremap(get_immrbase() + 0x900, 0xff);
return 0;
}
void __init cpm2_reset(void)
{
#ifdef CONFIG_PPC_85xx
cpm2_immr = ioremap(get_immrbase() + 0x80000, CPM_MAP_SIZE);
#else
cpm2_immr = ioremap(get_immrbase(), CPM_MAP_SIZE);
#endif
cpm_muram_init();
cpmp = &cpm2_immr->im_cpm;
#ifndef CONFIG_PPC_EARLY_DEBUG_CPM
cpm_command(CPM_CR_RST, 0);
#endif
}
static void __init mpc82xx_ads_pic_init(void)
{
struct device_node *np = of_find_compatible_node(NULL, "cpm-pic", "CPM2");
struct resource r;
cpm2_map_t *cpm_reg;
if (np == NULL) {
printk(KERN_ERR "PIC init: can not find cpm-pic node\n");
return;
}
if (of_address_to_resource(np, 0, &r)) {
printk(KERN_ERR "PIC init: invalid resource\n");
of_node_put(np);
return;
}
cpm2_pic_init(np);
of_node_put(np);
/* Initialize the default interrupt mapping priorities,
* in case the boot rom changed something on us.
*/
cpm_reg = (cpm2_map_t *) ioremap(get_immrbase(), sizeof(cpm2_map_t));
cpm_reg->im_intctl.ic_siprr = 0x05309770;
iounmap(cpm_reg);
#ifdef CONFIG_PCI
/* Initialize stuff for the 82xx CPLD IC and install demux */
m82xx_pci_init_irq();
#endif
}
void __init cpm_reset(void)
{
sysconf8xx_t __iomem *siu_conf;
mpc8xx_immr = ioremap(get_immrbase(), 0x4000);
if (!mpc8xx_immr) {
printk(KERN_CRIT "Could not map IMMR\n");
return;
}
cpmp = &mpc8xx_immr->im_cpm;
#ifndef CONFIG_PPC_EARLY_DEBUG_CPM
out_be16(&cpmp->cp_cpcr, CPM_CR_RST | CPM_CR_FLG);
while (in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG);
#endif
#ifdef CONFIG_UCODE_PATCH
cpm_load_patch(cpmp);
#endif
siu_conf = immr_map(im_siu_conf);
out_be32(&siu_conf->sc_sdcr, 1);
immr_unmap(siu_conf);
cpm_muram_init();
}
int __init add_bridge(struct device_node *dev)
{
int len;
struct pci_controller *hose;
struct resource rsrc;
const int *bus_range;
int primary = 1, has_address = 0;
phys_addr_t immr = get_immrbase();
DBG("Adding PCI host bridge %s\n", dev->full_name);
/* Fetch host bridge registers address */
has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
/* Get bus range if any */
bus_range = get_property(dev, "bus-range", &len);
if (bus_range == NULL || len < 2 * sizeof(int)) {
printk(KERN_WARNING "Can't get bus-range for %s, assume"
" bus 0\n", dev->full_name);
}
hose = pcibios_alloc_controller();
if (!hose)
return -ENOMEM;
hose->arch_data = dev;
hose->set_cfg_type = 1;
hose->first_busno = bus_range ? bus_range[0] : 0;
hose->last_busno = bus_range ? bus_range[1] : 0xff;
/* MPC83xx supports up to two host controllers one at 0x8500 from immrbar
* the other at 0x8600, we consider the 0x8500 the primary controller
*/
/* PCI 1 */
if ((rsrc.start & 0xfffff) == 0x8500) {
setup_indirect_pci(hose, immr + 0x8300, immr + 0x8304);
}
/* PCI 2 */
if ((rsrc.start & 0xfffff) == 0x8600) {
setup_indirect_pci(hose, immr + 0x8380, immr + 0x8384);
primary = 0;
hose->bus_offset = hose->first_busno;
mpc83xx_pci2_busno = hose->first_busno;
}
printk(KERN_INFO "Found MPC83xx PCI host bridge at 0x%016llx. "
"Firmware bus number: %d->%d\n",
(unsigned long long)rsrc.start, hose->first_busno,
hose->last_busno);
DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
hose, hose->cfg_addr, hose->cfg_data);
/* Interpret the "ranges" property */
/* This also maps the I/O region and sets isa_io/mem_base */
pci_process_bridge_OF_ranges(hose, dev, primary);
return 0;
}
/***************************************************************************
* hpm200_get_vport
* port : virtual port number
* ZION_INIT_L -> if zero then ZION is initialized.
* p_val : pointer of value
**************************************************************************/
static int hpm200_get_vport( int port, int *p_val )
{
int retval=0;
int val=0;
unsigned long gpio_1 = get_immrbase() + HPM200_REG_DIPSW;
unsigned long gpio_2 = get_immrbase() + HPM200_REG_LED;
volatile unsigned long *reg_1 = NULL;
volatile unsigned long *reg_2 = NULL;
reg_1 = (volatile unsigned long *)ioremap(gpio_1,4);
if (unlikely(NULL==reg_1)){
PERROR("ioremap failed 0x%08lX\n", gpio_1);
retval=-ENOMEM;
goto fail;
}
reg_2 = (volatile unsigned long *)ioremap(gpio_2,4);
if (unlikely(NULL==reg_2)){
PERROR("ioremap failed 0x%08lX\n", gpio_2);
retval=-ENOMEM;
goto fail;
}
switch(port) {
/* ZION_INIT_L */
case P2IOPORT_VPORT_ZION_INIT_L:
val = (ioread32be((void*)reg_1)&(1<<27))?1:0;
break;
default: /* check unsupported port */
PERROR("unsupported ports 0x%08X\n", port);
retval=-EINVAL;
}
fail:
/* complete */
if(NULL!=reg_1) iounmap(reg_1);
if(NULL!=reg_2) iounmap(reg_2);
PDEBUG( "port=0x%08X, val=%d\n", port, val);
*p_val = val;
return retval;
}
static void quanta_lb_restart(char *cmd)
{
void __iomem *immap = ioremap(get_immrbase(), 0x1000000);
if (immap) {
unsigned long pdata = in_be32(immap + 0x90d10);
pdata &= ~(1 << 7);
out_be32(immap + 0x90d10, pdata);
}
fsl_rstcr_restart(NULL);
}
static void init_fcc2_ioports(struct fs_platform_info *fpi)
{
cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
struct device_node *np;
struct resource r;
u32 *bcsr;
struct io_port *io;
u32 tempval;
np = of_find_node_by_type(NULL, "memory");
if (!np) {
printk(KERN_INFO "No memory node in device tree\n");
return;
}
if (of_address_to_resource(np, 1, &r)) {
printk(KERN_INFO "No memory reg property [1] in devicetree\n");
return;
}
of_node_put(np);
io = &immap->im_ioport;
bcsr = ioremap(r.start + 12, sizeof(u32));
/* Enable the PHY */
clrbits32(bcsr, BCSR3_FETHIEN2);
setbits32(bcsr, BCSR3_FETH2_RST);
/* FCC2 are port B/C. */
/* Configure port A and C pins for FCC2 Ethernet. */
tempval = in_be32(&io->iop_pdirb);
tempval &= ~PB2_DIRB0;
tempval |= PB2_DIRB1;
out_be32(&io->iop_pdirb, tempval);
tempval = in_be32(&io->iop_psorb);
tempval &= ~PB2_PSORB0;
tempval |= PB2_PSORB1;
out_be32(&io->iop_psorb, tempval);
setbits32(&io->iop_pparb, PB2_DIRB0 | PB2_DIRB1);
tempval = PC_CLK(fpi->clk_tx - 8) | PC_CLK(fpi->clk_rx - 8);
/* Alter clocks */
clrbits32(&io->iop_psorc, tempval);
clrbits32(&io->iop_pdirc, tempval);
setbits32(&io->iop_pparc, tempval);
cpm2_clk_setup(CPM_CLK_FCC2, fpi->clk_rx, CPM_CLK_RX);
cpm2_clk_setup(CPM_CLK_FCC2, fpi->clk_tx, CPM_CLK_TX);
iounmap(bcsr);
iounmap(immap);
}
void __init m82xx_board_setup(void)
{
cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
struct device_node *np;
struct resource r;
u32 *bcsr;
np = of_find_node_by_type(NULL, "memory");
if (!np) {
printk(KERN_INFO "No memory node in device tree\n");
return;
}
if (of_address_to_resource(np, 1, &r)) {
printk(KERN_INFO "No memory reg property [1] in devicetree\n");
return;
}
of_node_put(np);
bcsr = ioremap(r.start + 4, sizeof(u32));
/* Enable the 2nd UART port */
clrbits32(bcsr, BCSR1_RS232_EN2);
#ifdef CONFIG_SERIAL_CPM_SCC1
clrbits32((u32 *) & immap->im_scc[0].scc_sccm,
UART_SCCM_TX | UART_SCCM_RX);
clrbits32((u32 *) & immap->im_scc[0].scc_gsmrl,
SCC_GSMRL_ENR | SCC_GSMRL_ENT);
#endif
#ifdef CONFIG_SERIAL_CPM_SCC2
clrbits32((u32 *) & immap->im_scc[1].scc_sccm,
UART_SCCM_TX | UART_SCCM_RX);
clrbits32((u32 *) & immap->im_scc[1].scc_gsmrl,
SCC_GSMRL_ENR | SCC_GSMRL_ENT);
#endif
#ifdef CONFIG_SERIAL_CPM_SCC3
clrbits32((u32 *) & immap->im_scc[2].scc_sccm,
UART_SCCM_TX | UART_SCCM_RX);
clrbits32((u32 *) & immap->im_scc[2].scc_gsmrl,
SCC_GSMRL_ENR | SCC_GSMRL_ENT);
#endif
#ifdef CONFIG_SERIAL_CPM_SCC4
clrbits32((u32 *) & immap->im_scc[3].scc_sccm,
UART_SCCM_TX | UART_SCCM_RX);
clrbits32((u32 *) & immap->im_scc[3].scc_gsmrl,
SCC_GSMRL_ENR | SCC_GSMRL_ENT);
#endif
iounmap(bcsr);
iounmap(immap);
}
static int __init fpga_rw_init(void)
{
int status = 0;
immap = ioremap(get_immrbase() + 0xc00 + 0x8, 4);
status = register_chrdev( FPGA_RW_DEV_MAJOR, DRIVER_NAME, &fpga_rw_fops);
if( status < 0)
{
printk("register_chrdev error, stauts = %d \n", status);
}
printk("\n fpga_rw_drv sucess., version = %s \n", FPGA_DRV_VESION );
return status;
}
void __init cpm2_reset(void)
{
#ifdef CONFIG_PPC_85xx
cpm2_immr = ioremap(get_immrbase() + 0x80000, CPM_MAP_SIZE);
#else
cpm2_immr = ioremap(get_immrbase(), CPM_MAP_SIZE);
#endif
/* Reclaim the DP memory for our use.
*/
cpm_muram_init();
/* Tell everyone where the comm processor resides.
*/
cpmp = &cpm2_immr->im_cpm;
#ifndef CONFIG_PPC_EARLY_DEBUG_CPM
/* Reset the CPM.
*/
cpm_command(CPM_CR_RST, 0);
#endif
}
long __init mpc83xx_time_init(void)
{
#define SPCR_OFFSET 0x00000110
#define SPCR_TBEN 0x00400000
__be32 __iomem *spcr = ioremap(get_immrbase() + SPCR_OFFSET, 4);
__be32 tmp;
tmp = in_be32(spcr);
out_be32(spcr, tmp | SPCR_TBEN);
iounmap(spcr);
return 0;
}
long int get_gpio6(void)
{
#define GP1DAT_OFFSET 0x00000c08
#define GP1DAT_MASK 0xfc000000
__be32 __iomem *spcr = ioremap(get_immrbase() + GP1DAT_OFFSET, 4);
__be32 tmp;
tmp = in_be32(spcr);
//out_be32(spcr, tmp | SPCR_TBEN);
//printk(" gpio6 0x%08x\n",tmp);
iounmap(spcr);
return tmp;
}
void __init cam_mapin_extra_chip_select(void)
{
extern phys_addr_t get_immrbase(void);
phys_addr_t immr_base = -1;
immr_base = get_immrbase();
if ( immr_base != -1 ) {
//configuration base
settlbcam(15, immr_base, immr_base, 1024*1024, _PAGE_IO, 0);
//CS1: CPLD
settlbcam(14, SYNO_CPLD_BASE, SYNO_CPLD_BASE, SYNO_CPLD_SIZE, _PAGE_IO, 0);
} else {
printk("HW Settings Error: Failed to get immr_base\n");
}
}
static int mpc83xx_is_pci_agent(void)
{
struct mpc83xx_rcw __iomem *rcw_regs;
int ret;
rcw_regs = ioremap(get_immrbase() + IMMR_RCW_OFFSET,
sizeof(struct mpc83xx_rcw));
if (!rcw_regs)
return -ENOMEM;
ret = !(in_be32(&rcw_regs->rcwhr) & RCW_PCI_HOST);
iounmap(rcw_regs);
return ret;
}
static int pmc_suspend_enter(suspend_state_t state)
{
int ret = 0;
int result;
switch (state) {
#ifdef CONFIG_PPC_85xx
case PM_SUSPEND_MEM:
#ifdef CONFIG_SPE
enable_kernel_spe();
#endif
enable_kernel_fp();
pr_debug("%s: Entering deep sleep\n", __func__);
local_irq_disable();
mpc85xx_enter_deep_sleep(get_immrbase(), POWMGTCSR_DPSLP);
pr_debug("%s: Resumed from deep sleep\n", __func__);
break;
#endif
case PM_SUSPEND_STANDBY:
local_irq_disable();
flush_dcache_L1();
setbits32(&pmc_regs->powmgtcsr, POWMGTCSR_SLP);
/* At this point, the CPU is asleep. */
/* Upon resume, wait for SLP bit to be clear. */
result = spin_event_timeout(
(in_be32(&pmc_regs->powmgtcsr) & POWMGTCSR_SLP) == 0,
10000, 10);
if (!result) {
pr_err("%s: timeout waiting for SLP bit "
"to be cleared\n", __func__);
ret = -ETIMEDOUT;
}
break;
default:
ret = -EINVAL;
}
return ret;
}
static int pmc_suspend_enter(suspend_state_t state)
{
int ret;
u32 powmgtreq = 0x00500000;
switch (state) {
case PM_SUSPEND_MEM:
#ifdef CONFIG_SPE
enable_kernel_spe();
#endif
pr_debug("Entering deep sleep\n");
local_irq_disable();
mpc85xx_enter_deep_sleep(get_immrbase(),
powmgtreq);
pr_debug("Resumed from deep sleep\n");
return 0;
/* else fall-through */
case PM_SUSPEND_STANDBY:
local_irq_disable();
/* Start the power monitor using FPGA */
pixis_start_pm_sleep();
setbits32(&pmc_regs->pmcsr, PMCSR_SLP);
/* At this point, the CPU is asleep. */
/* Upon resume, wait for SLP bit to be clear. */
ret = spin_event_timeout((in_be32(&pmc_regs->pmcsr) & PMCSR_SLP)
== 0, 10000, 10) ? 0 : -ETIMEDOUT;
if (ret)
dev_err(pmc_dev,
"timeout waiting for SLP bit to be cleared\n");
/* Stop the power monitor using FPGA */
pixis_stop_pm_sleep();
return 0;
default:
return -EINVAL;
}
}
static void __init
smp_86xx_release_core(int nr)
{
__be32 __iomem *mcm_vaddr;
unsigned long pcr;
if (nr < 0 || nr >= NR_CPUS)
return;
mcm_vaddr = ioremap(get_immrbase() + MPC86xx_MCM_OFFSET,
MPC86xx_MCM_SIZE);
pcr = in_be32(mcm_vaddr + (MCM_PORT_CONFIG_OFFSET >> 2));
pcr |= 1 << (nr + 24);
out_be32(mcm_vaddr + (MCM_PORT_CONFIG_OFFSET >> 2), pcr);
iounmap(mcm_vaddr);
}
static void init_scc4_uart_ioports(struct fs_uart_platform_info *data)
{
cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
setbits32(&immap->im_ioport.iop_ppard, 0x00000600);
clrbits32(&immap->im_ioport.iop_psord, 0x00000600);
clrbits32(&immap->im_ioport.iop_pdird, 0x00000200);
setbits32(&immap->im_ioport.iop_pdird, 0x00000400);
clrbits32(&immap->im_cpmux.cmx_scr, (0x00000007 << (4 - data->clk_tx)));
clrbits32(&immap->im_cpmux.cmx_scr, (0x00000038 << (4 - data->clk_rx)));
setbits32(&immap->im_cpmux.cmx_scr,
((data->clk_tx - 1) << (4 - data->clk_tx)));
setbits32(&immap->im_cpmux.cmx_scr,
((data->clk_rx - 1) << (4 - data->clk_rx)));
iounmap(immap);
}
void mpc83xx_restart(char *cmd)
{
#define RST_OFFSET 0x00000900
#define RST_PROT_REG 0x00000018
#define RST_CTRL_REG 0x0000001c
__be32 __iomem *reg;
/* map reset register space */
reg = ioremap(get_immrbase() + 0x900, 0xff);
local_irq_disable();
/* enable software reset "RSTE" */
out_be32(reg + (RST_PROT_REG >> 2), 0x52535445);
/* set software hard reset */
out_be32(reg + (RST_CTRL_REG >> 2), 0x2);
for (;;) ;
}
static void mpc837x_rdb_sd_cfg(void)
{
void __iomem *im;
im = ioremap(get_immrbase(), 0x1000);
if (!im) {
WARN_ON(1);
return;
}
/*
* On RDB boards (in contrast to MDS) USBB pins are used for SD only,
* so we can safely mux them away from the USB block.
*/
clrsetbits_be32(im + MPC83XX_SICRL_OFFS, MPC837X_SICRL_USBB_MASK,
MPC837X_SICRL_SD);
clrsetbits_be32(im + MPC83XX_SICRH_OFFS, MPC837X_SICRH_SPI_MASK,
MPC837X_SICRH_SD);
iounmap(im);
}
void __init cpm_reset(void)
{
sysconf8xx_t __iomem *siu_conf;
mpc8xx_immr = ioremap(get_immrbase(), 0x4000);
if (!mpc8xx_immr) {
printk(KERN_CRIT "Could not map IMMR\n");
return;
}
cpmp = &mpc8xx_immr->im_cpm;
#ifndef CONFIG_PPC_EARLY_DEBUG_CPM
/* Perform a reset.
*/
out_be16(&cpmp->cp_cpcr, CPM_CR_RST | CPM_CR_FLG);
/* Wait for it.
*/
while (in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG);
#endif
#ifdef CONFIG_UCODE_PATCH
cpm_load_patch(cpmp);
#endif
/* Set SDMA Bus Request priority 5.
* On 860T, this also enables FEC priority 6. I am not sure
* this is what we really want for some applications, but the
* manual recommends it.
* Bit 25, FAM can also be set to use FEC aggressive mode (860T).
*/
siu_conf = immr_map(im_siu_conf);
if ((mfspr(SPRN_IMMR) & 0xffff) == 0x0900) /* MPC885 */
out_be32(&siu_conf->sc_sdcr, 0x40);
else
out_be32(&siu_conf->sc_sdcr, 1);
immr_unmap(siu_conf);
cpm_muram_init();
}
int mpc837x_usb_cfg(void)
{
void __iomem *immap;
struct device_node *np = NULL;
const void *prop;
const void *dr_mode = NULL; /* 2011.2.28, added by panasonic ---> */
int ret = 0;
np = of_find_compatible_node(NULL, NULL, "fsl-usb2-dr");
if (!np)
return -ENODEV;
prop = of_get_property(np, "phy_type", NULL);
if (!prop || (strcmp(prop, "ulpi") && strcmp(prop, "serial"))) {
printk(KERN_WARNING "837x USB PHY type not supported\n");
of_node_put(np);
return -EINVAL;
}
dr_mode = of_get_property(np, "dr_mode", NULL); /* 2011.2.28, added by panasonic */
/* Map IMMR space for pin and clock settings */
immap = ioremap(get_immrbase(), 0x1000);
if (!immap) {
of_node_put(np);
return -ENOMEM;
}
/* Configure clock */
clrsetbits_be32(immap + MPC83XX_SCCR_OFFS, MPC837X_SCCR_USB_DRCM_11,
(!dr_mode||strcmp(dr_mode,"none"))? MPC837X_SCCR_USB_DRCM_11: 0);/* 2011.2.28, modified by panasonic (SAV) */
/* Configure pin mux for ULPI/serial */
clrsetbits_be32(immap + MPC83XX_SICRL_OFFS, MPC837X_SICRL_USB_MASK,
MPC837X_SICRL_USB_ULPI);
iounmap(immap);
of_node_put(np);
return ret;
}
/***************************************************************************
* hpm200_init
**************************************************************************/
static inline int hpm200_init( struct p2ioport_info_s *info )
{
/* print init Message. */
PINFO( " board type: %s(ver. %s)\n", BOARDTYPE_NAME, HPM200_VER );
/* init debug switch. */
HPM200_DEBUG = 0;
/* set info. */
info->nr_dipsw = HPM200_MAXNR_DIPSW;
info->nr_led = HPM200_MAXNR_LED;
info->nr_rotarysw = HPM200_MAXNR_ROTARYSW;
info->nr_device = HPM200_MAXNR_DEVICE;
info->ops = &hpm200_ops;
strcpy( info->name, BOARDTYPE_NAME );
/* set IMMR base address. */
HPM200_IMMRBAR = (unsigned long)get_immrbase();
PDEBUG( "IMMRBAR: 0x%08lX\n", HPM200_IMMRBAR );
/* init regs. */
regs.dipsw = ioremap( (HPM200_REG_DIPSW+HPM200_IMMRBAR), 4 );
if ( unlikely(NULL == regs.dipsw) ) goto EXIT;
regs.led = ioremap( (HPM200_REG_LED+HPM200_IMMRBAR) , 4 );
if ( unlikely(NULL == regs.led) ) goto FAIL_LED;
/* success. */
return (0);
FAIL_LED:
iounmap( regs.dipsw );
regs.dipsw = NULL;
EXIT:
PERROR("ioremap failed!\n");
return (-ENOMEM);
}
int mpc837x_usb_cfg(void)
{
void __iomem *immap;
struct device_node *np = NULL;
const void *prop;
int ret = 0;
np = of_find_compatible_node(NULL, NULL, "fsl-usb2-dr");
if (!np || !of_device_is_available(np))
return -ENODEV;
prop = of_get_property(np, "phy_type", NULL);
if (!prop || (strcmp(prop, "ulpi") && strcmp(prop, "serial"))) {
printk(KERN_WARNING "837x USB PHY type not supported\n");
of_node_put(np);
return -EINVAL;
}
immap = ioremap(get_immrbase(), 0x1000);
if (!immap) {
of_node_put(np);
return -ENOMEM;
}
clrsetbits_be32(immap + MPC83XX_SCCR_OFFS, MPC837X_SCCR_USB_DRCM_11,
MPC837X_SCCR_USB_DRCM_11);
clrsetbits_be32(immap + MPC83XX_SICRL_OFFS, MPC837X_SICRL_USB_MASK,
MPC837X_SICRL_USB_ULPI);
iounmap(immap);
of_node_put(np);
return ret;
}
void __init mpc85xx_ads_pic_init(void)
{
struct mpic *mpic1;
phys_addr_t OpenPIC_PAddr;
/* Determine the Physical Address of the OpenPIC regs */
OpenPIC_PAddr = get_immrbase() + MPC85xx_OPENPIC_OFFSET;
mpic1 = mpic_alloc(OpenPIC_PAddr,
MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
4, MPC85xx_OPENPIC_IRQ_OFFSET, 0, 250,
mpc85xx_ads_openpic_initsenses,
sizeof(mpc85xx_ads_openpic_initsenses),
" OpenPIC ");
BUG_ON(mpic1 == NULL);
mpic_assign_isu(mpic1, 0, OpenPIC_PAddr + 0x10200);
mpic_assign_isu(mpic1, 1, OpenPIC_PAddr + 0x10280);
mpic_assign_isu(mpic1, 2, OpenPIC_PAddr + 0x10300);
mpic_assign_isu(mpic1, 3, OpenPIC_PAddr + 0x10380);
mpic_assign_isu(mpic1, 4, OpenPIC_PAddr + 0x10400);
mpic_assign_isu(mpic1, 5, OpenPIC_PAddr + 0x10480);
mpic_assign_isu(mpic1, 6, OpenPIC_PAddr + 0x10500);
mpic_assign_isu(mpic1, 7, OpenPIC_PAddr + 0x10580);
/* dummy mappings to get to 48 */
mpic_assign_isu(mpic1, 8, OpenPIC_PAddr + 0x10600);
mpic_assign_isu(mpic1, 9, OpenPIC_PAddr + 0x10680);
mpic_assign_isu(mpic1, 10, OpenPIC_PAddr + 0x10700);
mpic_assign_isu(mpic1, 11, OpenPIC_PAddr + 0x10780);
/* External ints */
mpic_assign_isu(mpic1, 12, OpenPIC_PAddr + 0x10000);
mpic_assign_isu(mpic1, 13, OpenPIC_PAddr + 0x10080);
mpic_assign_isu(mpic1, 14, OpenPIC_PAddr + 0x10100);
mpic_init(mpic1);
}
/* TDM register programming */
static int tdm_fsl_starlite_reg_init(struct tdm_priv *priv)
{
int i;
phys_addr_t base = get_immrbase();
#ifdef CONFIG_MPC831x_RDB
__be32 __iomem *psccr;
__be32 __iomem *psicr;
psccr = ioremap(base + SCCR_OFFSET, 4);
if (!psccr)
return -1;
/* CSB:TDM clk =1 */
clrsetbits_be32(psccr, SCCR_TDM_MASK, TDM_CM_01);
iounmap(psccr);
psicr = ioremap(base + SICRL_OFFSET, 4);
if (!psicr)
return -1;
/* enable TDM in SICR */
clrbits32(psicr, SICRL_TDM_MASK);
iounmap(psicr);
#endif
#ifdef CONFIG_MPC85xx_RDB
__be32 __iomem *pmuxcr;
pmuxcr = ioremap(base + PMUXCR_OFFSET, 4);
if (!pmuxcr)
return -1;
out_be32(pmuxcr, in_be32(pmuxcr) | PMUXCR_TDM_ENABLE);
iounmap(pmuxcr);
#endif
/* channel/group round robin */
out_be32(&priv->dmac_regs->dmacr, DMACR_ERGA | DMACR_ERCA);
/* Enable error Interrupts for TDM Rx &Tx */
out_8(&priv->dmac_regs->dmaseei, TDMTX_DMA_CH);
out_8(&priv->dmac_regs->dmaseei, TDMRX_DMA_CH);
out_be32(&priv->dmac_regs->dmagpor, DMAGPOR_SNOOP);
tx_tcd_init(priv);
rx_tcd_init(priv);
/* TDM RD->TD loopback, Share T/R Fsync,Clock */
if (priv->cfg.loopback)
out_be32(&priv->tdm_regs->gir, GIR_LPBK | GIR_RTS);
else
out_be32(&priv->tdm_regs->gir, GIR_RTS);
/*
Rx Water mark 0, FIFO enable, Wide fifo, DMA enable for RX,
Receive Sync out, syncwidth = ch width, Rx clk out,zero sync,
falling edge , data order
*/
out_be32(&priv->tdm_regs->rir,
RIR_RFWM(0) | RIR_RFEN | RIR_RWEN | RIR_RDMA | RIR_RSL |
RIR_RSO | RIR_RCOE | RIR_RRDO | RIR_RFSD(0x01));
out_be32(&priv->tdm_regs->tir,
TIR_TFWM(0) | TIR_TFEN | TIR_TWEN | TIR_TDMA | TIR_TSL |
TIR_TSO | TIR_TRDO | TIR_TFSD(0x01));
/* no of channels ,Channel size-coading */
out_be32(&priv->tdm_regs->rfp,
RFP_RNCF(priv->cfg.num_ch) | RFP_RCS(priv->cfg.ch_type));
out_be32(&priv->tdm_regs->tfp,
TFP_TNCF(priv->cfg.num_ch) | TFP_TCS(priv->cfg.ch_type));
out_be32(&priv->tdm_regs->rier, 0);
out_be32(&priv->tdm_regs->tier, 0);
/* clear all receive and transmit chs */
for (i = 0; i < 4; i++) {
out_be32(&priv->tdm_regs->tcma[i], 0);
out_be32(&priv->tdm_regs->tcen[i], 0);
out_be32(&priv->tdm_regs->rcen[i], 0);
}
return 0;
}
/* ************************************************************************
*
* Setup the architecture
*
*/
static void __init mpc836x_mds_setup_arch(void)
{
struct device_node *np;
u8 __iomem *bcsr_regs = NULL;
if (ppc_md.progress)
ppc_md.progress("mpc836x_mds_setup_arch()", 0);
/* Map BCSR area */
np = of_find_node_by_name(NULL, "bcsr");
if (np) {
struct resource res;
of_address_to_resource(np, 0, &res);
bcsr_regs = ioremap(res.start, resource_size(&res));
of_node_put(np);
}
#ifdef CONFIG_PCI
for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
mpc83xx_add_bridge(np);
#endif
#ifdef CONFIG_QUICC_ENGINE
qe_reset();
if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
par_io_init(np);
of_node_put(np);
for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
par_io_of_config(np);
#ifdef CONFIG_QE_USB
/* Must fixup Par IO before QE GPIO chips are registered. */
par_io_config_pin(1, 2, 1, 0, 3, 0); /* USBOE */
par_io_config_pin(1, 3, 1, 0, 3, 0); /* USBTP */
par_io_config_pin(1, 8, 1, 0, 1, 0); /* USBTN */
par_io_config_pin(1, 10, 2, 0, 3, 0); /* USBRXD */
par_io_config_pin(1, 9, 2, 1, 3, 0); /* USBRP */
par_io_config_pin(1, 11, 2, 1, 3, 0); /* USBRN */
par_io_config_pin(2, 20, 2, 0, 1, 0); /* CLK21 */
#endif /* CONFIG_QE_USB */
}
if ((np = of_find_compatible_node(NULL, "network", "ucc_geth"))
!= NULL){
uint svid;
/* Reset the Ethernet PHY */
#define BCSR9_GETHRST 0x20
clrbits8(&bcsr_regs[9], BCSR9_GETHRST);
udelay(1000);
setbits8(&bcsr_regs[9], BCSR9_GETHRST);
/* handle mpc8360ea rev.2.1 erratum 2: RGMII Timing */
svid = mfspr(SPRN_SVR);
if (svid == 0x80480021) {
void __iomem *immap;
immap = ioremap(get_immrbase() + 0x14a8, 8);
/*
* IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
* IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
*/
setbits32(immap, 0x0c003000);
/*
* IMMR + 0x14AC[20:27] = 10101010
* (data delay for both UCC's)
*/
clrsetbits_be32(immap + 4, 0xff0, 0xaa0);
iounmap(immap);
}
iounmap(bcsr_regs);
of_node_put(np);
}
#endif /* CONFIG_QUICC_ENGINE */
}
/* TDM register programming */
static int tdm_fsl_reg_init(struct tdm_priv *priv)
{
int i;
int ch_size_type;
phys_addr_t base = get_immrbase();
struct tdm_adapter *adap;
if (!priv) {
pr_err("%s: Invalid handle\n", __func__);
return -EINVAL;
}
adap = priv->adap;
/* channel/group round robin */
out_be32(&priv->dmac_regs->dmacr, DMACR_ERGA | DMACR_ERCA);
/* Enable error Interrupts for TDM Rx &Tx */
out_8(&priv->dmac_regs->dmaseei, TDMTX_DMA_CH);
out_8(&priv->dmac_regs->dmaseei, TDMRX_DMA_CH);
out_be32(&priv->dmac_regs->dmagpor, DMAGPOR_SNOOP);
tx_tcd_init(priv);
rx_tcd_init(priv);
/* TDM RD->TD loopback, Share T/R Fsync,Clock */
if (adap->adapt_cfg.loopback)
out_be32(&priv->tdm_regs->gir, GIR_LPBK | GIR_RTS);
else
out_be32(&priv->tdm_regs->gir, GIR_RTS);
/*
Rx Water mark 0, FIFO enable, Wide fifo, DMA enable for RX,
Receive Sync out, syncwidth = ch width, Rx clk out,zero sync,
falling edge , data order
*/
out_be32(&priv->tdm_regs->rir,
RIR_RFWM(RIR_RFWM_VAL) | RIR_RFEN | RIR_RWEN | RIR_RDMA |
RIR_RSL | RIR_RSO | RIR_RCOE | RIR_RRDO |
RIR_RFSD(RIR_RFSD_VAL));
out_be32(&priv->tdm_regs->tir,
TIR_TFWM(TIR_RFWM_VAL) | TIR_TFEN | TIR_TWEN | TIR_TDMA |
TIR_TSL | TIR_TSO | TIR_TRDO | TIR_TFSD(TIR_RFSD_VAL));
/* no of channels ,Channel size-coading */
switch (adap->adapt_cfg.ch_size_type) {
case CHANNEL_8BIT_LIN:
ch_size_type = CHANNEL_8BIT_LIN;
break;
case CHANNEL_8BIT_ULAW:
ch_size_type = CHANNEL_8BIT_ULAW;
break;
case CHANNEL_8BIT_ALAW:
ch_size_type = CHANNEL_8BIT_ALAW;
break;
case CHANNEL_16BIT_LIN:
ch_size_type = CHANNEL_16BIT_LIN;
break;
default:
pr_err("%s:Invalid channel_size_type.\n"
"Setting channel to default size: 16 bits", __func__);
ch_size_type = CHANNEL_16BIT_LIN;
}
out_be32(&priv->tdm_regs->rfp,
RFP_RNCF(adap->adapt_cfg.num_ch) | RFP_RCS(ch_size_type));
out_be32(&priv->tdm_regs->tfp,
TFP_TNCF(adap->adapt_cfg.num_ch) | TFP_TCS(ch_size_type));
out_be32(&priv->tdm_regs->rier, 0);
out_be32(&priv->tdm_regs->tier, 0);
/* clear all receive and transmit chs */
for (i = 0; i < 4; i++) {
out_be32(&priv->tdm_regs->tcma[i], 0);
out_be32(&priv->tdm_regs->tcen[i], 0);
out_be32(&priv->tdm_regs->rcen[i], 0);
}
return 0;
}
