/*
* Initialize UPM for NAND flash access.
*/
static void nand_upm_setup (volatile ccsr_lbc_t *lbc)
{
uint i;
uint or3 = CONFIG_SYS_OR3_PRELIM;
uint clock = get_lbc_clock ();
out_be32 (&lbc->br3, 0); /* disable bank and reset all bits */
out_be32 (&lbc->br3, CONFIG_SYS_BR3_PRELIM);
/*
* Search appropriate UPM table for bus clock.
* If the bus clock exceeds a tolerated value, take the UPM timing for
* the next higher supported frequency to ensure that access works
* (even the access may be slower then).
*/
for (i = 0; (i < UPM_FREQS) && (clock > upm_freq_table[i].freq); i++)
;
if (i >= UPM_FREQS)
/* no valid entry found */
/* take last entry with configuration for max. bus clock */
i--;
if (upm_freq_table[i].ehtr) {
/* EHTR must be set due to TQM8548 timing specification */
or3 |= OR_UPM_EHTR;
}
if (upm_freq_table[i].ead)
/* EAD must be set due to TQM8548 timing specification */
or3 |= OR_UPM_EAD;
out_be32 (&lbc->or3, or3);
/* Assign address of table */
nand_upm_patt = upm_freq_table[i].upm_patt;
for (i = 0; i < 64; i++) {
upmb_write (i, *nand_upm_patt);
nand_upm_patt++;
}
/* Put UPM back to normal operation mode */
if (upm_freq_table[i].gpl4_disable)
/* GPL4 must be disabled according to timing specification */
out_be32 (&lbc->mbmr, MxMR_OP_NORM | MxMR_GPL_x4DIS);
return;
}
/*
* Initialize Local Bus
*/
void local_bus_init (void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint lbc_mhz = get_lbc_clock () / 1000000;
#ifdef CONFIG_MPC8548
uint svr = get_svr ();
uint lcrr;
/*
* MPC revision < 2.0
* According to MPC8548E_Device_Errata Rev. L, Erratum LBIU1:
* Modify engineering use only register at address 0xE_0F20.
* "1. Read register at offset 0xE_0F20
* 2. And value with 0x0000_FFFF
* 3. OR result with 0x0000_0004
* 4. Write result back to offset 0xE_0F20."
*
* According to MPC8548E_Device_Errata Rev. L, Erratum LBIU2:
* Modify engineering use only register at address 0xE_0F20.
* "1. Read register at offset 0xE_0F20
* 2. And value with 0xFFFF_FFDF
* 3. Write result back to offset 0xE_0F20."
*
* Since it is the same register, we do the modification in one step.
*/
if (SVR_MAJ (svr) < 2) {
uint dummy = gur->lbiuiplldcr1;
dummy &= 0x0000FFDF;
dummy |= 0x00000004;
gur->lbiuiplldcr1 = dummy;
}
lcrr = CONFIG_SYS_LBC_LCRR;
/*
* Local Bus Clock > 83.3 MHz. According to timing
* specifications set LCRR[EADC] to 2 delay cycles.
*/
if (lbc_mhz > 83) {
lcrr &= ~LCRR_EADC;
lcrr |= LCRR_EADC_2;
}
/*
* According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30
* disable PLL bypass for Local Bus Clock > 83 MHz.
*/
if (lbc_mhz >= 66)
lcrr &= (~LCRR_DBYP); /* DLL Enabled */
else
lcrr |= LCRR_DBYP; /* DLL Bypass */
lbc->lcrr = lcrr;
asm ("sync;isync;msync");
/*
* According to MPC8548ERMAD Rev.1.3 read back LCRR
* and terminate with isync
*/
lcrr = lbc->lcrr;
asm ("isync;");
/* let DLL stabilize */
udelay (500);
#else /* !CONFIG_MPC8548 */
/*
* Errata LBC11.
* Fix Local Bus clock glitch when DLL is enabled.
*
* If localbus freq is < 66MHz, DLL bypass mode must be used.
* If localbus freq is > 133MHz, DLL can be safely enabled.
* Between 66 and 133, the DLL is enabled with an override workaround.
*/
if (lbc_mhz < 66) {
lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */
lbc->ltedr = LTEDR_BMD | LTEDR_PARD | LTEDR_WPD | LTEDR_WARA |
LTEDR_RAWA | LTEDR_CSD; /* Disable all error checking */
} else if (lbc_mhz >= 133) {
lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
} else {
/*
* On REV1 boards, need to change CLKDIV before enable DLL.
* Default CLKDIV is 8, change it to 4 temporarily.
*/
uint pvr = get_pvr ();
uint temp_lbcdll = 0;
if (pvr == PVR_85xx_REV1) {
/* FIXME: Justify the high bit here. */
lbc->lcrr = 0x10000004;
}
lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
udelay (200);
/*
* Sample LBC DLL ctrl reg, upshift it to set the
* override bits.
*/
temp_lbcdll = gur->lbcdllcr;
gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
asm ("sync;isync;msync");
}
#endif /* !CONFIG_MPC8548 */
#ifdef CONFIG_CAN_DRIVER
/*
* According to timing specifications EAD must be
* set if Local Bus Clock is > 83 MHz.
*/
if (lbc_mhz > 83)
set_lbc_or(2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD);
else
set_lbc_or(2, CONFIG_SYS_OR2_CAN);
set_lbc_br(2, CONFIG_SYS_BR2_CAN);
/* LGPL4 is UPWAIT */
out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL_x4DIS | MxMR_WLFx_3X);
/* Initialize UPMC for CAN: single read */
upmc_write (0x00, 0xFFFFED00);
upmc_write (0x01, 0xCCFFCC00);
upmc_write (0x02, 0x00FFCF00);
upmc_write (0x03, 0x00FFCF00);
upmc_write (0x04, 0x00FFDC00);
upmc_write (0x05, 0x00FFCF00);
upmc_write (0x06, 0x00FFED00);
upmc_write (0x07, 0x3FFFCC07);
/* Initialize UPMC for CAN: single write */
upmc_write (0x18, 0xFFFFED00);
upmc_write (0x19, 0xCCFFEC00);
upmc_write (0x1A, 0x00FFED80);
upmc_write (0x1B, 0x00FFED80);
upmc_write (0x1C, 0x00FFFC00);
upmc_write (0x1D, 0x0FFFEC00);
upmc_write (0x1E, 0x0FFFEF00);
upmc_write (0x1F, 0x3FFFEC05);
#endif /* CONFIG_CAN_DRIVER */
}
