static struct mem_timings *setup_clock(void) { struct mem_timings *mem = get_mem_timings(); struct arm_clk_ratios *arm_ratios = get_arm_clk_ratios(); if (!mem) { die("Unable to auto-detect memory timings\n"); } system_clock_init(mem, arm_ratios); return mem; }
void main(void) { struct mem_timings *mem; struct arm_clk_ratios *arm_ratios; int ret; void *entry; clock_set_rate(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ /* Clock must be initialized before console_init, otherwise you may need * to re-initialize serial console drivers again. */ mem = get_mem_timings(); arm_ratios = get_arm_clk_ratios(); system_clock_init(mem, arm_ratios); console_init(); /* * FIXME: Do necessary I2C init so low-level PMIC code doesn't need to. * Also, we should only call power_init() on cold boot. */ power_init(); if (!mem) { printk(BIOS_CRIT, "Unable to auto-detect memory timings\n"); while(1); } printk(BIOS_SPEW, "man: 0x%x type: 0x%x, div: 0x%x, mhz: 0x%x\n", mem->mem_manuf, mem->mem_type, mem->mpll_mdiv, mem->frequency_mhz); ret = ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE); if (ret) { printk(BIOS_ERR, "Memory controller init failed, err: %x\n", ret); while(1); } /* Set up MMU and caches */ mmu_setup_by_mva(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB); initialize_s5p_mshc(); graphics(); entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); printk(BIOS_INFO, "entry is 0x%p, leaving romstage.\n", entry); stage_exit(entry); }