phys_size_t initdram (int board_type) { volatile struct mpc5xxx_mmap_ctl *mm = (struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR; volatile struct mpc5xxx_cdm *cdm = (struct mpc5xxx_cdm *) MPC5XXX_CDM; volatile struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *) MPC5XXX_SDRAM; ulong dramsize = 0; #ifndef CONFIG_SYS_RAMBOOT long test1, test2; /* setup SDRAM chip selects */ out_be32(&mm->sdram0, 0x0000001c); /* 512MB at 0x0 */ out_be32(&mm->sdram1, 0x40000000); /* disabled */ /* setup config registers */ out_be32(&sdram->config1, SDRAM_CONFIG1); out_be32(&sdram->config2, SDRAM_CONFIG2); #if SDRAM_DDR /* set tap delay */ out_be32(&cdm->porcfg, SDRAM_TAPDELAY); #endif /* find RAM size using SDRAM CS0 only */ sdram_start(0); test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000); sdram_start(1); test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000); if (test1 > test2) { sdram_start(0); dramsize = test1; } else { dramsize = test2; } /* memory smaller than 1MB is impossible */ if (dramsize < (1 << 20)) { dramsize = 0; } /* set SDRAM CS0 size according to the amount of RAM found */ if (dramsize > 0) { out_be32(&mm->sdram0, 0x13 + __builtin_ffs(dramsize >> 20) - 1); } else {
phys_size_t initdram (int board_type) { ulong dramsize = 0; ulong dramsize2 = 0; uint svr, pvr; #ifndef CONFIG_SYS_RAMBOOT ulong test1, test2; /* setup SDRAM chip selects */ out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS0CFG, 0x0000001c); /* 512MB at 0x0 */ out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS1CFG, 0x80000000);/* disabled */ __asm__ volatile ("sync"); /* setup config registers */ out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1); out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2); __asm__ volatile ("sync"); #if SDRAM_DDR /* set tap delay */ out_be32 ((unsigned __iomem *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY); __asm__ volatile ("sync"); #endif /* find RAM size using SDRAM CS0 only */ sdram_start (0); test1 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000); sdram_start(1); test2 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000); if (test1 > test2) { sdram_start (0); dramsize = test1; } else { dramsize = test2; } /* memory smaller than 1MB is impossible */ if (dramsize < (1 << 20)) { dramsize = 0; } /* set SDRAM CS0 size according to the amount of RAM found */ if (dramsize > 0) { out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS0CFG, (0x13 + __builtin_ffs(dramsize >> 20) - 1)); } else {
/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx * * This routine performs standard 8260 initialization sequence * and calculates the available memory size. It may be called * several times to try different SDRAM configurations on both * 60x and local buses. */ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, ulong orx, volatile uchar * base) { volatile uchar c = 0xff; volatile uint *sdmr_ptr; volatile uint *orx_ptr; ulong maxsize, size; int i; /* We must be able to test a location outsize the maximum legal size * to find out THAT we are outside; but this address still has to be * mapped by the controller. That means, that the initial mapping has * to be (at least) twice as large as the maximum expected size. */ maxsize = (1 + (~orx | 0x7fff))/* / 2*/; sdmr_ptr = &memctl->memc_psdmr; orx_ptr = &memctl->memc_or1; *orx_ptr = orx; /* * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): * * "At system reset, initialization software must set up the * programmable parameters in the memory controller banks registers * (ORx, BRx, P/LSDMR). After all memory parameters are configured, * system software should execute the following initialization sequence * for each SDRAM device. * * 1. Issue a PRECHARGE-ALL-BANKS command * 2. Issue eight CBR REFRESH commands * 3. Issue a MODE-SET command to initialize the mode register * * The initial commands are executed by setting P/LSDMR[OP] and * accessing the SDRAM with a single-byte transaction." * * The appropriate BRx/ORx registers have already been set when we * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. */ *sdmr_ptr = sdmr | PSDMR_OP_PREA; *base = c; *sdmr_ptr = sdmr | PSDMR_OP_CBRR; for (i = 0; i < 8; i++) *base = c; *sdmr_ptr = sdmr | PSDMR_OP_MRW; *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */ *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; *base = c; size = get_ram_size ((long *)base, maxsize); *orx_ptr = orx | ~(size - 1); return (size); }
int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ /* Fix this */ gd->ram_size = get_ram_size((volatile void *)kw_sdram_bar(0), kw_sdram_bs(0)); return 0; }
int dram_init(void) { gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); return 0; }
int dram_init (void) { /* dram_init must store complete ramsize in gd->ram_size */ gd->ram_size = get_ram_size((void *)SCB9328_SDRAM_1, SCB9328_SDRAM_1_SIZE); return 0; }
int dram_init(void) { /* use the DDR controllers configured size */ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, (ulong)imx_ddr_size()); return 0; }
phys_size_t initdram (int board_type) { ulong size; size = dramSetup (); return get_ram_size(CFG_SDRAM_BASE, size); }
long int initdram (int board_type) { ulong dramsize = 0; ulong dramsize2 = 0; uint svr, pvr; #ifndef CFG_RAMBOOT ulong test1, test2; /* setup SDRAM chip selects */ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */ __asm__ volatile ("sync"); /* setup config registers */ *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; __asm__ volatile ("sync"); #if SDRAM_DDR /* set tap delay */ *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; __asm__ volatile ("sync"); #endif /* find RAM size using SDRAM CS0 only */ sdram_start(0); test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); sdram_start(1); test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); if (test1 > test2) { sdram_start(0); dramsize = test1; } else { dramsize = test2; } /* memory smaller than 1MB is impossible */ if (dramsize < (1 << 20)) { dramsize = 0; } /* set SDRAM CS0 size according to the amount of RAM found */ if (dramsize > 0) { *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; } else {
int dram_init(void) { gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; gd->ram_size = gd->bd->bi_dram[0].size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE); return 0; }
int dram_init(void) { /* check for the maximum amount of memory possible on AP7000 devices */ gd->ram_size = get_ram_size( (void *)CONFIG_SYS_SDRAM_BASE, (256<<20)); return 0; }
/* * DRAM configuration */ int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); return 0; }
int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ gd->ram_size = get_ram_size( (void *)CONFIG_SYS_SDRAM_BASE, CONFIG_MAX_RAM_BANK_SIZE); return 0; }
/* * ATTENTION: Although partially referenced initdram does NOT make real use * use of CONFIG_SYS_SDRAM_BASE. The code does not work if * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000. */ phys_size_t initdram(int board_type) { struct mpc5xxx_mmap_ctl *mmap_ctl = (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR; struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM; ulong dramsize = 0; ulong dramsize2 = 0; uint svr, pvr; if (gt_ifm_sensor_type == O2DNT2) { /* activate SDRAM CS1 */ setbits_be32((void *)MPC5XXX_GPS_PORT_CONFIG, 0x80000000); } #ifndef CONFIG_SYS_RAMBOOT ulong test1, test2; /* setup SDRAM chip selects */ out_be32(&mmap_ctl->sdram0, 0x0000001E); /* 2 GB at 0x0 */ out_be32(&mmap_ctl->sdram1, 0x00000000); /* disabled */ /* setup config registers */ out_be32(&sdram->config1, SDRAM_CONFIG1); out_be32(&sdram->config2, SDRAM_CONFIG2); /* find RAM size using SDRAM CS0 only */ sdram_start(0); test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000); sdram_start(1); test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000); if (test1 > test2) { sdram_start(0); dramsize = test1; } else { dramsize = test2; } /* memory smaller than 1MB is impossible */ if (dramsize < (1 << 20)) dramsize = 0; /* set SDRAM CS0 size according to the amount of RAM found */ if (dramsize > 0) { out_be32(&mmap_ctl->sdram0, (0x13 + __builtin_ffs(dramsize >> 20) - 1)); } else {
int dram_init(void) { #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) ddrmc_init(); #endif gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); return 0; }
int dram_init(void) { /* Since we have discontinuous RAM configuration, just put * bank1 here for relocation */ gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); return 0; }
static long int dram_size (long int mbmr_value, long int *base, long int maxsize) { volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; memctl->memc_mbmr = mbmr_value; return (get_ram_size(base, maxsize)); }
int dram_init(void) { u32 size; size = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); gd->ram_size = size; return 0; }
int dram_init(void) { setup_iomux_ddr(); ddr_ctrl_init(); gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); return 0; }
int dram_init(void) { gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE); zynq_ddrc_init(); return 0; }
/* * Autodetect onboard DDR SDRAM on 440 platforms * * NOTE: Some of the hardcoded values are hardware dependant, * so this should be extended for other future boards * using this routine! */ long int initdram(int board_type) { int i; int tr1_bank1; for (i=0; i<N_MB0CF; i++) { /* * Disable memory controller. */ mtsdram(mem_cfg0, 0x00000000); /* * Setup some default */ mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */ mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */ mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ /* * Following for CAS Latency = 2.5 @ 133 MHz PLB */ mtsdram(mem_b0cr, mb0cf[i].reg); mtsdram(mem_tr0, 0x41094012); mtsdram(mem_tr1, 0x80800800); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/ mtsdram(mem_rtr, 0x7e000000); /* Interval 15.20µs @ 133MHz PLB*/ mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM*/ udelay(400); /* Delay 200 usecs (min) */ /* * Enable the controller, then wait for DCEN to complete */ mtsdram(mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ udelay(10000); if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) { /* * Optimize TR1 to current hardware environment */ sdram_tr1_set(0x00000000, &tr1_bank1); mtsdram(mem_tr1, (tr1_bank1 | 0x80800800)); #ifdef CONFIG_SDRAM_ECC ecc_init(0, mb0cf[i].size); #endif /* * OK, size detected -> all done */ return mb0cf[i].size; } } return 0; /* nothing found ! */ }
int dram_init(void) { gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE) + get_ram_size((long *)PHYS_SDRAM_5, PHYS_SDRAM_7_SIZE) + get_ram_size((long *)PHYS_SDRAM_6, PHYS_SDRAM_7_SIZE) + get_ram_size((long *)PHYS_SDRAM_7, PHYS_SDRAM_7_SIZE) + get_ram_size((long *)PHYS_SDRAM_8, PHYS_SDRAM_8_SIZE); return 0; }
int dram_init(void) { gd->bd->bi_dram[0].start = PHYS_SDRAM; if (get_ram_size((long *) PHYS_SDRAM, PHYS_SDRAM_SIZE) != PHYS_SDRAM_SIZE) return -1; gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; return 0; }
static long int dram_size (long int mamr_value, long int *base, long int maxsize) { volatile immap_t *immr = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immr->im_memctl; memctl->memc_mamr = mamr_value; return (get_ram_size (base, maxsize)); }
/* * ATTENTION: Although partially referenced initdram does NOT make real use * use of CONFIG_SYS_SDRAM_BASE. The code does not work if * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000. */ phys_size_t initdram(int board_type) { ulong dramsize = 0; ulong dramsize2 = 0; uint svr, pvr; #if !defined(CONFIG_SYS_RAMBOOT) && \ (defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD)) ulong test1, test2; /* setup SDRAM chip selects */ out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e); /* 2GB at 0x0 */ out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */ /* setup config registers */ out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1); out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2); #ifdef SDRAM_DDR /* set tap delay */ out_be32((void *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY); #endif /* find RAM size using SDRAM CS0 only */ sdram_start(0); test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); sdram_start(1); test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); if (test1 > test2) { sdram_start(0); dramsize = test1; } else { dramsize = test2; } /* memory smaller than 1MB is impossible */ if (dramsize < (1 << 20)) dramsize = 0; /* set SDRAM CS0 size according to the amount of RAM found */ if (dramsize > 0) { out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x13 + __builtin_ffs(dramsize >> 20) - 1); } else {
void dram_init_banksize(void) { int i; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { gd->bd->bi_dram[i].start = kw_sdram_bar(i); gd->bd->bi_dram[i].size = get_ram_size((long *)kw_sdram_bar(i), kw_sdram_bs(i)); } }
void dram_init_banksize(void) { /* We should init the Dram options, and kernel get it by tag. */ int dram_size; int ret; ret = script_parser_fetch("dram_para", "dram_size", &dram_size, 1); if (!ret) { if (dram_size) { gd->bd->bi_dram[0].size = dram_size * 1024 * 1024; } else { gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); } } else { gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); } gd->bd->bi_dram[0].start = PHYS_SDRAM_1; }
void dram_init_banksize(void) { gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, \ PHYS_SDRAM_1_SIZE); // gd->bd->bi_dram[1].start = PHYS_SDRAM_2; // gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, \ // PHYS_SDRAM_2_SIZE); }
void sdram_init(void) { unsigned long ram_size; config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0); ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000); if (ram_size == 0x80000000 || ram_size == 0x40000000 || ram_size == 0x20000000) return; ddr3_emif_regs.sdram_config = 0x638453B2; config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0); ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000); if (ram_size == 0x08000000) return; hang(); }
void kw_sdram_size_adjust(enum memory_bank bank) { u32 size; /* probe currently equipped RAM size */ size = get_ram_size((void *)kw_sdram_bar(bank), kw_sdram_bs(bank)); /* adjust SDRAM window size accordingly */ kw_sdram_bs_set(bank, size); }